Inventor

CHUNG-HSING WANG

Inventor
TW

Overview

69→
Patents
2021–2026
Patent span
Electricity
Primary field (CPC H)

Patents· 69 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing33%
H10DInorganic electric semiconductor devices21%
H01LSemiconductor devices19%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H03KPulse technique3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
G01RMeasuring electric variables1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
H05KPrinted circuits1%
Y02PClimate change mitigation technologies in the production or processing of goods1%
PatentTitleYear
12,585,854Circuit cells having power grid stubs202612,578,386Scan chain control202612,462,086Integrated circuit having hybrid sheet structure202512,433,032Semiconductor structure including boundary header cell and method for manufacturing the same202512,380,265Integrated circuit and method of forming the same202512,353,816Structure and method of rectangular cell in semiconductor device202512,346,285Diagonal torus network202512,336,295Integrated circuit device and method202512,254,260Systems and methods for integrated circuit layout202512,243,821Conductive line structures and method of forming same202512,230,624Integrated circuit with mixed row heights202512,191,248Semiconductor arrangement and method of making202512,182,488Semiconductor device including standard-cell-adapted power grid arrangement202412,176,288Semiconductor device including frontside power mesh and backside power mesh and manufacturing method thereof202412,175,180Systems and methods for context aware circuit design202412,131,109Block level design method for heterogeneous PG-structure cells202412,112,117Method of manufacturing a semiconductor device including PG-aligned cells202412,107,048Layouts for conductive layers in integrated circuits202412,106,030Method of forming merged pillar structures and method of generating layout diagram of same202412,093,625Integrated circuit design method, system and computer program product202412,087,690Integrated circuit having a high cell density202412,086,522Method of generating netlist including proximity-effect-inducer (PEI) parameters202412,067,337Power grid, IC and method for placing power grid202412,039,242Structure and method of non-rectangular cell in semiconductor device202412,019,972Method and system of forming semiconductor device202412,008,302Integrated circuit with thicker metal lines on lower metallization layer202411,943,939Integrated circuit device and method202411,942,469Backside conducting lines in integrated circuits202411,935,833Method of forming power grid structures202411,929,331Routing structure202411,907,007Clock signal distribution system, integrated circuit device and method202411,908,853Integrated circuit and method of generating integrated circuit layout202411,893,333Hybrid sheet layout, method, system, and structure202411,861,284Conductor scheme selection and track planning for mixed-diagonal-manhattan routing202411,853,678Block level design method for heterogeneous PG-structure cells202311,816,413Systems and methods for context aware circuit design202311,809,803Method for evaluating failure-in-time202311,783,106Circuit testing and manufacture using multiple timing libraries202311,775,725System and computer program product for integrated circuit design202311,769,766Integrated circuit with mixed row heights202311,748,542Systems and methods for integrated circuit layout202311,727,183Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement202311,720,738Leakage analysis on semiconductor device202311,715,733Integrated circuit device and method202311,714,949Leakage analysis on semiconductor device202311,704,469Integrated circuit and method of forming the same202311,669,671Semiconductor device including PG-aligned cells and method of generating layout of same202311,669,669Circuit layouts and related methods202311,651,136Method and system of forming semiconductor device202311,600,568Layouts for conductive layers in integrated circuits202311,593,546Integrated circuit with thicker metal lines on lower metallization layer202311,574,108Block level design method for heterogeneous PG-structure cells202311,574,106Method, system, and storage medium of resource planning for designing semiconductor device202311,552,068Integrated circuit and method of generating integrated circuit layout202311,532,562Routing structure and method of forming the same202211,501,052Conductor scheme selection and track planning for mixed-diagonal-Manhattan routing202211,437,319Integrated circuit having a high cell density202211,366,951Method for evaluating failure-in-time202211,347,922Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement202211,282,829Integrated circuit with mixed row heights202211,251,124Power grid structures and method of forming the same202211,239,154Fishbone structure enhancing spacing with adjacent conductive line in power network202211,227,093Method and system of forming semiconductor device202211,211,327Via sizing for IR drop reduction202111,205,032Integrated circuit design method, system and computer program product202111,182,527Cell placement site optimization202111,176,303Constrained cell placement202111,176,305Method and system for sigma-based timing optimization202111,157,677Merged pillar structures and method of generating layout diagram of same2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (69)· patent assignee history
2021–2026Based in TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG CO LTD692021–2026
Locations
LocationPatentsSpan
TW692021–2026