Voltage supply circuit having an absorption unit and method for operating the same

The semiconductor integrated circuit (IC) industry has produced a wide variety of devices to address issues in a number of different areas. Some of these devices have differing power requirements. As ICs have become smaller and more complex, operating voltages continue to decrease for optimizing IC performance.

One or more embodiments are illustrated by way of example, and not by limitation, in the figures of the accompanying drawings, wherein elements having the same reference numeral designations represent like elements throughout. It is emphasized that, in accordance with standard practice in the industry various features may not be drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features in the drawings may be arbitrarily increased or reduced for clarity of discussion. One or more embodiments illustrated in the drawings, incorporated herein in their entirety, include the following:

FIG. 1 is a schematic diagram of a voltage supply unit in accordance with one or more embodiments;

FIG. 2 is a schematic diagram of a voltage supply unit in accordance with one or more embodiments;

FIG. 3 is a schematic diagram of a voltage supply unit in accordance with one or more embodiments;

FIG. 4 is a schematic diagram of a voltage supply unit in accordance with one or more embodiments;

FIG. 5 is a flow chart illustrating a method in accordance with one or more embodiments; and

FIG. 6 is a flow chart illustrating a method in accordance with one or more embodiments.

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosed subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are examples and are not intended to be limiting.

This description of the various embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. In the description, relative terms such as “before,” “after,” “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivative thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the system be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein components are attached to one another either directly or indirectly through intervening components, unless expressly described otherwise.

FIG. 1 is a schematic diagram of a voltage supply unit 100 in accordance with one or more embodiments. Voltage supply unit 100 comprises a regulator unit 102 , a cascode unit 104 , a first absorption unit 106 , a first current mirror 108 , a second absorption unit 110 , a voltage clamping unit 112 and resistors R 1 and R 2 . Voltage supply unit 100 is connected to voltage supply VDDQ and a load unit 120 . Voltage supply unit 100 is configured to receive a first input signal VREF 1 and voltage supply VDDQ. Voltage supply unit 100 is configured to send an output voltage signal VO to load unit 120 .

In some embodiments, output voltage signal VO is an intermediate voltage signal that is less than voltage supply VDDQ. In some embodiments, output voltage supply VO is an intermediate voltage signal that is greater than voltage supply VDDQ. In some embodiments, voltage supply VDDQ is a high-voltage supply greater than at least one of VDD or intermediate voltage signal VO. In some embodiments, voltage supply VDDQ is an integer multiple of VDD. In some embodiments, output voltage signal VO is substantially equal to VDD. In some embodiments, output voltage signal VO is an integer multiple of VDD, but less than voltage supply VDDQ. In some embodiments, voltage supply unit 100 is configured to generate an output voltage signal VO substantially equal to 2*VDD. In some embodiments, a low-voltage level refers to a voltage level less than voltage supply VDDQ and intermediate voltage signal VO. In some embodiments, VDD is characterized as a low-voltage level. In some embodiments, ground is characterized as a low-voltage level. In some embodiments, VDD is a voltage ranging from about 0.6 volts to about 1.2 volts. In some embodiments, voltage supply VDDQ is substantially equal to 2.5 volts. In some embodiments, voltage supply VDDQ is substantially equal to 3.3 volts. In some embodiments, voltage supply VDDQ is substantially equal to 5.0 volts.

In some embodiments, one or more of the semiconductor devices contained in voltage supply unit 100 comprise FinFET or Tri-gate devices. In some embodiments, one or more of the semiconductor devices contained in voltage supply unit 100 are produced by a 10 nanometer (nm), 14 nm or 16 nm semiconductor manufacturing process. In some embodiments, one or more of the semiconductor devices contained in voltage supply unit 100 are produced by a 65 nm or 90 nm semiconductor manufacturing process. In some embodiments, one or more of the semiconductor devices contained in voltage supply unit 100 comprise thin-gate devices or low-voltage devices. In some embodiments, a thin-gate device comprises one or more semiconductor devices in an integrated circuit where the equivalent oxide thickness of the one or more semiconductor devices is less than the equivalent oxide thickness of other semiconductor devices contained in the integrated circuit. In some embodiments, a low-voltage device comprises a semiconductor device in an integrated circuit where the Vdd of the semiconductor device is less than the Vdd of other semiconductor devices contained in the integrated circuit.

In some embodiments, for a 10 nm semiconductor manufacturing process, a thin-gate device comprises a semiconductor device with an equivalent oxide thickness ranging from about 5 angstroms (Å) to about 8 Å. In some embodiments, for a 10 nm semiconductor manufacturing process, a low-voltage device comprises a semiconductor device with a Vdd ranging from about 0.7 volts to about 0.9 volts.

In some embodiments, for a 16/14 nm semiconductor manufacturing process, a thin-gate device comprises a semiconductor device with an equivalent oxide thickness ranging from about 7 Å to about 10 Å. In some embodiments, for a 16/14 nm semiconductor manufacturing process, a low-voltage device comprises a semiconductor device with a Vdd ranging from about 0.8 volts to about 0.95 volts.

In some embodiments, for a 22/20 nm semiconductor manufacturing process, a thin-gate device comprises a semiconductor device with an equivalent oxide thickness ranging from about 8 Å to about 11 Å. In some embodiments, for a 22/20 nm semiconductor manufacturing process, a low-voltage device comprises a semiconductor device with a Vdd ranging from about 0.85 volts to about 1.0 volts.

In some embodiments, for a 32/28 nm semiconductor manufacturing process, a thin-gate device comprises a semiconductor device with an equivalent oxide thickness ranging from about 9 Å to about 12 Å. In some embodiments, for a 32/28 nm semiconductor manufacturing process, a low-voltage device comprises a semiconductor device with a Vdd ranging from about 0.9 volts to about 1.05 volts.

In some embodiments, for a 45/40 nm semiconductor manufacturing process, a thin-gate device comprises a semiconductor device with an equivalent oxide thickness ranging from about 10 Å to about 15 Å. In some embodiments, for a 45/40 nm semiconductor manufacturing process, a low-voltage device comprises a semiconductor device with a Vdd ranging from about 1.0 volts to about 1.1 volts.

In some embodiments, for a 65 nm semiconductor manufacturing process, a thin-gate device comprises a semiconductor device with an equivalent oxide thickness ranging from about 11 Å to about 16 Å. In some embodiments, for a 65 nm semiconductor manufacturing process, a low-voltage device comprises a semiconductor device with a Vdd ranging from about 1.1 volts to about 1.2 volts.

In some embodiments, for a 90 nm semiconductor manufacturing process, a thin-gate device comprises a semiconductor device with an equivalent oxide thickness ranging from about 12 Å to about 20 Å. In some embodiments, for a 90 nm semiconductor manufacturing process, a low-voltage device comprises a semiconductor device with a Vdd ranging from about 1.2 volts to about 1.5 volts.

Regulator unit 102 is connected to cascode unit 104 , resistor R 1 and resistor R 2 . Regulator unit 102 is configured to receive a first input signal VREF 1 and a second input signal VFB. Regulator unit 102 is configured to provide a bias voltage to an n-type metal oxide semiconductor (NMOS) transistor N 1 and to control a source current I 1 received from cascode unit 104 .

Regulator unit 102 comprises operational amplifier OP 1 , NMOS transistor N 1 and capacitor C 1 . Operational amplifier OP 1 is configured to receive first input signal VREF 1 and second input signal VFB. The first input signal VREF 1 is a reference voltage at the non-inverting terminal of the operational amplifier OP 1 . The second input signal VFB is a voltage at the inverting terminal of the operational amplifier OP 1 . Operational amplifier OP 1 is configured to send an output signal to NMOS transistor N 1 and capacitor C 1 . The output signal of the operational amplifier OP 1 is a voltage applied to the gate of NMOS transistor N 1 and capacitor C 1 . The operational amplifier OP 1 includes two input terminals and one output terminal. The first input terminal of the operational amplifier OP 1 is connected to the source of the first input signal VREF 1 . The second input terminal of the operational amplifier OP 1 is connected to the source of the second input signal VFB. In some embodiments, operational amplifier OP 1 is configured in a negative feedback configuration such that the source of the second input signal VFB is connected to resistors R 1 and R 2 at node FB. The output of the operational amplifier OP 1 is connected to NMOS transistor N 1 and capacitor C 1 . In some embodiments, operational amplifier OP 1 is configured in a comparator configuration. In some embodiments, operational amplifier OP 1 includes a comparator device. In some embodiments, a p-type metal oxide semiconductor (PMOS transistor) is used in regulator unit 102 .

The gate of NMOS transistor N 1 is connected to operational amplifier OP 1 and is configured to receive the output signal of the operational amplifier OP 1 . The drain of NMOS transistor N 1 is connected to cascode unit 104 (by the source of NMOS transistor N 2 ). The source of NMOS transistor N 1 is connected to ground. The regulator unit 102 is configured to maintain the gate voltage of NMOS transistor N 1 , which controls the source current I 1 received from cascode unit 104 . In some embodiments, given a first input signal VREF 1 and a second signal VFB, the regulator unit 102 is configured to control the gate voltage of NMOS transistor N 1 . The gate voltage of NMOS transistor N 1 controls the source current I 1 received from cascode unit 104 . In some embodiments, the output voltage signal VO of voltage supply unit 100 is fed back to the operational amplifier OP 1 by node FB and is compared with the first input signal VREF 1 to provide a desired supply voltage (output voltage signal VO).

Capacitor C 1 is connected to the gate of NMOS transistor N 1 , the output of operational amplifier OP 1 and ground.

Cascode unit 104 is connected to regulator unit 102 , first absorption unit 106 and voltage clamping unit 112 . Cascode unit 104 is connected to voltage clamping unit 112 by node VC. Cascode unit 104 is configured to receive a first bias signal B 1 , a second bias signal B 2 , source current I 1 and a clamp voltage from node VC. Cascode unit 104 is configured to send source current I 1 to regulator unit 102 . Cascode unit 104 comprises NMOS transistor N 2 and NMOS transistor N 3 . In some embodiments, cascode unit 104 prevents electrical over stress (EOS) in voltage supply unit 100 . In some embodiments, one or more PMOS transistors are used in cascode unit 104 .

The gate of NMOS transistor N 2 is connected to the source of first bias signal B 1 . In some embodiments, first bias signal B 1 is a bias voltage received from a bias generation circuit (not shown). In some embodiments, first bias signal B 1 is a bias voltage substantially equal to VDD and is received from a bias generation circuit (not shown). The drain of NMOS transistor N 2 is connected to the source of NMOS transistor N 3 and to voltage clamping unit 112 (by the drain of PMOS diode-connected transistor P 8 ). In some embodiments, voltage clamping unit 112 reduces EOS in NMOS transistors N 2 and N 3 . In some embodiments, voltage clamping unit 112 is configured to clamp the voltage at node VC at a first intermediate voltage. In some embodiments, the first intermediate voltage is substantially equal to a voltage ranging between about the first bias signal B 1 and about the second bias signal B 2 . In some embodiments, the first intermediate voltage is substantially equal to a voltage ranging between about VDD and about 2*VDD. In some embodiments, the first intermediate voltage is substantially equal to a voltage of about 1.5*VDD. The source of NMOS transistor N 2 is connected to the drain of NMOS transistor N 1 . In some embodiments, the voltage clamping unit 112 is implemented with more than one PMOS diode-connected transistors. In some embodiments, the voltage clamping unit 112 is implemented with one or more NMOS diode-connected transistors.

The gate of NMOS transistor N 3 is connected to the source of second bias signal B 2 . In some embodiments, second bias signal B 2 is a bias voltage received from a bias generation circuit (not shown). In some embodiments, second bias signal B 2 is a bias voltage substantially equal to 2*VDD and is received from a bias generation circuit (not shown). The drain of NMOS transistor N 3 is connected to first absorption unit 106 (by the drain of PMOS transistor P 4 ). The source of NMOS transistor N 3 is connected to the drain of NMOS transistor N 2 and to voltage clamping unit 112 (by the drain of NMOS transistor N 4 ). In some embodiments, voltage clamping unit 112 reduces EOS in NMOS transistors N 2 and N 3 . In some embodiments, voltage clamping unit 112 is configured to clamp the voltage at node VC at a first intermediate voltage. In some embodiments, the first intermediate voltage is substantially equal to a voltage ranging between about the first bias signal B 1 and about the second bias signal B 2 . In some embodiments, the first intermediate voltage is substantially equal to a voltage ranging between about VDD and about 2*VDD. In some embodiments, the first intermediate voltage is substantially equal to a voltage of about 1.5*VDD. The body of NMOS transistor N 3 is connected to the source of NMOS transistor N 3 .

First absorption unit 106 is connected to cascode unit 104 and first current mirror 108 . First absorption unit 106 is configured to receive a source current I 1 from first current mirror 108 . First absorption unit 106 is configured to send source current I 1 to cascode unit 104 . First absorption unit 106 comprises PMOS transistor P 3 and PMOS transistor P 4 . In some embodiments, first absorption unit 106 is configured to absorb one or more voltage drops from the voltage supply VDDQ. In some embodiments, one or more NMOS transistors are used in first absorption unit 106 .

The source of PMOS transistor P 3 is connected to first current mirror 108 (by the drain of PMOS transistor P 2 ) and is configured to receive the source current I 1 . The body of PMOS transistor P 3 is connected to the source of PMOS transistor P 3 . PMOS transistor P 3 is connected in a diode configuration such that the gate of PMOS transistor P 3 is connected to the drain of PMOS transistor P 3 . The drain and gate of PMOS transistor P 3 are connected to the source of PMOS transistor P 4 . The drain of PMOS transistor P 3 is configured to send the source current I 1 to PMOS transistor P 4 .

The source of PMOS transistor P 4 is connected to the drain of PMOS transistor P 3 and is configured to receive the source current I 1 . The body of PMOS transistor P 4 is connected to the source of PMOS transistor P 4 . PMOS transistor P 4 is connected in a diode configuration such that the gate of PMOS transistor P 4 is connected to the drain of PMOS transistor P 4 . The drain and gate of PMOS transistor P 4 are connected to the drain of NMOS transistor N 3 . The drain of PMOS transistor P 4 is configured to send the source current I 1 to NMOS transistor N 3 .

First current mirror 108 is connected to first absorption unit 106 and second absorption unit 110 . First current mirror 108 is configured to receive a source current I 1 from voltage supply VDDQ. First current mirror 108 is configured to send a source current I 1 to first absorption unit 106 and to send a supply current I 2 to second absorption unit 110 . In some embodiments, the supply current I 2 is mirrored from the source current I 1 . For example, source current I 1 is used to set the gate voltage of PMOS transistors P 2 and P 1 ; and the gate voltage of PMOS transistor P 1 is used to set the supply current I 2 . In some embodiments, one or more NMOS transistors are used in first current mirror 108 .

The source of PMOS transistor P 2 is connected to voltage supply VDDQ and is configured to receive the source current I 1 . The body of PMOS transistor P 2 is connected to the source of PMOS transistor P 2 . The gate of PMOS transistor P 2 is connected to the gate of PMOS transistor P 1 . PMOS transistor P 2 is connected in a diode configuration such that the gate of PMOS transistor P 2 is connected to the drain of PMOS transistor P 2 . The drain and gate of PMOS transistor P 2 are connected to the source of PMOS transistor P 3 . The drain of PMOS transistor P 2 is configured to send the source current I 1 to the source of PMOS transistor P 3 .

The source of PMOS transistor P 1 is connected to voltage supply VDDQ and is configured to receive the supply current I 2 . The body of PMOS transistor P 1 is connected to the source of PMOS transistor P 1 . The gate of PMOS transistor P 1 is connected to the gate of PMOS transistor P 2 . The drain of PMOS transistor P 1 is connected to second absorption unit 110 (by the source of PMOS transistor P 5 ). The drain of PMOS transistor P 1 is configured to send the supply current I 2 to the source of PMOS transistor P 5 .

Second absorption unit 110 is connected to first current mirror 108 , voltage clamping unit 112 , resistor R 1 and load unit 120 . Second absorption unit 110 is configured to receive a supply current I 2 from first current mirror 108 . Second absorption unit 110 is configured to send supply current I 2 to load unit 120 and resistor R 1 . Second absorption unit 110 comprises PMOS transistor P 5 . In some embodiments, second absorption unit 110 comprises more than one PMOS transistor P 5 . In some embodiments, second absorption unit 110 is configured to absorb one or more voltage drops from the voltage supply VDDQ. In some embodiments, one or more NMOS transistors are used in second absorption unit 110 . In some embodiments, second absorption unit 110 is optional. In some embodiments, second absorption unit 110 is not used where supply voltage VDDQ is substantially equal to 3*VDD and the output voltage VO is substantially equal to 2*VDD. In some embodiments, second absorption unit 110 is not used where the difference between supply voltage VDDQ and the output voltage VO is substantially equal to or less than VDD.

The source of PMOS transistor P 5 is connected to first current mirror 108 and is configured to receive the supply current I 2 . The body of PMOS transistor P 5 is connected to the source of PMOS transistor P 5 . PMOS transistor P 5 is connected in a diode configuration such that the gate of PMOS transistor P 5 is connected to the drain of PMOS transistor P 5 . The drain and gate of PMOS transistor P 5 are connected to the source of NMOS transistor N 4 , resistor R 1 and load unit 120 . The drain of PMOS transistor P 5 is configured to send the supply current I 2 to load unit 120 and resistor R 1 .

Voltage clamping unit 112 is connected to second absorption unit 110 , resistor R 1 , load unit 120 and cascode unit 104 . Voltage clamping unit 112 comprises a diode-connected PMOS transistor P 8 . In some embodiments, voltage clamping unit 112 reduces EOS in NMOS transistors N 2 and N 3 . In some embodiments, voltage clamping unit 112 is configured to clamp the voltage at node VC at a first intermediate voltage. In some embodiments, the first intermediate voltage is substantially equal to a voltage ranging between about the first bias signal B 1 and about the second bias signal B 2 . In some embodiments, the first intermediate voltage is substantially equal to a voltage ranging between about VDD and about 2*VDD. In some embodiments, the first intermediate voltage is substantially equal to a voltage of about 1.5*VDD. The source of NMOS transistor N 2 is connected to the drain of NMOS transistor N 1 . In some embodiments, the voltage clamping unit 112 is implemented with more than one PMOS diode-connected transistors. In some embodiments, the voltage clamping unit 112 is implemented with one or more NMOS diode-connected transistors. In some embodiments, voltage clamping unit 112 is optional.

The source of PMOS transistor P 8 is connected to second absorption unit 110 , resistor R 1 and load unit 120 . The body of PMOS transistor P 8 is connected to the source of PMOS transistor P 8 . PMOS transistor P 8 is connected in a diode configuration such that the gate of PMOS transistor P 8 is connected to the drain of PMOS transistor P 8 . The drain and gate of PMOS transistor P 8 are connected to the drain of NMOS transistor N 2 and the source of NMOS transistor N 3 .

Resistor R 1 is connected to resistor R 2 , second absorption unit 110 , voltage clamping unit 112 , load unit 120 and regulator unit 102 . Resistor R 1 is connected to resistor R 2 and regulator unit 102 by node FB. In some embodiments, resistor R 1 and resistor R 2 form an adjustable voltage divider unit. Current I 2 b flows through resistor R 1 . Resistor R 1 and R 2 form an adjustable voltage divider 114 .

Resistor R 2 is connected to resistor R 1 , regulator unit 102 and ground. One end of Resistor R 2 is connected to resistor R 1 and regulator unit 102 by node FB. Another end of resistor R 2 is connected to ground. In some embodiments, resistor R 2 and resistor R 1 form an adjustable voltage divider unit. Current I 2 b flows through resistor R 2 . In some embodiments, resistor R 2 is configured to be a variable resistor. In some embodiments, resistor R 2 and resistor R 1 form an adjustable voltage divider unit since resistor R 2 is configured to be a variable resistor. For example, the voltage at node FB is represented by formula 1:

V FB =VO*R 2/ R 1+ R 2  (1)

Where V FB is the voltage at node FB, VO is the output voltage signal VO of voltage supply unit 100 , R 1 is the value of resistor R 1 and R 2 is the value of resistor R 2 .

As seen from formula 1, the value of resistor R 2 controls the voltage V FB at node FB. In some embodiments, resistor R 2 controls the amount of voltage V FB fed back to the regulator unit 102 . In some embodiments, by adjusting the value of resistor R 2 , the amount of voltage V FB fed back to the regulator unit 102 is also adjusted.

Voltage supply unit 100 is configured to output voltage signal VO to load unit 120 . Voltage supply unit 100 is configured to output current I 2 a to load unit 120 . In some embodiments, output voltage signal VO is an intermediate voltage signal less than voltage supply VDDQ. In some embodiments, voltage supply VDDQ is an integer multiple of VDD.

Load unit 120 comprises load unit 120 a , load unit 120 b , load unit 120 c , and load capacitor CL. In some embodiments, load units 120 a , 120 b and 120 c are load units configured with substantially different input voltage requirements, and voltage supply unit 100 is capable of providing the substantially different voltage requirements of load unit 120 . In some embodiments, load units 120 a , 120 b and 120 c are load units configured with substantially the same input voltage requirements and voltage supply unit 100 is capable of providing the substantially similar voltage requirements of load unit 120 . In some embodiments, voltage supply VDDQ is substantially equal to 3*VDD, and the voltage of load line L is substantially equal to 2*VDD.

Load unit 120 a is connected to VDDQ and load line L. In some embodiments, the voltage of load line L is substantially equal to 2*VDD.

Load unit 120 b is connected to VDDC and load line L. In some embodiments, the voltage of load line L is substantially equal to 2*VDD. In some embodiments, voltage supply VDDC is substantially equal to VDD.

Load unit 120 c is connected to load line L and ground. In some embodiments, the voltage of load line L is substantially equal to 2*VDD.

Load capacitor CL is connected to load line L and ground. In some embodiments, the voltage of load line L is substantially equal to 2*VDD.

FIG. 2 is a schematic diagram of a voltage supply unit 200 in accordance with one or more embodiments. Voltage supply unit 200 is an embodiment of the voltage supply unit 100 shown in FIG. 1 . As shown in FIG. 2 , similar elements have a same reference number as shown in FIG. 1 . In comparison with voltage supply unit 100 (shown in FIG. 1 ), voltage supply unit 200 also includes a third absorption unit 202 , NMOS transistor N 6 and a second current mirror 204 . In some embodiments, third absorption unit 202 , NMOS transistor N 6 and a second current mirror 204 provide stability to voltage supply unit 200 during low-load or no-load conditions.

Third absorption unit 202 is connected to second absorption unit 110 , voltage clamping unit 112 , resistor R 1 and load unit 120 by load line L. Third absorption unit 202 is also connected to NMOS transistor N 6 . Third absorption unit 202 is configured to receive a current I 3 from load line L. Third absorption unit 202 is configured to send current I 3 to NMOS transistor N 6 . Third absorption unit 202 comprises PMOS transistor P 6 and PMOS transistor P 7 . In some embodiments, third absorption unit 202 is configured to absorb one or more voltage drops from the load line L. In some embodiments, one or more NMOS transistors are used in third absorption unit 202 .

The source of PMOS transistor P 6 is connected to second absorption unit 110 , voltage clamping unit 112 , resistor R 1 and load unit 120 by load line L and is configured to receive current I 3 . The body of PMOS transistor P 6 is connected to the source of PMOS transistor P 6 . PMOS transistor P 6 is connected in a diode configuration such that the gate of PMOS transistor P 6 is connected to the drain of PMOS transistor P 6 . The drain and gate of PMOS transistor P 6 are connected to the source of PMOS transistor P 7 . The drain of PMOS transistor P 6 is configured to send the current I 3 to PMOS transistor P 7 .

The source of PMOS transistor P 7 is connected to the drain of PMOS transistor P 6 and is configured to receive the current I 3 . The body of PMOS transistor P 7 is connected to the source of PMOS transistor P 7 . PMOS transistor P 7 is connected in a diode configuration such that the gate of PMOS transistor P 7 is connected to the drain of PMOS transistor P 7 . The drain and gate of PMOS transistor P 7 are connected to the drain of NMOS transistor N 6 . The drain of PMOS transistor P 7 is configured to send the current I 3 to NMOS transistor N 6 .

The gate of NMOS transistor N 6 is connected to the source of third bias signal B 3 . In some embodiments, third bias signal B 3 is a bias voltage received from a bias generation circuit (not shown). In some embodiments, third bias signal B 3 is a bias voltage substantially equal to VDD and is received from a bias generation circuit (not shown). The drain of NMOS transistor N 6 is connected to third absorption unit 202 (by the drain of PMOS transistor P 7 ). In some embodiments, NMOS transistor N 6 reduces EOS in third absorption unit 202 and second current mirror 204 . The source of NMOS transistor N 6 is connected to the drain of NMOS transistor N 5 .

Second current mirror 204 is connected to NMOS transistor N 6 . Second current mirror 204 is configured to receive a current from current source CS 1 and voltage supply VDD. Second current mirror 204 is configured to receive a current I 3 from NMOS transistor N 6 and third absorption unit 202 . In some embodiments, the current I 3 is mirrored from the current received from the current source CS 1 . For example, current received from the current source CS 1 is used to set the gate voltage of NMOS transistors N 7 and N 5 ; and the gate voltage of NMOS transistor N 5 is used to set the value of current I 3 . In some embodiments, one or more PMOS transistors are used in second current mirror 204 .

Current source CS 1 is connected to voltage supply VDD, the drain of NMOS transistor N 7 and resistor Rb. Current source CS 1 is configured to provide a reference electric current for second current mirror 204 .

The drain of NMOS transistor N 7 is configured to receive current from current source CS 1 . The gate of NMOS transistor N 7 is connected to the gate of NMOS transistor N 5 (by resistor Rb). NMOS transistor N 7 is connected in a diode configuration such that the gate of NMOS transistor N 7 is connected to the drain of NMOS transistor N 7 . The source of NMOS transistor N 7 is connected to ground.

Resistor Rb is connected to current source CS 1 , the gate and drain of NMOS transistor N 7 , the gate of NMOS transistor N 5 , and capacitor C 2 . In some embodiments, resistor Rb and capacitor C 2 form a low pass filter to filter the signal received from NMOS transistor N 7 and current source CS 1 .

Capacitor C 2 is connected to the gate of NMOS transistor N 5 and resistor Rb.

The drain of NMOS transistor N 5 is configured to receive the current I 3 from the source of NMOS transistor N 6 . The gate of NMOS transistor N 5 is connected to the gate of NMOS transistor N 7 (by resistor Rb). The source of NMOS transistor N 5 is connected to ground. In some embodiments, during a high-load condition, NMOS transistor N 5 is slightly biased and adjusts the current I 3 . In some embodiments, during a low-load condition, NMOS transistor N 5 is heavily biased and adjusts the current I 3 . In some embodiments, during a no-load condition, NMOS transistor N 5 is heavily biased and adjusts the current I 3 . In some embodiments, during a low-load or no-load condition, NMOS transistor N 5 is a stability enhancement device by controlling the current I 3 .

FIG. 3 is a schematic diagram of a voltage supply unit 300 in accordance with one or more embodiments. Voltage supply unit 300 is an embodiment of the voltage supply unit 200 shown in FIG. 2 . As shown in FIG. 3 , similar elements have a same reference number as shown in FIG. 2 . In comparison with voltage supply unit 200 (shown in FIG. 2 ), voltage supply unit 300 includes first absorption unit 306 in place of first absorption unit 106 . In comparison with voltage supply unit 200 (shown in FIG. 2 ), voltage supply unit 300 includes voltage clamping unit 312 in place of voltage clamping unit 112 .

First absorption unit 306 is connected to cascode unit 104 and first current mirror 108 . First absorption unit 306 is configured to receive a source current I 1 from first current mirror 108 . First absorption unit 306 is configured to send source current I 1 to cascode unit 104 . First absorption unit 306 comprises diode D 1 and diode D 2 . In some embodiments, first absorption unit 306 is configured to absorb one or more voltage drops from the voltage supply VDDQ.

The anode of diode D 1 is connected to first current mirror 108 (by the drain of PMOS transistor P 2 ) and is configured to receive the source current I 1 . The cathode of diode D 1 is configured to send the source current I 1 to the anode of diode D 2 .

The anode of diode D 2 is connected to the cathode of diode D 1 and is configured to receive the source current I 1 . The cathode of D 2 is configured to send the source current I 1 to NMOS transistor N 3 .

Voltage clamping unit 312 is connected to second absorption unit 110 , resistor R 1 , load unit 120 and cascode unit 104 . Voltage clamping unit 312 comprises diode D 3 . In some embodiments, voltage clamping unit 312 reduces EOS in NMOS transistors N 2 and N 3 . In some embodiments, voltage clamping unit 312 is configured to clamp the voltage at node VC at a first intermediate voltage. In some embodiments, the first intermediate voltage is substantially equal to a voltage ranging between about the first bias signal B 1 and about the second bias signal B 2 . In some embodiments, the first intermediate voltage is substantially equal to a voltage ranging between about VDD and about 2*VDD. In some embodiments, the first intermediate voltage is substantially equal to a voltage of about 1.5*VDD. The source of NMOS transistor N 2 is connected to the drain of NMOS transistor N 1 . In some embodiments, voltage clamping unit 312 is optional.

FIG. 4 is a schematic diagram of a voltage supply unit 400 in accordance with one or more embodiments. Voltage supply unit 400 is an embodiment of the voltage supply unit 100 shown in FIG. 1 . As shown in FIG. 4 , similar elements have a same reference number as shown in FIG. 1 . In comparison with voltage supply unit 100 (shown in FIG. 1 ), voltage supply unit 400 does not include voltage clamping unit 112 . In comparison with voltage supply unit 100 (shown in FIG. 1 ), voltage supply unit 400 includes cascode unit 404 in place of cascode unit 104 . In comparison with voltage supply unit 100 (shown in FIG. 1 ), voltage supply unit 400 includes first absorption unit 406 in place of first absorption unit 106 . In comparison with voltage supply unit 100 (shown in FIG. 1 ), voltage supply unit 400 includes second absorption unit 410 in place of second absorption unit 110 .

In comparison with voltage supply unit 100 (shown in FIG. 1 ), voltage supply unit 400 is configured to generate output voltage signal VO as represented by formula 2:

VO=X*VDD   (2)

Where VO is the output voltage signal VO of voltage supply unit 400 , X is a positive number and VDD is a voltage supply. In some embodiments, X is an integer.

Cascode unit 404 includes three or more NMOS transistor devices N 11 , . . . N 1 X (where X is an integer corresponding to the number of NMOS transistor devices) connected in the same configuration as that shown in FIG. 1 . In comparison with cascode unit 104 (shown in FIG. 1 ), cascode unit 404 does not include voltage clamping unit 112 . Each of the NMOS transistor devices N 11 , . . . N 1 X are configured to receive a corresponding bias signal B 1 , . . . a Xth bias signal B 1 X. In some embodiments, the function of the cascode unit 404 is the same as cascode unit 104 (shown in FIG. 1 ). As shown in equation 2, the value of integer X determines the number of NMOS transistor devices N 11 , . . . N 1 X and bias input signals B 11 , . . . B 1 X in cascode unit 400 .

In some embodiments, if the integer X is equal to 3, then the output voltage signal VO is substantially equal to 3*VDD and three NMOS transistors N 11 , N 12 and N 13 are used in cascode unit 404 .

In this example, the first intermediate voltage between NMOS transistor N 11 and N 12 is substantially equal to a voltage ranging between about the first bias signal B 11 and about the second bias signal B 12 . In some embodiments, the first intermediate voltage is substantially equal to a voltage ranging between about VDD and about 2*VDD. In some embodiments, the first intermediate voltage is substantially equal to a voltage of about 1.5*VDD. In this example, the second intermediate voltage between NMOS transistor N 12 and N 13 is substantially equal to a voltage ranging between about the second bias signal B 12 and about the third bias signal B 13 . In some embodiments, the second intermediate voltage is substantially equal to a voltage ranging between about 2*VDD and about 3*VDD. In some embodiments, the second intermediate voltage is substantially equal to a voltage of about 2.5*VDD. In some embodiments, cascode unit 404 prevents electrical over stress (EOS) in voltage supply unit 400 . In some embodiments, one or more PMOS transistors are used in cascode unit 404 .

First absorption unit 406 includes diode devices D 11 , . . . D 1 n (where n is an integer corresponding to the number of diode devices) in place of PMOS transistors P 3 and P 4 .

The anode of diode D 11 is connected to first current mirror 108 (by the drain of PMOS transistor P 2 ) and is configured to receive the source current I 1 . The cathode of diode D 11 is configured to send the source current I 1 to the anode of diode D 1 n.

The anode of diode D 1 n is connected to the cathode of diode D 11 and is configured to receive the source current I 1 . The cathode of diode D 1 n is configured to send the source current I 1 to NMOS transistor N 1 X.

In some embodiments, the function of the first absorption unit 406 is the same as first absorption unit 106 (shown in FIG. 1 ). In some embodiments, first absorption unit 406 is configured to absorb one or more voltage drops from the voltage supply VDDQ. For example, where VDDQ is substantially equal to 4*VDD, and output voltage signal VO is substantially equal to 2*VDD, then the integer n is equal to 3 or 4 such that first absorption unit 406 includes 3 diodes (D 11 , D 12 and D 13 ) or 4 diodes (D 11 , D 12 , D 13 and D 14 ). For example, where VDDQ is substantially equal to 3*VDD, and output voltage signal VO is substantially equal to 2*VDD, then the integer n is equal to 2 or 3 such that first absorption unit 406 includes 2 diodes (D 11 and D 12 ) or 3 diodes (D 11 , D 12 and D 13 ).

Second absorption unit 410 includes diode devices D 21 , . . . D 2 m (where m is an integer corresponding to the number of diode devices) in place of PMOS transistor P 5 .

The anode of diode D 21 is connected to first current mirror 108 (by the drain of PMOS transistor P 1 ) and is configured to receive the supply current I 2 . The cathode of diode D 21 is configured to send the supply current I 2 to the anode of diode D 2 m.

The anode of diode D 2 m is connected to the cathode of diode D 21 and is configured to receive the supply current I 2 . The cathode of diode D 2 m is configured to send the supply current I 2 to load unit 120 and resistor R 1 .

In some embodiments, the function of the second absorption unit 410 is the same as second absorption unit 110 (shown in FIG. 1 ). In some embodiments, second absorption unit 410 is configured to absorb one or more voltage drops from the voltage supply VDDQ and to reduce EOS on PMOS transistor P 1 . For example, where VDDQ is substantially equal to 4*VDD, and output voltage signal VO is substantially equal to 2*VDD, then the integer n is equal to 3 or 4 such that second absorption unit 410 includes 3 diodes (D 21 , D 22 and D 23 ) or 4 diodes (D 21 , D 22 , D 23 and D 24 ). For example, where VDDQ is substantially equal to 3*VDD, and output voltage signal VO is substantially equal to 2*VDD, then the integer n is equal to 2 or 3 such that second absorption unit 410 includes 2 diodes (D 21 and D 22 ) or 3 diodes (D 21 , D 22 and D 23 ).

FIG. 5 is a flow chart illustrating a method 500 of generating an intermediate voltage level from a high voltage level in a voltage supply unit in accordance with one or more embodiments. Method 500 begins with operation 502 in which a first current signal of a current mirror is controlled by a first operating voltage of a regulator unit.

In operation 504 , a first voltage drop and a second voltage drop from the high voltage level are absorbed. In some embodiments, the first voltage drop is absorbed by a first P-type transistor and the second voltage drop is absorbed by a second P-type transistor.

In operation 506 , the electrical over stress in the voltage supply unit is reduced by controlling a first bias voltage of a first N-type transistor and controlling a second bias voltage of a second N-type transistor.

In operation 508 , the electrical over stress in the first N-type transistor and the second N-type transistor are reduced by clamping a voltage level between the first N-type transistor and the second N-type transistor to an intermediate biasing voltage level. In some embodiments, the intermediate biasing voltage level is between the first bias voltage and the second bias voltage.

In operation 510 , a first operating voltage of the current mirror is controlled by the first current signal.

In operation 512 , a second operating voltage of the current mirror is controlled by the first operating voltage of the current mirror.

In operation 514 , a second current signal of the current mirror is controlled by the second operating voltage of the current mirror.

In operation 516 , a feedback voltage signal is controlled by an adjustable voltage divider.

FIG. 6 is a flow chart illustrating a method 600 of controlling a first operating voltage of a regulator unit in accordance with one or more embodiments. Method 600 is an embodiment of operation 502 shown in method 500 . Method 600 begins with operation 602 in which a first voltage signal is received. In some embodiments, the first voltage signal is a reference voltage.

In operation 604 , a second voltage signal is received. In some embodiments, the second voltage signal is substantially equal to the feedback voltage signal.

In operation 606 , the first operating voltage of the regulator unit is sent.

One aspect of this description relates to a voltage supply unit comprising a regulator unit, a voltage divider and a first current mirror. The regulator unit is configured to receive a first voltage signal and a second voltage signal, and is configured to generate a third voltage signal. The voltage divider is connected between the first current mirror and the regulator unit, and the voltage divider controls the second voltage signal. The first current mirror is connected to the regulator unit, an input voltage supply and the voltage divider. The first current mirror is configured to generate a first current signal and a second current signal, the second current signal is mirrored from the first current signal, the first current signal is controlled by the third voltage signal and the second current signal controls an output voltage supply signal.

Another aspect of this description relates a voltage supply unit comprising a regulator unit, an adjustable voltage divider and a first current mirror. The regulator unit is configured to receive a first voltage signal and a second voltage signal, and is configured to generate a third voltage signal. The adjustable voltage divider is connected between the first current mirror and the regulator unit, and the adjustable voltage divider controls the second voltage signal. The first current mirror is connected to the regulator unit, an input voltage supply and the adjustable voltage divider. Further, the first current mirror is configured to generate a first current signal and a second current signal, the second current signal is mirrored from the first current signal, the first current signal is controlled by the third voltage signal, and the second current signal controls an output voltage supply signal.

Still another aspect of this description relates to a method of generating an output voltage level from an input voltage level in a voltage supply unit, the method comprising controlling a first current signal of a current mirror by a first operating voltage of a regulator unit, controlling a first operating voltage of the current mirror by the first current signal, controlling a second operating voltage of the current mirror by the first operating voltage of the current mirror, controlling a second current signal of the current mirror by the second operating voltage of the current mirror and controlling a feedback voltage signal by an adjustable voltage divider, wherein the output voltage level is less than the input voltage level.

It will be readily seen by one of ordinary skill in the art that the disclosed embodiments fulfill one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents and various other embodiments as broadly disclosed herein. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.