LexDanaLexDanabeta
Inventor

Chih-Chang Lin

Inventor
San Jose, CA, US

Overview

116→
Patents
2004–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 116 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary
H03KPulse technique23%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses12%
G06FElectric digital data processing10%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems7%
G11CStatic stores6%
H04LTransmission of digital information, e.g. telegraphic communication6%
G05FSystems for regulating electric or magnetic variables5%
H03FAmplifiers5%
H10DInorganic electric semiconductor devices4%
H01LSemiconductor devices2%
PatentTitleYear
10,855,280Input/output circuit and method202010,778,203Clock generation circuit and charge pumping system202010,686,434Input/output circuit202010,673,437Level shifting circuit and method202010,546,528Pixel circuit and method of adjusting brightness of pixel circuit202010,536,146Edge detector circuit and method202010,483,954Clock generation circuit and charge pumping system201910,401,889Current generator and method of operating201910,367,491Delay line circuit and method of operating the same201910,355,682Clock generation circuit and charge pumping system201910,298,237Level shifting circuit, apparatus and method of operating the same201910,187,046Input/output circuit201910,177,764Input/output circuit20199,998,103Delay line circuit20189,966,935Latch circuit and method of operating the latch circuit20189,929,735'Phase correction of multiple phase clock transmission and method for performing the same'20189,871,521'Level shifting circuit, apparatus and method of operating the same'20189,831,860Clock generation circuit20179,800,154'Voltage supply unit and method for operating the same'2017RE046556'Regulators regulating charge pump and memory circuits thereof'20179,755,429'Circuit and method for increasing inductor current'20179,722,818'Decision feedback equalizer summation circuit'20179,712,145'Delay line circuit with variable delay line unit'20179,601,489'Dummy metal gate structures to reduce dishing during chemical-mechanical polishing'2017RE046336'Phase-lock assistant circuitry'20179,584,107'Delay line circuit'20179,570,977'Charge pump initialization device, integrated circuit having charge pump initialization device, and method of operation'20179,559,686'Input/output circuit'20179,531,350'Level shifters for IO interfaces'20169,509,260'High-speed transimpedance amplifier'20169,502,098'Method of operating a voltage regulator to reduce contention current'20169,503,252'Phase interpolator with linear phase change'20169,489,989'Voltage regulators, memory circuits, and operating methods thereof'20169,461,539'Self-calibrated voltage regulator'20169,455,666'Multiple frequency LC voltage controlled oscillator scheme'20169,450,573'Input/output circuit'20169,450,789'Apparatus having programmable taps and method of using the same'2016RE046107'Integrated circuits including a charge pump circuit and operating methods thereof'20169,419,617'Circuit for reducing negative bias temperature instability'20169,407,218'Multi-stage transimpedance amplifier and a method of using the same'20169,391,626'Capacitive load PLL with calibration loop'20169,360,876'Voltage supply circuit having an absorption unit and method for operating the same'20169,293,992'Voltage regulator'20169,275,719'Voltage regulator'20169,276,537'Amplifier inductor sharing for inductive peaking and method therefor'20169,270,276'Level shifting apparatus and method of using the same'20169,236,799'Current generator and method of operating'20169,214,933'Input/output circuit'20159,214,805'Input/output circuit having an inductor'20159,209,681'Charge pump initialization device, integrated circuit having charge pump initialization device, and method of operation'20159,209,182'Dummy metal gate structures to reduce dishing during chemical-mechanical polishing'20159,203,387'Delay line circuit with variable delay line unit'20159,197,195'Drivers having T-coil structures'20159,134,360'Method and apparatus for feedback-based resistance calibration'20159,094,249'Apparatus having programmable taps'20159,071,242'Level shifters, methods for making the level shifters and methods of using integrated circuits'20158,971,395'Decision feedback equalizer having programmable taps'20158,903,030'Clock data recovery circuit with hybrid second order digital filter having distinct phase and frequency correction latencies'20148,896,352'Drivers having T-coil structures'20148,885,787'Clock and data recovery using LC voltage controlled oscillator and delay locked loop'20148,884,665'Multiple-phase clock generator'20148,878,585'Slicer and method of operating the same'20148,872,592'High-speed transimpedance amplifier'20148,873,689'Phase interpolator for clock data recovery circuit with active wave shaping integrators'20148,862,951'Decision feedback equalizer'20148,854,104'Voltage level shifter'20148,847,652'Reconfigurable and auto-reconfigurable resonant clock'20148,816,732'Capactive load PLL with calibration loop'20148,791,720'Circuit for reducing negative bias temperature instability'20148,766,613'Method of operating voltage regulator'20148,709,684'Automatic misalignment balancing scheme for multi-patterning technology'20148,698,566'Phase locked loop calibration'20148,673,312'Method for one-step purification of recombinant Helicobacter pylori neutrophil-activating protein'20148,643,422'Slicer and method of operating the same'20148,629,704'Level shifters, integrated circuits, systems, and methods for operating the level shifters'20148,625,240'Input/output circuit with inductor'20148,614,604'Amplifier inductor sharing for inductive peaking'20138,610,421'Current generator and method of operating'20138,588,358'Clock and data recovery using LC voltage controlled oscillator and delay locked loop'20138,575,966'Method of operating phase-lock assistant circuitry'20138,570,068'Circuit for reducing negative bias temperature instability'20138,493,124'Low minimum power supply voltage level shifter'20138,456,942'Regulators regulating charge pump and memory circuits thereof'20138,436,671'Level shifters having diode-connected devices for input-output interfaces'20138,432,204'Current-controlled oscillator (CCO) based PLL'20138,378,654'Voltage regulator with high accuracy and high power supply rejection ratio'20138,378,756'Drive loop for MEMS oscillator'20138,368,437'Phase locked loop with charge pump'20138,354,862'Phase-lock assistant circuitry'20138,324,960'Charge pump doubler'20128,223,576'Regulators regulating charge pump and memory circuits thereof'20128,217,729'Integrated circuits including an LC tank circuit and operating methods thereof'20128,207,775'VOL up-shifting level shifters'20128,183,913'Integrated circuits including a charge pump circuit and operating methods thereof'20128,179,162'Phase-lock assistant circuitry'20128,132,135'Method and system for creating a boolean model of multi-path and multi-strength signals for verification'20128,068,576'Counters and exemplary applications'20117,961,050'Integrated circuits including an equalizer and operating methods thereof'20117,823,104'Determination of single-fix rectification function'20107,735,035'Method and system for creating a boolean model of multi-path and multi-strength signals for verification'20107,694,251'Method and system for verifying power specifications of a low power design'20107,669,165'Method and system for equivalence checking of a low power design'20107,644,380'Method for analyzing circuits having MOS devices'20107,627,842'Method and system for verification of circuits with encoded signals'20097,620,918'Method and system for logic equivalence checking'20097,620,919'Method and system for logic equivalence checking'20097,373,618'Method and system for selection and replacement of subcircuits in equivalence checking'20087,279,822'Transformer level driving circuit'20077,266,790'Method and system for logic equivalence checking'20077,240,311'Combinational equivalence checking methods and systems with internal don\'t cares'20077,137,084'Similarity-driven synthesis for equivalence checking of complex designs'20067,067,957'Ceramic transformer level driving circuit'20067,057,672'Method and apparatus for high frequency data transmission and testability in a low voltage, differential swing design'20066,848,084'Method and apparatus for verification of memories at multiple abstraction levels'20056,842,884'Combinational equivalence checking methods and systems with internal don\'t cares'20056,742,174'Similarity-driven synthesis for equivalence checking of complex designs'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2020Based in San Jose, CA, US· patent location history
2006–2007Based in Taipei, TW· patent location history
2006Based in Santa Clara, CA, US· patent location history
2008–2012Based in Saratoga, CA, US· patent location history
2011–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (54)· patent assignee history
2011–2017Patents assigned to LIN CHIH-CHANG (40)· patent assignee history
2012–2017Patents assigned to CHERN CHAN-HONG (34)· patent assignee history
2012–2017Patents assigned to HUANG MING-CHIEH (34)· patent assignee history
2014Based in Hsinchu, TW· patent location history
2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (42)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG542011–2016
TAIWAN SEMICONDUCTOR MFG CO LTD422015–2020
LIN CHIH-CHANGself402011–2017
CHERN CHAN-HONG342012–2017
HUANG MING-CHIEH342012–2017
Locations
LocationPatentsSpan
San Jose, California, US1052004–2020
Saratoga, California, US72008–2012
Taipei, TW22006–2007
Hsinchu, TW12014
Santa Clara, California, US12006