Delay circuit and semiconductor memory device

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2013-132938, filed on Jun. 25, 2013; the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a delay circuit and a semiconductor memory device.

In a semiconductor memory device, a sense amplifier is activated after the potential of a bit line reaches a potential enough to define the output of the sense amplifier when reading data. In the activation, a margin for the timing of activating the sense amplifier is set in such a way that variations in the characteristic of a transistor for use in the sense amplifier are absorbed.

FIG. 1 is a block diagram of the schematic configuration of a semiconductor memory device according to a first embodiment;

FIG. 2 is a block diagram of one column extracted from the semiconductor memory device in FIG. 1 ;

FIG. 3 is a circuit diagram of an exemplary configuration of a delay circuit in FIG. 2 ;

FIG. 4 is a plan view of an exemplary layout configuration of the delay circuit in FIG. 3 ;

FIG. 5 is a timing chart of the voltage waveforms of respective components included in the semiconductor memory device in FIG. 1 when reading data;

FIG. 6A is a diagram of the relationship between the threshold voltage and the delay amount before compensating a delay in the delay circuit in FIG. 3 ;

FIG. 6B is a diagram of the relationship between the threshold voltage and the delay amount after compensating a delay in the delay circuit in FIG. 3 ;

FIG. 7 is a diagram of the list of changes in the access time and the activation voltage before and after compensating a delay when changing the characteristics of the transistor of the delay circuit in FIG. 3 and operation conditions;

FIG. 8 is a graph that changes in the activation voltage are plotted before and after compensating a delay when changing the characteristics of the transistor of the delay circuit in FIG. 3 and operation conditions; and

FIG. 9 is a circuit diagram of an exemplary configuration of a delay circuit applied to a semiconductor memory device according to a second embodiment.

In general, according to one embodiment, a load adjusting circuit and a driving force adjusting circuit are provided. The load adjusting circuit adjusts the load of an inverter circuit based on the threshold voltage of a first conductive type transistor provided on the inverter circuit. The driving force adjusting circuit adjusts the driving force of the inverter circuit based on the threshold voltage of the first conductive type transistor.

In the following, a semiconductor memory device according to embodiments will be described in detail with reference to the accompanying drawings. It is noted that the present invention is not limited to these embodiments.

First Embodiment

FIG. 1 is a block diagram of the schematic configuration of a semiconductor memory device according to a first embodiment.

In FIG. 1 , a semiconductor memory device is provided with a memory cell array 11 , a row decoder 13 , a sense amplifier circuit 14 , and a timing control circuit 15 .

Here, on the memory cell array 11 , memory cells 12 are arranged in a matrix configuration in the row direction and the column direction. It is noted that the memory cell 12 can complementarily store data, and can configure an SRAM, for example.

The memory cell array 11 is provided with a word line WL that transmits a signal to select a row of the memory cell 12 . Moreover, the memory cell array 11 is provided with bit lines BLt and BLc that complementarily transmit signals read out of the memory cell 12 .

The memory cells 12 on the same rows are connected to each other through the respective word lines WL. Furthermore, the memory cells 12 on the same columns are connected to each other through the respective bit lines BLt and BLc. It is noted that in reading/writing data to the memory cell 12 , the bit lines BLt and BLc can complementarily operate to each other. For example, in reading/writing data to the memory cell 12 , the bit line BLc can be set at low level when the bit line BLt is set at high level, whereas the bit line BLc can be set at high level when the bit line BLt is set at low level. It is noted that both of the bit lines BLt and BLc are precharged at high level in standby.

Here, the memory cell 12 is provided with a pair of drive transistors D 1 and D 2 , a pair of load transistors L 1 and L 2 , and a pair of transmission transistors F 1 and F 2 . It is noted that P-channel field effect transistors can be used for the load transistors L 1 and L 2 and N-channel field effect transistors can be used for the drive transistors D 1 and D 2 and the transmission transistors F 1 and F 2 .

The drive transistor D 1 and the load transistor L 1 are connected to each other in series, so that a CMOS inverter is configured, and the drive transistor D 2 and the load transistor L 2 are connected to each other in series, so that a CMOS inverter is configured. The outputs and inputs of a pair of the CMOS inverters are in cross coupling to each other, so that a flip-flop is configured. The word line WL is connected to the gates of the transmission transistors F 1 and F 2 .

Here, the connecting point between the drain of the drive transistor D 1 and the drain of the load transistor L 1 can configure a storage node Nt, and the connecting point between the drain of the drive transistor D 2 and the drain of the load transistor L 2 can configure a storage node Nc.

Moreover, the bit line BLt is connected to the storage node Nt through the transmission transistor F 1 . Furthermore, the bit line BLc is connected to the storage node Nc through the transmission transistor F 2 .

The row decoder 13 can select a row of the memory cell 12 specified by a row address. The sense amplifier circuit 14 can detect data stored on the memory cell 12 based on the signals read out of the memory cell 12 to the bit lines BLt and BLc.

FIG. 2 is a block diagram of one column extracted from the semiconductor memory device in FIG. 1 .

In FIG. 2 , the sense amplifier circuit 14 is provided with a sense amplifier 14 a for individual columns to detect signals transmitted through the bit lines BLt and BLc. The timing control circuit 15 is provided with a delay circuit 16 that delays a clock signal CLK to generate a sense amplifier enable signal SAE. The delay circuit 16 is provided with inverter circuits B 1 to Bn connected in 2n stages (n is a positive integer). The row decoder 13 is provided with a buffer B 0 that drives the word line WL based on the clock signal CLK.

FIG. 3 is a circuit diagram of an exemplary configuration of the delay circuit in FIG. 2 . It is noted that in the example in FIG. 3 , the case is illustrated where the delay circuit 16 is configured using the inverter circuits B 1 and B 2 in two stages.

In FIG. 3 , the inverter circuit B 1 is provided with a load adjusting circuit LA and a driving force adjusting circuit DA. The load adjusting circuit LA is provided with a P-type transistor P 2 . The driving force adjusting circuit DA is provided with an N-type transistor N 2 . The load adjusting circuit LA can adjust a load in the pulldown of the inverter circuit B 1 based on the threshold voltage of the P-type transistor P 2 . The driving force adjusting circuit DA can adjust the driving force (the capability of carrying an electric current) of the inverter circuit B 1 based on the threshold voltage of the P-type transistor P 2 .

The gate potential of the P-type transistor P 2 is set so as to adjust the load charge amount of the inverter circuit B 1 , and the P-type transistor P 2 can output an output signal OUT 1 of the inverter circuit B 1 from the drain. The source potential of the P-type transistor P 2 is inputted to the gate of the N-type transistor N 2 . A P-type transistor P 1 is connected in series to the source side of the P-type transistor P 2 , and the source of the P-type transistor P 1 is set at a first potential VDD. An N-type transistor N 1 is connected in series to the drain side of the P-type transistor P 2 , an N-type transistor N 3 is connected in series to the source side of the N-type transistor N 1 , and the sources of the N-type transistors N 2 and N 3 are set at a second potential VSS. It is noted that the first potential VDD can be set higher than the second potential VSS. For example, the first potential VDD can be set at a power supply potential, and the second potential VSS can be set to a ground potential. The gate of the P-type transistor P 2 can be set at the second potential VSS. An input signal IN of the inverter circuit B 1 is inputted to the gates of the P-type transistor P 1 and the N-type transistors N 1 and N 3 .

The inverter B 2 is provided with a P-type transistor P 4 and an N-type transistor N 4 . The P-type transistor P 4 and the N-type transistor N 4 are connected to each other in series. The source of the P-type transistor P 4 is set at the first potential VDD, and the source of the N-type transistor N 4 is set at the second potential VSS. The output signal OUT 1 of the inverter circuit B 1 is inputted to the gates of the P-type transistor P 4 and the N-type transistor N 4 . An output signal OUT 2 of the inverter circuit B 2 is outputted from the drain of the P-type transistor P 4 .

In the case where the input signal IN is at low level, the P-type transistor P 1 is turned on, and the N-type transistors N 1 and N 3 are turned off. Thus, the source potential of the P-type transistor P 2 is set at the first potential VDD. Moreover, since the gate potential of the P-type transistor P 2 is set at the second potential VSS, the P-type transistor P 2 is turned on, and the output signal OUT 1 of the inverter B 1 is turned at high level. The output signal OUT 1 of the inverter B 1 is then inverted at the inverter B 2 , and the output signal OUT 2 of the inverter B 2 is turned at low level.

When the input signal IN rises from low level to high level, the P-type transistor P 1 is turned off, and the N-type transistors N 1 and N 3 are turned on. Thus, the drain potential of the P-type transistor P 2 is pulled down through the N-type transistors N 1 and N 3 , and the output signal OUT 1 of the inverter B 1 is turned at low level. The output signal OUT 1 of the inverter B 1 is then inverted at the inverter B 2 , and the output signal OUT 2 of the inverter B 2 is turned at high level. Here, since the gate potential of the P-type transistor P 2 is set at the second potential VSS, the P-type transistor P 2 is turned on, and a charge amount q is discharged from the source of the P-type transistor P 2 to the drain. The charge amount q can be given by q=C (VDD−Vtp), where the capacitance of a source node of the P-type transistor P 2 is C, the threshold voltage of the P-type transistor P 2 is Vtp, and the second potential VSS is the ground potential. Thus, when the threshold voltage Vtp of the P-type transistor P 2 is low, the charge amount q discharged in the pulldown of the inverter B 1 is increased, and the load of the inverter B 1 is increased. As a result, when the threshold voltages Vtp of the P-type transistors P 1 and P 2 are reduced, the load in the pulldown of the inverter B 1 can be increased, the dependence of the delay time of the inverter B 1 on characteristic fluctuations of the P-type transistors P 1 and P 2 can be reduced, whereas the operations of the P-type transistors P 1 and P 2 become faster.

Moreover, since the gate potential of the N-type transistor N 2 is set to the source potential of the P-type transistor P 2 , when the threshold voltage Vtp of the P-type transistor P 2 is low, the gate potential of the N-type transistor N 2 drops, and the driving force of the N-type transistor N 2 is reduced. As a result, when the threshold voltages Vtp of the P-type transistors P 1 and P 2 are reduced, the driving force in the pulldown of the inverter B 1 can be reduced, and the dependence of the delay time of the inverter B 1 on characteristic fluctuations of the P-type transistors P 1 and P 2 can be reduced, whereas the operations of the P-type transistors P 1 and P 2 become faster.

Furthermore, the P-type transistor P 1 is connected in series to the source side of the P-type transistor P 2 , so that the source and drain of the P-type transistor P 2 can be pulled up through the P-type transistor P 1 when the input signal IN is at low level. Thus, the source and drain of the P-type transistor P 2 can be precharged when the input signal IN is at low level, and the circuit to precharge the source and drain of the P-type transistor P 2 can be simplified.

In addition, the N-type transistor N 1 is connected in series to the drain side of the P-type transistor P 2 , and the drain of the N-type transistor N 2 is connected to the source of the N-type transistor N 1 , so that the timing of turning on the N-type transistor N 2 can be determined based on the input signal IN. Thus, it is unnecessary to separately provide a circuit that determines the timing of turning on the N-type transistor N 2 , and the circuit configuration can be simplified.

Moreover, the N-type transistor N 3 is connected in series to the source side of the N-type transistor N 1 , so that the inverter B 1 can be pulled down through the N-type transistor N 3 even in the case where it is difficult to turn on the N-type transistor N 2 because the threshold voltages Vtp of the P-type transistors P 1 and P 2 drop too much.

It is noted that in the example in FIG. 3 , a method is described in which the delay circuit is configured using the inverters B 1 and B 2 in two stages. However, the delay circuit may be configured using only the inverter B 1 , or the delay circuit may be configured by alternately connecting the inverters B 1 and B 2 to each other in a plurality of stages.

FIG. 4 is a plan view of an exemplary layout configuration of the delay circuit in FIG. 3 .

In FIG. 4 , a P-well PW and active regions A 2 and A 4 are formed on a semiconductor substrate 21 , and active regions A 1 and A 3 are formed on the P-well PW. Gate electrodes G 1 and G 2 are formed on the active region A 1 , gate electrodes G 1 and G 3 are formed on the active region A 2 , and a gate electrode G 4 is formed on the active regions A 3 and A 4 . It is noted that the active regions A 1 to A 4 can configure the source layer, the drain layer, and the channel layer of a transistor.

The active region A 1 and the gate electrode G 1 can configure the P-type transistor P 1 , the active region A 1 and the gate electrode G 2 can configure the P-type transistor P 2 , and the active region A 3 and the gate electrode G 4 can configure the P-type transistor P 4 . The active region A 2 and the gate electrode G 1 can configure the N-type transistors N 1 and N 3 , the active region A 2 and the gate electrode G 3 can configure the N-type transistor N 2 , and the active region A 4 and the gate electrode G 4 can configure the N-type transistor N 4 .

The source layers of the P-type transistors P 1 and P 4 are connected to the first potential VDD through an interconnection H 1 . The source layers of the N-type transistors N 2 to N 4 are connected to the second potential VSS through an interconnection H 2 . The source layer of the P-type transistor P 2 is connected to the gate electrode G 3 through an interconnection H 3 . The drain layer of the P-type transistor P 2 is connected to the drain layer of the N-type transistor N 1 through an interconnection H 4 . The drain layer of the N-type transistor N 2 is connected to the source layer of the N-type transistor N 1 and the drain layer of the N-type transistor N 3 through an interconnection H 5 . The drain layer of the P-type transistor P 4 is connected to the drain layer of the N-type transistor N 4 through an interconnection H 6 .

FIG. 5 is a timing chart of the voltage waveforms of respective components included in the semiconductor memory device in FIG. 1 when reading data.

In FIG. 5 , both of the bit lines BLt and BLc are precharged at high level in standby. Moreover, before the clock signal CLK rises, the potential of the word line WL is set at low level, and the memory cell 12 is not selected. Moreover, before the clock signal CLK rises, the sense amplifier enable signal SAE is maintained at low level, and the sense amplifier circuit 14 a is not activated.

In reading data, when the clock signal CLK rises, a word line WL on a row selected at the row decoder 13 rises to turn on the transmission transistor F 1 . At this time, it is supposed that ‘zero’ is stored on the storage node Nt of the selected cell and ‘one’ is stored on the storage node Nc, the bit line BLt on the selected column is in discharge through the drive transistor D 1 , and the potential of the bit line BLt is gradually reduced according to the driving force of the drive transistor D 1 . Thus, the voltage difference between the bit lines BLt and BLc is increased, and the voltage difference between the bit lines BLt and BLc reaches a lowest voltage Vf that can be detected at the sense amplifier circuit 14 a.

Furthermore, when the clock signal CLK rises, the sense amplifier enable signal SAE rises according to the delay time of the delay circuit 16 , and the sense amplifier circuit 14 a is activated. At this time, when the sense amplifier circuit 14 a is activated before the voltage difference between the bit lines BLt and BLc reaches the lowest voltage Vf, the sense amplifier circuit 14 a makes a false detection. Thus, the delay time of the delay circuit 16 is set in such a way that the sense amplifier circuit 14 a is activated after the voltage difference between the bit lines BLt and BLc reaches the lowest voltage Vf. Here, when the delay time of the delay circuit 16 is prolonged, the read rate is reduced although it can be reliably prevented that the sense amplifier circuit 14 a makes a false detection. Thus, in order that correctness in detection at the sense amplifier circuit 14 a is compatible with the rapidity in reading data, preferably, the delay time of the delay circuit 16 is set in such a way that the sense amplifier circuit 14 a is activated immediately after the voltage difference between the bit lines BLt and BLc reaches the lowest voltage Vf. When the sense amplifier circuit 14 a is activated, data on the selected cell is determined based on the voltage difference between the bit lines BLt and BLc, and the determined result is outputted as read data RD.

Here, since the bit lines BLt and BLc are in discharge through the transmission transistor F 1 and the drive transistor D 1 and through the transmission transistor F 2 and the drive transistor D 2 , respectively, a time period for which the voltage difference between the bit lines BLt and BLc reaches the lowest voltage Vf is determined according to the characteristic of the N-type transistor of the memory cell 12 , and the time period does not depend on characteristic fluctuations of the P-type transistor.

On the other hand, in the case where the configuration similar to the configuration of the inverter B 2 is used for the configuration of the inverter B 1 (in the case where a delay is not compensated), the delay time of the delay circuit 16 is determined according to the characteristics of the N-type transistor and the P-type transistor, and the delay time depends on characteristic fluctuations of both of the N-type transistor and the P-type transistor. Namely, delay time td 2 under an SS condition is longer than delay time td 1 under an SF condition. It is noted that the SS condition is the case where characteristics vary in such a way that the operations of the P-type transistor and the N-type transistor become slow, and the SF condition is the case where characteristics vary in such a way that the operation of the P-type transistor becomes faster and the operation of the N-type transistor becomes slow. As a result, the access time for which the clock signal CLK rises and then the lead data RD is outputted is different between the SF condition and the SS condition. Namely, access time tac 2 under the SS condition is longer than access time tac 1 under the SF condition. At this time, under the SS condition, since the sense amplifier circuit 14 a is activated some time behind when the voltage difference between the bit lines BLt and BLc reaches the lowest voltage Vf, an extra margin is added to the timing of activating the sense amplifier circuit 14 a , and the read rate of the sense amplifier circuit 14 a is reduced.

On the other hand, in the case where the inverter B 1 is used for the delay circuit 16 (in the case where a delay is compensated), the dependence of the delay time of the inverter B 1 on characteristic fluctuations of the P-type transistor can be reduced. Thus, the delay time of the delay circuit 16 is determined according to the characteristic of the N-type transistor, and it can be prevented that the delay time of the delay circuit 16 depends on characteristic fluctuations of the P-type transistor. Namely, the delay time under the SS condition can be made equal to the delay time td 1 under the SF condition, and the access time under the SS condition can be made equal to the access time tac 1 under the SF condition. At this time, the sense amplifier circuit 14 a can be activated immediately after the voltage difference between the bit lines BLt and BLc reaches the lowest voltage Vf also under the SS condition as similar to the SF condition, and an extra margin added to the timing of activating the sense amplifier circuit 14 a can be reduced, so that the read rate of the sense amplifier circuit 14 a can be improved.

It is noted that the inverter B 1 is used for the delay circuit 16 , so that it is made possible that the delay time of the delay circuit 16 is determined according to the characteristic of the N-type transistor of the delay circuit 16 as similar to the fact that the time period to reach the lowest voltage Vf is determined according to the characteristic of the N-type transistor of the memory cell 12 . At this time, preferably, the characteristic of the N-type transistor is matched between the memory cell 12 and the delay circuit 16 , and preferably, the threshold voltage of the N-type transistor of the delay circuit 16 and the threshold voltage of the N-type transistor of the memory cell 12 are equal to each other.

FIG. 6A is a diagram of the relationship between the threshold voltage and the delay amount before compensating a delay in the delay circuit in FIG. 3 , and FIG. 6B is a diagram of the relationship between the threshold voltage and the delay amount after compensating a delay in the delay circuit in FIG. 3 .

In FIG. 6A , in the case where a delay is not compensated at the delay circuit in FIG. 3 , the delay time of the delay circuit fluctuates depending on characteristic fluctuations of the N-type transistor and the P-type transistor. It is noted that an FF condition is the case where characteristics vary in such a way that the operations of the P-type transistor and the N-type transistor become faster and an FS condition is the case where characteristics vary in such a way that the operation of the P-type transistor becomes slow and the operation of the N-type transistor becomes faster, and a TT condition is the case where the characteristics of the P-type transistor and the N-type transistor are typical characteristics. Moreover, ΔVtp expresses a change in the threshold of the P-type transistor, and ΔVtn expresses a change in the threshold of the N-type transistor.

On the other hand, in FIG. 6B , in the case where a delay is compensated at the delay circuit in FIG. 3 , it can be prevented that the delay time of the delay circuit does not fluctuate even in the case where the characteristic of the P-type transistor fluctuates. Thus, it can be prevented that the rate of the delay time of the delay circuit is not limited under the SS condition, and the read rate of the sense amplifier circuit 14 a can be improved.

FIG. 7 is a diagram of the list of changes in the access time and the activation voltage before and after compensating a delay when changing the characteristics of the transistor of the delay circuit in FIG. 3 and operation conditions. It is noted that SS — −40, SF — −40, FS — −40, and FF — −40 express the cases where samples are operated at a temperature of −40□C under the SS condition, the SF condition, the FS condition, and the FF condition, respectively, and SS 125, SF 125, FS 125, and FF 125 express the cases where samples are operated at a temperature of 125□C under the SS condition, the SF condition, the FS condition, and the FF condition, respectively.

In FIG. 7 , in the case where a delay is not compensated, the lowest voltage Vf is determined at SF — −40, whereas the access time tac is determined at SS — −40. It is supposed that the lowest voltage Vf is one at SF — −40, the lowest voltage Vf is 1.13 at SS — −40, and an extra margin is added at SS — −40.

On the other hand, in the case where a delay is compensated, the lowest voltage Vf and the access time tac are determined at SS — −40, and the access time tac can be reduced. Thus, the rate can be accelerated 0.94 times the case where a delay is not compensated.

FIG. 8 is a graph that changes in the activation voltage are plotted before and after compensating a delay when changing the characteristics of the transistor of the delay circuit in FIG. 3 and operation conditions.

In FIG. 8 , in the case where a delay is compensated, variations in the lowest voltage Vf with respect to variations in the operation condition can be relaxed as compared with the case where a delay is not compensated. Thus, voltage swings in the bit lines BLt and BLc in reading data can be reduced, and power consumption can be reduced. For example, at SF — −40, the voltage swings in the bit lines BLt and BLc can be reduced by 10 to 20%, and power consumption can be reduced accordingly.

Second Embodiment

FIG. 9 is a circuit diagram of an exemplary configuration of a delay circuit applied to a semiconductor memory device according to a second embodiment. It is noted that in the example in FIG. 9 , the case is illustrated where a delay circuit is configured using inverters B 11 and B 12 in two stages. Moreover, in the example in FIG. 3 , the configuration is illustrated in which the dependence of the delay time of the inverter B 1 on characteristic fluctuations of the P-type transistors P 1 and P 2 is reduced. However, in the example in FIG. 9 , the configuration is illustrated in which the dependence of the delay time of the inverter B 11 on characteristic fluctuations of N-type transistors N 11 and N 12 is reduced.

In FIG. 9 , the inverter B 12 is provided with a load adjusting circuit LB and a driving force adjusting circuit DB. The load adjusting circuit LB is provided with the N-type transistor N 12 . The driving force adjusting circuit DB is provided with a P-type transistor P 12 . The load adjusting circuit LB can adjust a load in the pullup of the inverter circuit B 12 based on the threshold voltage of the N-type transistor N 12 . The driving force adjusting circuit DB can adjust the driving force of the inverter circuit B 12 based on the threshold voltage of the N-type transistor N 12 .

The gate potential of the N-type transistor N 12 is set in such a way that the load charge amount of the inverter circuit B 12 is adjusted, and the N-type transistor N 12 can output an output signal OUT of the inverter circuit B 12 from the drain. The source potential of the N-type transistor N 12 is inputted to the gate of the P-type transistor P 12 . The N-type transistor N 11 is connected in series to the source side of the N-type transistor N 12 , and the source of the N-type transistor N 11 is set at the second potential VSS. A P-type transistor P 11 is connected in series to the drain side of the N-type transistor N 12 , a P-type transistor P 13 is connected in series to the source side of the P-type transistor P 11 , and the sources of the P-type transistors P 12 and P 13 are set at the first potential VDD. The gate of the N-type transistor N 12 can be set at the first potential VDD. An input signal IN 2 of the inverter circuit B 12 is inputted to the gates of the N-type transistor N 11 and the P-type transistors P 11 and P 13 .

The inverter B 11 is provided with a P-type transistor P 14 and an N-type transistor N 14 . The P-type transistor P 14 and the N-type transistor N 14 are connected to each other in series. The source of the P-type transistor P 14 is set at the first potential VDD, and the source of the N-type transistor N 14 is set at the second potential VSS. An input signal IN 1 of the inverter circuit B 11 is inputted to the gates of the P-type transistor P 14 and the N-type transistor N 14 . The input signal IN 2 of the inverter circuit B 12 is outputted from the drain of the P-type transistor P 14 .

In the case where the input signal IN 1 is at low level, the input signal IN 1 is inverted at the inverter B 11 , and the input signal IN 2 of the inverter B 12 is turned at high level. At this time, the N-type transistor N 11 is turned on, and the P-type transistors P 11 and P 13 are turned off. Thus, the source potential of the N-type transistor N 12 is set at the second potential VSS. Moreover, since the gate potential of the N-type transistor N 12 is set at the first potential VDD, the N-type transistor N 12 is turned on, and the output signal OUT of the inverter B 12 is turned at low level.

When the input signal IN 1 rises from low level to high level, the input signal IN 1 is inverted at the inverter B 11 , and the input signal IN 2 of the inverter B 12 is turned at low level. At this time, the N-type transistor N 11 is turned off, and the P-type transistors P 11 and P 13 are turned on. Thus, the drain potential of the N-type transistor N 12 is pulled up through the P-type transistors P 11 and P 13 , and the output signal OUT of the inverter B 12 is turned at high level. Here, since the gate potential of the N-type transistor N 12 is set at the first potential VDD, the N-type transistor N 12 is turned on, and the source is charged by the charge amount q from the drain of the N-type transistor N 12 . The charge amount q can be given by q=C (VDD−Vtn), where the capacitance of a source node of the N-type transistor N 12 is C, the threshold voltage of the N-type transistor N 12 is Vtn, and the second potential VSS is the ground potential. Thus, when the threshold voltage Vtn of the N-type transistor N 12 is low, the charge amount q charged in the pullup of the inverter B 12 is increased, and the load of the inverter B 12 is increased. As a result, when the threshold voltages Vtn of the N-type transistors N 11 and N 12 are reduced, the load in the pullup of the inverter B 12 can be increased, and the dependence of the delay time of the inverter B 12 on characteristic fluctuations of the N-type transistors N 11 and N 12 can be reduced, whereas the operations of the N-type transistors N 11 and N 12 become faster.

Moreover, since the gate potential of the P-type transistor P 12 is set to the source potential of the N-type transistor N 12 , the gate potential of the P-type transistor P 12 is increased, and the driving force of the P-type transistor P 12 is reduced when the threshold voltage Vtn of the N-type transistor N 12 is low. As a result, when the threshold voltages Vtn of the N-type transistors N 11 and N 12 are reduced, the driving force in the pullup of the inverter B 12 can be reduced, and the dependence of the delay time of the inverter B 12 on characteristic fluctuations of the N-type transistors N 11 and N 12 can be reduced, whereas the operations of the N-type transistors N 11 and N 12 become faster.

It is noted that in the example in FIG. 9 , a method is described in which the delay circuit is configured using the inverters B 11 and B 12 in two stages. However, the delay circuit may be configured using only the inverter B 12 , or the delay circuit may be configured by alternately connecting the inverters B 11 and B 12 to each other in a plurality of stages.

Furthermore, the configuration in FIG. 3 is suited to an SRAM in which the bit lines BLt and BLc are in discharge from the state in which the bit lines BLt and BLc are in precharge according to data in the memory cell 12 . On the other hand, the configuration of FIG. 9 is suited to an SRAM in which the bit lines BLt and BLc are in charge from the state in which the bit lines BLt and BLc are in discharge according to data in the memory cell 12 .

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.