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Inventor

Osamu Hirabayashi

Inventor
Tokyo, JP

Overview

45→
Patents
2000–2015
Patent span
Physics
Primary field (CPC G)

Patents· 45 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores64%
H01RElectrically-conductive connections9%
H10BElectronic memory devices7%
G06FElectric digital data processing5%
H03KPulse technique5%
B60YIndexing scheme relating to aspects cross-cutting vehicle technology2%
G01RMeasuring electric variables2%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%
H03MCoding2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
9,183,905'Delay circuit and semiconductor memory device'20158,784,144'Terminal fitting having a retracted portion extending from one side plate to another side plate'20148,747,156'Terminal fitting'20148,740,645'Terminal fitting'20148,708,759'Terminal fitting and connector'20148,223,579'Semiconductor storage device'20128,102,727'Semiconductor memory device'20128,023,351'Semiconductor memory device'20118,018,756'Semiconductor memory device'20117,986,547'Semiconductor memory device'20117,885,125'Semiconductor memory device having integrated driving word line intermediate voltages by pull-up circuits'20117,823,046'Semiconductor device'20107,729,180'Semiconductor memory device'20107,695,290'Board connector'20107,609,581'Semiconductor memory device'20097,593,276'Semiconductor memory device'20097,535,753'Semiconductor memory device'20097,532,539'Semiconductor device whose operation frequency and power supply voltage are dynamically controlled according to load'20097,477,561'Semiconductor memory device'20097,430,134'Memory cell structure of SRAM'20087,398,439'Semiconductor device with memory and method for memory test'20087,382,674'Static random access memory (SRAM) with clamped source potential in standby mode'20087,362,646'Semiconductor memory device'20087,277,322'Semiconductor memory device having ECC circuit'20077,266,735'Semiconductor device having ECC circuit'20077,259,977'Semiconductor device having hierarchized bit lines'20077,254,085'Static random access memory device and method of reducing standby current'20077,249,296'Semiconductor integrated circuit'20077,215,178'MOS type semiconductor integrated circuit device'20077,187,616'MOS semiconductor integrated circuit device'20077,126,852'Semiconductor memory device having an error correcting code circuit'20067,099,182'Static random access memory and pseudo-static noise margin measuring method'20066,999,338'Semiconductor storage device'20066,982,900'Semiconductor integrated circuit device'20066,978,402'Semiconductor memory'20056,931,565'Semiconductor memory'20056,865,102'Static semiconductor storage device'20056,724,230'Semiconductor integrated circuit'20046,597,626'Synchronous semiconductor memory device'20036,469,557'Semiconductor integrated circuit and delayed clock signal generation method'20026,429,454'Semiconductor device with test circuit'20026,154,394'Data input-output circuit and semiconductor data storage device provided therewith'20006,154,393'Semiconductor memory device of double-data rate mode'20006,118,729'Synchronous semiconductor memory device'20006,011,751'Sychronous semiconductor memory device with burst address counter operating under linear/interleave mode of single data rate/double data rate scheme'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2015Patents assigned to TOSHIBA KK (39)· patent assignee history
2000–2003Based in Hiratsuka, JP· patent location history
2000–2005Based in Kanagawa, JP· patent location history
2000Based in Yokohama, JP· patent location history
2004–2015Based in Tokyo, JP· patent location history
2010–2014Patents assigned to SUMITOMO WIRING SYSTEMS (5)· patent assignee history
2010–2014Based in Yokkaichi, JP· patent location history
2012–2014Patents assigned to HIRABAYASHI OSAMU (6)· patent assignee history
2014Patents assigned to HIRASAWA DAISUKE (2)· patent assignee history
2014Patents assigned to MIZUTANI YOSHIHIRO (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TOSHIBA KK392000–2015
HIRABAYASHI OSAMUself62012–2014
SUMITOMO WIRING SYSTEMS52010–2014
HIRASAWA DAISUKE22014
MIZUTANI YOSHIHIRO22014
Locations
LocationPatentsSpan
Tokyo, JP312004–2015
Yokkaichi, JP52010–2014
Hiratsuka, JP42000–2003
Kanagawa, JP22000–2005
Yokohama, JP22000