Substrate with built-in electronic component

This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. JP2013-197663, filed on Sep. 25, 2013, and Japanese Application No. 2013-056590, filed on Mar. 19, 2013, the entire content of which are hereby incorporated herein by reference in their entirety.

The present disclosure relates to a substrate with built-in electronic component, in which an electronic component is stored in a cavity of a core layer, and more particularly, to a substrate with built-in electronic component, in which a plurality of electronic components are stored in one cavity.

A substrate with built-in electronic component, in which electronic components are stored in a cavity of a core layer, includes a core layer including a core material and a cavity formed by penetrating the core material, electronic components stored in the cavity, an insulating material that fills a gap between the cavity and each electronic component, and an insulating layer formed on the core layer and including a ground wiring, a signal wiring, and the like. The substrate with built-in electronic component has a structure in which the electronic components stored in the cavity are connected to those wirings.

In a major substrate with built-in electronic component in related art, one electronic component is stored in one cavity. In recent years, an attempt to store a plurality of electronic components in one cavity has been made for the purpose of reducing the number of electronic components to be mounted on a surface of the substrate with built-in electronic component.

For example, Japanese Patent Application Laid-open No. 2009-081183 discloses that a capacitor unit in which external electrodes of a plurality of capacitors are connected to be integrated is stored in a cavity of a core substrate. In this technique, the capacitor unit should be preliminarily manufactured before the external electrodes are stored, which is burdensome. In addition, when the arrangement of the capacitor unit in the cavity is changed, the arrangement of all the capacitors that constitute the capacitor unit is changed accordingly. Consequently, the degree of freedom in arrangement (degree of freedom in position or orientation) is lower compared with the case where the capacitors are individually stored. In contrast, Japanese Patent Application Laid-open No. 2006-129448 discloses that a plurality of active components, passive components, or active and passive components are stored in a concave portion of a support. In this technique, the positions or orientations of the stored components are not taken into consideration, and thus there may be a possibility that mutual interference such as crosstalk is caused between the adjacent components.

In view of the circumstances described above, it is desirable to provide a substrate with built-in electronic component, which is capable of obtaining a high degree of freedom in arrangement of electronic components in a cavity and of suppressing mutual interference between the electronic components stored in the cavity, also when a plurality of electronic components are stored in one cavity.

According to an embodiment of the present disclosure, there is provided a substrate with built-in electronic component, including a core layer, an insulating layer, and a plurality of electronic components.

The core layer includes a core material and a cavity formed in the core material and containing an insulating material.

The insulating layer includes a ground wiring and a signal wiring and is formed on the core layer.

The plurality of electronic components each include a first terminal and a second terminal and are stored in the cavity, the plurality of electronic components each having one end portion and the other end portion, the first terminal being formed at the one end portion and connected to the ground wiring, the second terminal being formed at the other end portion and connected to the signal wiring. Further, the plurality of electronic components have at least one of arrangements in which the first terminals face each other and in which the second terminals face each other.

Further, according to another embodiment of the present disclosure, there is provided a substrate with built-in electronic component, the substrate including a core layer including a cavity, electronic components stored in the cavity, an insulating material that fills a gap between the cavity and each of the electronic components, an insulating layer provided on a surface of the core layer in at least a thickness direction, and a wiring provided in the insulating layer, the substrate having a structure in which the electronic components stored in the cavity are connected to the wiring. The electronic components each have end portions on opposite sides and include a first terminal and a second terminal, the first terminal being formed at one of the end portions and used as a terminal on a ground potential side, the second terminal being formed at the other end portion and used as a terminal on a signal potential side. Two or more electronic components are stored in the one cavity, and the two or more electronic components stored in the one cavity have at least one of arrangements in which the first terminals on the ground potential side face each other in a non-contact manner and in which the second terminals on the signal potential side face each other in a non-contact manner.

According to the present disclosure, it is possible to provide a substrate with built-in electronic component, which is capable of obtaining a high degree of freedom in arrangement of electronic components in a cavity and of suppressing mutual interference between the electronic components stored in the cavity, also when a plurality of electronic components are stored in one cavity.

These and other objects, features and advantages of the present disclosure will become more apparent in light of the following detailed description of best mode embodiments thereof, as illustrated in the accompanying drawings.

FIG. 1 is a horizontal cross-sectional view showing an arrangement of electronic components in a substrate with built-in electronic component according to a first embodiment of the present disclosure;

FIG. 2 is a vertical cross-sectional view showing a structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 1 ;

FIG. 3 is a vertical cross-sectional view showing another structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 1 ;

FIG. 4 is a horizontal cross-sectional view showing an arrangement of electronic components in a substrate with built-in electronic component according to a second embodiment of the present disclosure;

FIG. 5 is a vertical cross-sectional view showing a structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 4 ;

FIG. 6 is a vertical cross-sectional view showing another structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 4 ;

FIG. 7 is a horizontal cross-sectional view showing an arrangement of electronic components in a substrate with built-in electronic component according to a third embodiment of the present disclosure;

FIG. 8 is a vertical cross-sectional view showing a structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 7 ;

FIG. 9 is a horizontal cross-sectional view showing an arrangement of electronic components in a substrate with built-in electronic component according to a fourth embodiment of the present disclosure;

FIG. 10 is a vertical cross-sectional view showing a structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 9 ;

FIG. 11 is a horizontal cross-sectional view showing an arrangement of electronic components in a substrate with built-in electronic component according to a fifth embodiment of the present disclosure;

FIG. 12 is a vertical cross-sectional view showing a structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 11 ;

FIG. 13 is a vertical cross-sectional view showing another structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 11 ;

FIG. 14 is a horizontal cross-sectional view showing an arrangement of electronic components in a substrate with built-in electronic component according to a sixth embodiment of the present disclosure; and

FIG. 15 is a vertical cross-sectional view showing a structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 14 .

According to an embodiment of the present disclosure, there is provided a substrate with built-in electronic component, the substrate including a core layer, an insulating layer, and a plurality of electronic components.

The core layer includes a core material and a cavity formed in the core material and containing an insulating material.

The insulating layer includes a ground wiring and a signal wiring and is formed on the core layer.

The plurality of electronic components each include a first terminal and a second terminal and are stored in the cavity, the plurality of electronic components each having one end portion and the other end portion, the first terminal being formed at the one end portion and connected to the ground wiring, the second terminal being formed at the other end portion and connected to the signal wiring. Further, the plurality of electronic components have at least one of arrangements in which the first terminals face each other and in which the second terminals face each other.

With the substrate with built-in electronic component, the plurality of electronic components are arranged in the cavity, and thus the degree of freedom in arrangement of the plurality of electronic components can be increased. Further, the plurality of electronic components are arranged such that the same type of terminals face each other, and thus mutual interference, such as crosstalk, between the electronic components can be suppressed compared with the arrangement in which the first terminal on the ground potential side and the second terminal on the signal potential side face each other.

The plurality of electronic components may be arranged such that the first terminals face each other via the insulating material and each of the second terminals and the core material face each other via the insulating material.

With this structure, the first terminals on the ground potential side face each other, and thus a distance between the first terminals of the plurality of electronic components can be reduced. Consequently, the length of the cavity in a direction in which those electronic components face each other can be reduced, and a reduction in area of the horizontal cross-section of the cavity can be achieved, resulting in a contribution to the downsizing of the substrate with built-in electronic component. Further, each of the second terminals and the core material face each other via the insulating material, and thus an electromagnetic failure caused between them can be prevented.

In this case, the core material may be made of a conductor and may be kept at a ground potential, and each of the second terminals and the core material may face each other at a distance larger than that between the first terminals. With this structure, if the positions of the electronic components are somewhat displaced in a process of manufacturing the substrate with built-in electronic component, the second terminals on the signal potential side and the core material that is kept at a ground potential can be prevented from coming into contact with each other. Consequently, an electromagnetic failure between them can be prevented, and defects or the like of the electronic components can be prevented. Further, the distance between the first terminals can be reduced relatively, and thus the downsizing of the substrate with built-in electronic component can be achieved while preventing an electromagnetic failure.

Alternatively, the plurality of electronic components may be arranged such that the second terminals face each other via the insulating material and each of the first terminals and the core material face each other via the insulating material. With this structure, the second terminals on the signal potential side face each other, and thus mutual interference, such as crosstalk, between the electronic components can be suppressed compared with the arrangement in which the first terminal on the ground potential side and the second terminal on the signal potential side face each other.

In this case, the core material may be made of a conductor and may be kept at a ground potential, and the second terminals face each other at a distance larger than that between each of the first terminals and the core material.

With this structure, if the positions of the electronic components are somewhat displaced in a process of manufacturing the substrate with built-in electronic component, the second terminals on the signal potential side can be prevented from being coming into contact with each other. Consequently, an electromagnetic failure between them can be prevented, and defects or the like of the electronic components can be prevented. Further, the distance between each of the first terminals on the ground potential side and the core material that is kept at a ground potential can be reduced relatively, and thus the downsizing of the substrate with built-in electronic component can be achieved while preventing an electromagnetic failure.

Further, the first terminal and the second terminal may each have an end surface and a side surface connected to the end surface, the plurality of electronic components may be arranged such that the side surfaces of the first terminals face each other via the insulating material and the side surfaces of the second terminals face each other via the insulating material, and the second terminals whose side surfaces face each other may be connected to each other.

With this structure, the plurality of electronic components can be arranged to be adjacent to one another when arranged to be parallel. This allows a reduction in area of the horizontal cross-section of the cavity to be achieved, resulting in a contribution to the downsizing of the substrate with built-in electronic component.

In this case, the core material may be made of a conductor and may be kept at a ground potential, the plurality of electronic components may be arranged such that the end surfaces of the first terminals each face the core material and the end surfaces of the second terminals each face the core material, and each of the second terminals and the core material may face each other at a distance larger than that between each of the first terminals and the core material. With this structure, if the positions of the electronic components are somewhat displaced in a process of manufacturing the substrate with built-in electronic component, the second terminals on the signal potential side and the core material that is kept at a ground potential can be prevented from coming into contact with each other. Consequently, an electromagnetic failure between them can be prevented, and defects or the like of the electronic components can be prevented. Further, the distance between the first terminals can be reduced relatively, and thus the downsizing of the substrate with built-in electronic component can be achieved while preventing an electromagnetic failure.

Alternatively, the plurality of electronic components may include a plurality of sets of electronic components in which the second terminals are connected to each other, and the plurality of sets of electronic components face each other via the end surfaces of the first terminals of the plurality of electronic components included in each of the sets of electronic components. With this structure, the sets of the plurality of electronic components connected parallel can face each other via the first terminals on the ground potential side and can be arranged close to each other. Consequently, also when a large number of electronic components are arranged in one cavity, a reduction in area of the horizontal cross-section of the cavity can be achieved, resulting in a contribution to the downsizing of the substrate with built-in electronic component.

Further, two of the plurality of electronic components may be arranged to face each other in one axis direction, and each of the two electronic components may be arranged such that the first terminal and the second terminal are arranged on a straight line along the axis direction. With this structure, the length of the cavity in one axis direction can be reduced. Consequently, a reduction in area of the horizontal cross-section of the cavity can be achieved, resulting in a contribution to the downsizing of the substrate with built-in electronic component.

Two of the plurality of electronic components may be arranged to face each other in one axis direction, and each of the two electronic components may be arranged such that the first terminal and the second terminal are arranged on a straight line along a direction orthogonal to the axis direction. With this structure, the plurality of electronic components can be arranged such that the side surfaces of the first terminals face each other in the axis direction and the side surfaces of the second terminals face each other in the axis direction. Consequently, the length of the cavity in a direction orthogonal to the axis direction can be reduced, and a reduction in area of the horizontal cross-section of the cavity can be achieved, resulting in a contribution to the downsizing of the substrate with built-in electronic component.

One of the plurality of electronic components may be arranged such that the first terminal and the second terminal are arranged on a straight line along one axis direction, and another one of the plurality of electronic components may be arranged such that the first terminal and the second terminal are arranged on a straight line along a direction orthogonal to the axis direction. With this structure, the shape of the cavity can be set according to the outline that surrounds the plurality of electronic components. This allows a further reduction in area of the horizontal cross-section of the cavity to be achieved, resulting in a further contribution to the downsizing of the substrate with built-in electronic component.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

First Embodiment

FIGS. 1 to 3

FIG. 1 is a horizontal cross-sectional view showing an arrangement of electronic components in a substrate with built-in electronic component according to a first embodiment of the present disclosure. FIG. 2 is a vertical cross-sectional view showing a structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 1 . FIG. 3 is a vertical cross-sectional view showing another structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 1 . It should be noted that FIG. 1 corresponds to a cross-sectional view taken along the line A-A of FIGS. 2 and 3 . Further, an X-axis direction, a Y-axis direction, and a Z-axis direction in FIGS. 1 to 16 indicate three axis directions orthogonal to one another. Each of the X-axis direction and the Y-axis direction indicates a horizontal direction, and the Z-axis direction indicates a thickness direction (vertical direction).

As shown in FIGS. 1 to 3 , the substrate with built-in electronic component in this embodiment includes a core layer 11 including a core material 11 b and a cavity 11 a , insulating layers 13 and 17 formed on the core layer 11 , and two electronic components P 1 and P 2 stored in the cavity 11 a.

The insulating layer 13 includes signal wirings 14 and a ground wiring 15 and is provided on the upper surface of the core layer 11 . The signal wirings 14 and the ground wiring 15 are each formed in one wiring layer arranged in the insulating layer 13 . Conductor pads 16 connected to the signal wirings 14 are provided on the upper surface of the insulating layer 13 .

As in the insulating layer 13 , the insulating layer 17 includes signal wirings 18 and a ground wiring 19 and is provided on the lower surface of the core layer 11 . The signal wirings 18 and the ground wiring 19 are each formed in one wiring layer arranged in the insulating layer 17 . Conductor pads 20 connected to the signal wirings 18 are provided on the lower surface of the insulating layer 17 .

The insulating layers 13 and 17 each have the thickness of 30 to 90 μm, for example. Further, each of the signal wirings 14 and 18 , ground wirings 15 and 19 , and conductor pads 16 and 20 is made of metal such as copper and an copper alloy and has the thickness of 5 to 25 μm, for example.

The core material 11 b is made of a conductor such as copper and a copper alloy and has the thickness of 100 to 400 μm, for example. The core material 11 b is connected to the ground wiring 19 and is kept at a ground potential. The cavity 11 a has a horizontal cross section with an approximately rectangular shape and is formed by penetrating the core material 11 b in the Z-axis direction (thickness direction). The cavity 11 a contains an insulating material 12 that fills a gap between the inner side surface of the core material 11 b and each of the electronic components P 1 and P 2 . The insulating material 12 and the insulating layers 13 and 17 are each made of a synthetic resin of an epoxy resin, polyimide, a bismaleimide triazine resin, a resin containing any one of them and a reinforcing filler made of a silicon dioxide, or the like (not only a thermosetting resin but also a thermoplastic resin can be used).

Each of the electronic components P 1 and P 2 has an approximately rectangular parallelepiped shape and is configured such that one end portion and the other end portion of the electronic component are arranged on a straight line extending along the X-axis direction in this embodiment. Each of the electronic components P 1 and P 2 includes a first terminal t 1 and a second terminal t 2 . The first terminal t 1 is formed at the one end portion and connected to the ground wiring 15 . The second terminal t 2 is formed at the other end portion and connected to the signal wiring 14 . That is, the first terminal t 1 is used as a terminal on a ground potential side and the second terminal t 2 is used as a terminal on a signal potential side. Each of the electronic components P 1 and P 2 is an electronic component such as a capacitor, an inductor, a resistor, and a filter and may be a combination of the same kind of electronic components or a combination of different kinds of electronic components.

As shown in FIG. 1 , the first terminal t 1 has an end surface t 11 and a side surface t 12 . The end surface t 11 can be assumed to be an end surface at one end portion of each of the electronic components P 1 and P 2 , and the side surface t 12 can be assumed to be a surface that is connected to and substantially orthogonal to the end surface t 11 . Similarly, the second terminal t 2 also has an end surface t 21 and a side surface t 22 . The end surface t 21 can be assumed to be an end surface at the other end portion of each of the electronic components P 1 and P 2 , and the side surface t 22 can be assumed to be a surface that is connected to and substantially orthogonal to the end surface t 21 .

As shown in FIG. 1 , the two electronic components P 1 and P 2 are arranged such that their first terminals t 1 face each other in the X-axis direction (one axis direction) and the first terminal t 1 and the second terminal t 2 of each electronic component are arranged on a straight line along the X-axis direction. That is, the end surfaces t 11 of the first terminals t 1 face each other at a distance CL 1 via the insulating material 12 . Further, the end surface t 21 of each of the second terminals t 2 faces the core material 11 b (to the inner wall of the cavity 11 a ) at a distance CL 2 larger than the distance CL 1 via the insulating material 12 . Furthermore, each of the side surfaces t 12 and t 22 of the first terminals t 1 and the second terminals t 2 faces the core material 11 b (to the inner wall of the cavity 11 a ) at a distance (not denoted by a reference symbol) larger than the distance CL 1 via the insulating material 12 . It should be noted that in the following description, the phrase of “face the core material 11 b ” refers to “face the inner side surface of the core material 11 b”.

In the structure example shown in FIG. 2 , the first terminals t 1 of the electronic components P 1 and P 2 are connected to the common ground wiring 15 via conductor vias 15 a . Further, the second terminal t 2 of the electronic component P 1 is connected to the signal wiring 14 (on the left-hand side of FIG. 2 ) via a conductor via 14 a , and the second terminal t 2 of the electronic component P 2 is connected to the different signal wiring 14 (on the right-hand side of FIG. 2 ) via a conductor via 14 a . Each of the signal wirings 14 is connected to a corresponding conductor pad 16 via a conductor via 16 a.

In other words, in the structure example shown in FIG. 2 , the first terminals t 1 of the two electronic components P 1 and P 2 are each kept at a ground potential (for example, 0 V). In contrast, the second terminals t 2 of the two electronic components P 1 and P 2 are each configured to receive an input of a signal individually from a corresponding conductor pad 16 . Specifically, signals with different potentials (for example, +3 V, +5 V, or −3 V) or signals with the same potential (for example, +3 V, +5 V, or −3 V) can be input to the second terminals t 2 of the electronic components P 1 and P 2 . Herein, the signals may be analog or digital.

As another structure example, as shown in FIG. 3 , the first terminals t 1 of the electronic components P 1 and P 2 are connected to the common ground wiring 15 via the conductor vias 15 a . Further, the second terminal t 2 of the electronic component P 1 is connected to the signal wiring 14 (on the left-hand side of FIG. 3 ) via the conductor via 14 a , and the second terminal t 2 of the electronic component P 2 is connected to the different signal wiring 14 (on the right-hand side of FIG. 3 ) via the conductor via 14 a . Additionally, the signal wirings 14 are connected to a common conductor pad 16 via the conductor vias 16 a.

In other words, in the structure example shown in FIG. 3 , the first terminals t 1 of the two electronic components P 1 and P 2 on the ground potential side are each at a ground potential (for example, 0 V), and the second terminals t 2 of the two electronic components P 1 and P 2 are each configured to receive an input of a signal from the common conductor pad 16 . Specifically, signals with the same potential (for example, +3 V, +5 V, or −3 V) can be input to the second terminals t 2 of the electronic components P 1 and P 2 . Herein, the signals may be analog or digital.

According to the substrate with built-in electronic component in this embodiment, the following effects can be obtained.

(a1) One cavity 11 a stores the two electronic components P 1 and P 2 , and thus the electronic components P 1 and P 2 in the cavity 11 a can have a high degree of freedom in arrangement (degree of freedom in position or orientation). Additionally, the two electronic components P 1 and P 2 stored in the cavity 11 a are arranged such that the first terminals t 1 on the ground potential side face each other in a non-contact manner. Consequently, compared with the case where the first terminal t 1 on the ground potential side and the second terminal t 2 on the signal potential side are arranged so as to face each other, mutual interference, such as crosstalk, between the electronic components P 1 and P 2 can be suppressed.

(a2) The first terminals t 1 of the two electronic components P 1 and P 2 on the ground potential side face each other, and thus the distance CL 1 between the first terminals t 1 can be reduced as much as possible and the length of the cavity 11 a in the X-axis direction can be reduced. This allows a reduction in area of the horizontal cross-section of the cavity 11 a to be achieved, resulting in a contribution to the downsizing of the substrate with built-in electronic component.

(a3) The second terminals t 2 of the two electronic components P 1 and P 2 on the signal potential side each face the core material 11 b (to the inner wall of the cavity 11 a ) at the distance CL 2 larger than the distance CL 1 , or the like. This arrangement can avoid bringing the second terminals t 2 of the electronic components P 1 and P 2 into contact with the core material 11 b that is kept at a ground potential, if the positions of the electronic components P 1 and P 2 are somewhat displaced in a process of manufacturing the substrate with built-in electronic component. Consequently, an electromagnetic failure due to such a contact can be prevented, and defects or the like of the electronic components P 1 and P 2 can be prevented. Further, if the first terminals t 1 that are each kept at the ground potential are brought into contact with or close to each other, an electromagnetic failure does not occur. This also allows the defects or the like of the electronic components P 1 and P 2 to be prevented.

(a4) The electronic components P 1 and P 2 are arranged such that a direction connecting the first terminals t 1 and the second terminals t 2 is on an approximately straight line along the X-axis direction, and thus the length of the cavity 11 a in the Y-axis direction can be reduced. This allows a further reduction in area of the horizontal cross-section of the cavity 11 a to be achieved, resulting in a further contribution to the downsizing of the substrate with built-in electronic component.

(a5) The structure example shown in FIG. 2 has a wiring structure in which the ground wiring 15 is interposed between the two signal wirings 14 connected to the second terminals t 2 of the electronic components P 1 and P 2 . Consequently, in this structure example, also when signals with different potentials or with the same potential are individually input to the respective second terminals t 2 , the generation of noise interference between the two signal wirings 14 can be suppressed.

Second Embodiment

FIGS. 4 to 6

FIG. 4 is a horizontal cross-sectional view showing an arrangement of electronic components in a substrate with built-in electronic component according to a second embodiment of the present disclosure. FIG. 5 is a vertical cross-sectional view showing a structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 4 . FIG. 6 is a vertical cross-sectional view showing another structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 4 . It should be noted that FIG. 4 corresponds to a cross-sectional view taken along the line B-B of FIGS. 5 and 6 .

As shown in FIGS. 4 to 6 , the substrate with built-in electronic component in this embodiment includes a core layer 11 including a core material 11 b and a cavity 11 a , insulating layers 13 and 17 formed on the core layer 11 , and two electronic components P 1 and P 2 stored in the cavity 11 a.

The insulating layer 13 includes signal wirings 14 and ground wirings 15 and is provided on the upper surface of the core layer 11 . The signal wirings 14 and the ground wirings 15 are each formed in one wiring layer arranged in the insulating layer 13 . Conductor pads 16 connected to the signal wirings 14 are provided on the upper surface of the insulating layer 13 .

As in the insulating layer 13 , the insulating layer 17 includes signal wirings 18 and a ground wiring 19 and is provided on the lower surface of the core layer 11 . The signal wirings 18 and the ground wiring 19 are each formed in one wiring layer arranged in the insulating layer 17 . Conductor pads 20 connected to the signal wirings 18 are provided on the lower surface of the insulating layer 17 .

The insulating layers 13 and 17 each have the thickness of 30 to 90 μm, for example. Further, each of the signal wirings 14 and 18 , ground wirings 15 and 19 , and conductor pads 16 and 20 is made of metal such as copper and an copper alloy and has the thickness of 5 to 25 μm, for example.

The core material 11 b is made of a conductor such as copper and a copper alloy and has the thickness of 100 to 400 μm, for example. The core material 11 b is connected to the ground wiring 19 and is kept at a ground potential. The cavity 11 a has a horizontal cross section with an approximately rectangular shape and is formed by penetrating the core material 11 b in the Z-axis direction (thickness direction). The cavity 11 a contains an insulating material 12 that fills a gap between the inner side surface of the core material 11 b and each of the electronic components P 1 and P 2 . The insulating material 12 and the insulating layers 13 and 17 are each made of a synthetic resin of an epoxy resin, polyimide, a bismaleimide triazine resin, a resin containing any one of them and a reinforcing filler made of a silicon dioxide, or the like (not only a thermosetting resin but also a thermoplastic resin can be used).

Each of the electronic components P 1 and P 2 has an approximately rectangular parallelepiped shape and is configured such that one end portion and the other end portion of the electronic component are arranged on a straight line extending along the X-axis direction in this embodiment. Each of the electronic components P 1 and P 2 includes a first terminal t 1 and a second terminal t 2 . The first terminal t 1 is formed at the one end portion and connected to the ground wiring 15 . The second terminal t 2 is formed at the other end portion and connected to the signal wiring 14 . That is, the first terminal t 1 is used as a terminal on a ground potential side and the second terminal t 2 is used as a terminal on a signal potential side. Each of the electronic components P 1 and P 2 is an electronic component such as a capacitor, an inductor, a resistor, and a filter and may be a combination of the same kind of electronic components or a combination of different kinds of electronic components.

As shown in FIG. 4 , the first terminal t 1 has an end surface t 11 and a side surface t 12 . The end surface t 11 can be assumed to be an end surface at one end portion of each of the electronic components P 1 and P 2 , and the side surface t 12 can be assumed to be a surface that is connected to and substantially orthogonal to the end surface t 11 . Similarly, the second terminal t 2 also has an end surface t 21 and a side surface t 22 . The end surface t 21 can be assumed to be an end surface at the other end portion of each of the electronic components P 1 and P 2 , and the side surface t 22 can be assumed to be a surface that is connected to and substantially orthogonal to the end surface t 21 .

As shown in FIG. 4 , the two electronic components P 1 and P 2 are arranged such that their second terminals t 2 face each other in the X-axis direction (one axis direction) and the first terminal t 1 and the second terminal t 2 of each electronic component are arranged on a straight line along the X-axis direction. That is, the end surface t 11 of each of the first terminals t 1 faces the core material 11 b (to the inner wall of the cavity 11 a ) at a distance CL 3 via the insulating material 12 . Further, the end surfaces t 21 of the second terminals t 2 face each other at a distance CL 4 larger than the distance CL 3 via the insulating material 12 . Furthermore, each of the side surfaces t 12 and t 22 of the first terminals t 1 and the second terminals t 2 faces the core material 11 b (to the inner wall of the cavity 11 a ) at a distance (not denoted by a reference symbol) larger than the distance CL 3 via the insulating material 12 .

In the structure example shown in FIG. 5 , the first terminal t 1 of the electronic component P 1 is connected to the ground wiring 15 (on the left-hand side of FIG. 5 ) via a conductor via 15 a , and the first terminal t 1 of the electronic component P 2 is connected to the different ground wiring 15 (on the right-hand side of FIG. 5 ) via a conductor via 15 a . Further, the second terminal t 2 of the electronic component P 1 is connected to the signal wiring 14 (on the left-hand side of FIG. 5 ) via a conductor via 14 a , and the second terminal t 2 of the electronic component P 2 is connected to the different signal wiring 14 (on the right-hand side of FIG. 5 ) via a conductor via 14 a . Furthermore, each of the signal wirings 14 is connected to a corresponding conductor pad 16 via a conductor via 16 a.

In other words, in the structure example shown in FIG. 5 , the first terminals t 1 of the two electronic components P 1 and P 2 are each kept at a ground potential (for example, 0 V), and the second terminals t 2 of the two electronic components P 1 and P 2 are each configured to receive an input of a signal individually from the corresponding conductor pad 16 . Specifically, not only signals with different potentials (for example, +3 V, +5 V, or −3 V) but also signals with the same potential (for example, +3 V, +5 V, or −3 V) can be input to the second terminals t 2 of the electronic components P 1 and P 2 . Herein, the signals may be analog or digital.

As another structure example, as shown in FIG. 6 , the first terminal t 1 of the electronic component P 1 is connected to the ground wiring 15 (on the left-hand side of FIG. 6 ) via the conductor via 15 a , and the first terminal t 1 of the electronic component P 2 is connected to the different ground wiring 15 (on the right-hand side of FIG. 6 ) via the conductor via 15 a . Further, the second terminal t 2 of the electronic component P 1 is connected to the signal wiring 14 (on the left-hand side of FIG. 6 ) via the conductor via 14 a , and the second terminal t 2 of the electronic component P 2 is connected to the different signal wiring 14 (on the right-hand side of FIG. 6 ) via the conductor via 14 a . Additionally, the signal wirings 14 are connected to a common conductor pad 16 via the conductor vias 16 a.

In other words, in the structure example shown in FIG. 6 , the first terminals t 1 of the two electronic components P 1 and P 2 are each at a ground potential (for example, 0 V), and the second terminals t 2 of the two electronic components P 1 and P 2 are each configured to receive an input of a signal from the common conductor pad 16 . Specifically, signals with the same potential (for example, +3 V, +5 V, or −3 V) can be input to the second terminals t 2 of the electronic components P 1 and P 2 . Herein, the signals may be analog or digital.

According to the substrate with built-in electronic component in this embodiment, the following effects can be obtained.

(b1) One cavity 11 a stores the two electronic components P 1 and P 2 , and thus the electronic components P 1 and P 2 in the cavity 11 a can have a high degree of freedom in arrangement (degree of freedom in position or orientation). Further, the two electronic components P 1 and P 2 stored in the cavity 11 a are arranged such that the second terminals t 2 on the signal potential side face each other in a non-contact manner. Consequently, compared with the case where the first terminal t 1 on the ground potential side and the second terminal t 2 on the signal potential side are arranged so as to face each other, mutual interference, such as crosstalk, between the electronic components P 1 and P 2 can be suppressed.

(b2) The first terminals t 1 of the two electronic components P 1 and P 2 on the ground potential side each face the core material 11 b (to the inner wall of the cavity 11 a ), and thus the distance CL 3 between each first terminal t 1 and the core material 11 b can be reduced as much as possible and the length of the cavity 11 a in the X-axis direction can be reduced. This allows a reduction in area of the horizontal cross-section of the cavity 11 a to be achieved, resulting in a contribution to the downsizing of the substrate with built-in electronic component.

(b3) The second terminals t 2 of the two electronic components P 1 and P 2 face each other at the distance CL 4 larger than the distance CL 3 , or the like. This arrangement can avoid bringing the second terminals t 2 of the electronic components P 1 and P 2 into contact with each other and with the core material 11 b , if the positions of the electronic components P 1 and P 2 are somewhat displaced in a process of manufacturing the substrate with built-in electronic component. Consequently, an electromagnetic failure due to such a contact can be prevented, and defects or the like of the electronic components P 1 and P 2 can be prevented. Further, if the first terminals t 1 are brought into contact with or close to the inner wall of the cavity 11 a , an electromagnetic failure does not occur because the first terminals t 1 are each kept at the ground potential. This also allows the defects or the like of the electronic components P 1 and P 2 to be prevented.

(b4) The electronic components P 1 and P 2 are arranged such that a direction connecting the first terminals t 1 and the second terminals t 2 is on an approximately straight line along the X-axis direction, and thus the length of the cavity 11 a in the Y-axis direction can be reduced. This allows a further reduction in area of the horizontal cross-section of the cavity 11 a to be achieved, resulting in a further contribution to the downsizing of the substrate with built-in electronic component.

(b5) The distance CL 3 between the first terminal t 1 and the core material 11 b can be reduced in each of the two electronic components P 1 and P 2 , and thus the distance CL 4 between the second terminals t 2 can be further increased. Consequently, as in the structure example shown in FIG. 5 , also when signals with different potentials or with the same potential are individually input to the respective second terminals t 2 of the electronic components P 1 and P 2 , a distance between the two signal wirings 14 connected to the respective second terminals t 2 can be increased as much as possible and the generation of noise interference between the two signal wirings 14 can be suppressed.

Third Embodiment

FIGS. 7 and 8

FIG. 7 is a horizontal cross-sectional view showing an arrangement of electronic components in a substrate with built-in electronic component according to a third embodiment of the present disclosure. FIG. 8 is a vertical cross-sectional view showing a structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 7 . It should be noted that FIG. 7 corresponds to a cross-sectional view taken along the line C-C of FIG. 8 .

As shown in FIGS. 7 and 8 , the substrate with built-in electronic component in this embodiment includes a core layer 11 including a core material 11 b and a cavity 11 a , insulating layers 13 and 17 formed on the core layer 11 , and two electronic components P 1 and P 2 stored in the cavity 11 a.

The insulating layer 13 includes signal wirings 14 and a ground wiring 15 and is provided on the upper surface of the core layer 11 . The signal wirings 14 and the ground wiring 15 are each formed in one wiring layer arranged in the insulating layer 13 . Conductor pads 16 connected to the signal wirings 14 are provided on the upper surface of the insulating layer 13 .

As in the insulating layer 13 , the insulating layer 17 includes signal wirings 18 and a ground wiring 19 and is provided on the lower surface of the core layer 11 . The signal wirings 18 and the ground wiring 19 are each formed in one wiring layer arranged in the insulating layer 17 . Conductor pads 20 connected to the signal wirings 18 are provided on the lower surface of the insulating layer 17 .

The insulating layers 13 and 17 each have the thickness of 30 to 90 μm, for example. Further, each of the signal wirings 14 and 18 , ground wirings 15 and 19 , and conductor pads 16 and 20 is made of metal such as copper and an copper alloy and has the thickness of 5 to 25 μm, for example.

The core material 11 b is made of a conductor such as copper and a copper alloy and has the thickness of 100 to 400 μm, for example. The core material 11 b is connected to the ground wiring 19 and is kept at a ground potential. The cavity 11 a has a horizontal cross section with an approximately rectangular shape and is formed by penetrating the core material 11 b in the Z-axis direction (thickness direction). The cavity 11 a contains an insulating material 12 that fills a gap between the inner side surface of the core material 11 b and each of the electronic components P 1 and P 2 . The insulating material 12 and the insulating layers 13 and 17 are each made of a synthetic resin of an epoxy resin, polyimide, a bismaleimide triazine resin, a resin containing any one of them and a reinforcing filler made of a silicon dioxide, or the like (not only a thermosetting resin but also a thermoplastic resin can be used).

Each of the electronic components P 1 and P 2 has an approximately rectangular parallelepiped shape and is configured such that one end portion and the other end portion of the electronic component are arranged on a straight line extending along the X-axis direction in this embodiment. Each of the electronic components P 1 and P 2 includes a first terminal t 1 and a second terminal t 2 . The first terminal t 1 is formed at the one end portion and connected to the ground wiring 15 . The second terminal t 2 is formed at the other end portion and connected to the signal wiring 14 . That is, the first terminal t 1 is used as a terminal on a ground potential side and the second terminal t 2 is used as a terminal on a signal potential side. Each of the electronic components P 1 and P 2 is an electronic component such as a capacitor, an inductor, a resistor, and a filter and may be a combination of the same kind of electronic components or a combination of different kinds of electronic components.

As shown in FIG. 7 , the first terminal t 1 has an end surface t 11 and a side surface t 12 . The end surface t 11 can be assumed to be an end surface at one end portion of each of the electronic components P 1 and P 2 , and the side surface t 12 can be assumed to be a surface that is connected to and substantially orthogonal to the end surface t 11 . Similarly, the second terminal t 2 also has an end surface t 21 and a side surface t 22 . The end surface t 21 can be assumed to be an end surface at the other end portion of each of the electronic components P 1 and P 2 , and the side surface t 22 can be assumed to be a surface that is connected to and substantially orthogonal to the end surface t 21 .

As shown in FIG. 7 , the two electronic components P 1 and P 2 are arranged such that their first terminals t 1 face each other in the Y-axis direction (one axis direction) and their second terminals t 2 face each other in the Y-axis direction. That is, the two electronic components P 1 and P 2 are arranged to face each other in the Y-axis direction (one axis direction) and are each arranged such that the first terminal t 1 and the second terminal t 2 are arranged on a straight line along the X-axis direction (direction orthogonal to the one axis direction). Further, the side surfaces t 12 of the first terminals t 1 face each other via the insulating material 12 , and the end surfaces t 11 of the first terminals t 1 each face the core material 11 b (to the inner wall of the cavity 11 a ) via the insulating material 12 . In contrast, the side surfaces t 22 of the second terminals t 2 face each other via the insulating material 12 , and the end surfaces t 21 of the second terminals t 2 each face the core material 11 b (to the inner wall of the cavity 11 a ) at a distance CL 6 larger than a distance CL 5 via the insulating material 12 . Furthermore, among the side surfaces t 12 and t 22 of the first terminals t 1 and the second terminals t 2 , the side surfaces t 12 and t 22 that do not face other side surfaces t 12 and t 22 each face the core material 11 b (to the inner wall of the cavity 11 a ) at a distance (not denoted by a reference symbol) larger than the distance CL 5 via the insulating material 12 .

In the structure example shown in FIG. 8 , the first terminals t 1 of the electronic components P 1 and P 2 on the ground potential side are connected to the common ground wiring 15 via conductor vias 15 a . Further, the second terminal t 2 of the electronic component P 1 is connected to the signal wiring 14 via a conductor via 14 a , and the second terminal t 2 of the electronic component P 2 is connected to the different signal wiring 14 (not shown in FIG. 8 ) via a conductor via 14 a . Each of the signal wirings 14 is connected to a common conductor pad 16 via conductor vias 16 a . In such a manner, the second terminals t 2 of the electronic components P 1 and P 2 , the side surfaces t 22 of which face each other in the Y-axis direction, are connected to each other, and thus the electronic components P 1 and P 2 are connected parallel to each other.

In other words, in the structure example shown in FIG. 8 , the first terminals t 1 of the two electronic components P 1 and P 2 are each at a ground potential (for example, 0 V), and the second terminals t 2 of the two electronic components P 1 and P 2 are each configured to receive an input of a signal from the common conductor pad 16 . Specifically, signals with the same potential (for example, +3 V, +5 V, or −3 V) can be input to the second terminals t 2 of the electronic components P 1 and P 2 . Herein, the signals may be analog or digital.

It should be noted that as another structure example (referring to in FIG. 8 ), the second terminals t 2 of the electronic components P 1 and P 2 may be connected to different conductor pads 16 and those conductor pads 16 may be connected to each other via a common wiring (not shown in the figure) or the like, and thus those second terminals t 2 may be connected to each other. This also allows the signals with the same potential to be input to the respective second terminals t 2 of the electronic components P 1 and P 2 .

In such a manner, when the two electronic components P 1 and P 2 are connected parallel to each other and used as one functional circuit, mutual interference, such as crosstalk, between the electronic components P 1 and P 2 is not seen as a problem, and thus the second terminals t 2 on the signal potential side may be arranged adjacently to each other. It should be noted that the phrase of being “connected parallel” refers to a case where the first terminals t 1 of the plurality of electronic components are connected to each other and the second terminals t 2 of the electronic components are connected to each other. Additionally, a specific connection method for the terminals is not particularly limited, and when electrical connections between the first terminals t 1 and between the second terminals t 2 are obtained via the conductor pads 16 , other wirings, and the like, a parallel circuit can be substantially achieved.

According to the substrate with built-in electronic component in this embodiment, the following effects can be obtained.

(c1) One cavity 11 a stores the two electronic components P 1 and P 2 , and thus the electronic components P 1 and P 2 in the cavity 11 a can have a high degree of freedom in arrangement (degree of freedom in position or orientation). Further, the two electronic components P 1 and P 2 are arranged such that the first terminals t 1 on the ground potential side face each other in a non-contact manner and the second terminals t 2 on the signal potential side face each other in a non-contact manner. Additionally, the distance CL 6 between each of the second terminals t 2 of the two electronic components P 1 and P 2 on the signal potential side and the core material 11 b (to the inner wall of the cavity 11 a ) is large, and thus interference between the second terminal t 2 and the ground (e.g., noise imparted to the ground potential of the core material 11 b by the second terminal t 2 ) can be suppressed.

(c2) The first terminals t 1 of the two electronic components P 1 and P 2 on the ground potential side each face the core material 11 b , and thus the distance CL 5 between each of the first terminals t 1 and the core material 11 b (the inner wall of the cavity 11 a ) can be reduced as much as possible and the length of the cavity 11 a in the X-axis direction can be reduced. This allows a reduction in area of the horizontal cross-section of the cavity 11 a to be achieved, resulting in a contribution to the downsizing of the substrate with built-in electronic component.

(c3) The second terminals t 2 of the two electronic components P 1 and P 2 on the signal potential side each face the core material 11 b (to the inner wall of the cavity 11 a ) at the distance CL 6 larger than the distance CL 5 , or the like. This arrangement can avoid bringing the second terminals t 2 of the electronic components P 1 and P 2 on the signal potential side into contact with the core material 11 b that is kept at a ground potential, if the positions of the electronic components P 1 and P 2 are somewhat displaced in a process of manufacturing the substrate with built-in electronic component. Consequently, an electromagnetic failure due to such a contact can be prevented, and defects or the like of the electronic components P 1 and P 2 can be prevented. Further, if the first terminals t 1 are brought into contact with or close to the core material 11 b (to the inner wall of the cavity 11 a ) that is kept at a ground potential, an electromagnetic failure does not occur because the first terminals t 1 are each kept at the ground potential. This also allows the defects or the like of the electronic components P 1 and P 2 to be prevented.

(c4) The two electronic components P 1 and P 2 are arranged such that a direction connecting the first terminal t 1 and the second terminal t 2 of one of the two electronic components P 1 and P 2 is parallel to a direction connecting the first terminal t 1 and the second terminal t 2 of the other electronic component. Thus, the length of the cavity 11 a in the Y-axis direction can be reduced. This allows a further reduction in area of the horizontal cross-section of the cavity 11 a to be achieved, resulting in a further contribution to the downsizing of the substrate with built-in electronic component.

Fourth Embodiment

FIGS. 9 and 10

FIG. 9 is a horizontal cross-sectional view showing an arrangement of electronic components in a substrate with built-in electronic component according to a fourth embodiment of the present disclosure. FIG. 10 is a vertical cross-sectional view showing a structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 9 . It should be noted that FIG. 9 corresponds to a cross-sectional view taken along the line D-D of FIG. 10 .

As shown in FIGS. 9 and 10 , the substrate with built-in electronic component in this embodiment includes a core layer 11 including a core material 11 b and a cavity 11 a , insulating layers 13 and 17 formed on the core layer 11 , and two electronic components P 1 and P 2 stored in the cavity 11 a.

The insulating layer 13 includes signal wirings 14 and a ground wiring 15 and is provided on the upper surface of the core layer 11 . The signal wirings 14 and the ground wiring 15 are each formed in one wiring layer arranged in the insulating layer 13 . Conductor pads 16 connected to the signal wirings 14 are provided on the upper surface of the insulating layer 13 .

As in the insulating layer 13 , the insulating layer 17 includes signal wirings 18 and a ground wiring 19 and is provided on the lower surface of the core layer 11 . The signal wirings 18 and the ground wiring 19 are each formed in one wiring layer arranged in the insulating layer 17 . Conductor pads 20 connected to the signal wirings 18 are provided on the lower surface of the insulating layer 17 .

The insulating layers 13 and 17 each have the thickness of 30 to 90 μm, for example. Further, each of the signal wirings 14 and 18 , ground wirings 15 and 19 , and conductor pads 16 and 20 is made of metal such as copper and an copper alloy and has the thickness of 5 to 25 μm, for example.

The core material 11 b is made of a conductor such as copper and a copper alloy and has the thickness of 100 to 400 μm, for example. The core material 11 b is connected to the ground wiring 19 and is kept at a ground potential. The cavity 11 a has a horizontal cross section with an approximately rectangular shape and is formed by penetrating the core material 11 b in the Z-axis direction (thickness direction). The cavity 11 a contains an insulating material 12 that fills a gap between the inner side surface of the core material 11 b and each of the electronic components P 1 and P 2 . The insulating material 12 and the insulating layers 13 and 17 are each made of a synthetic resin of an epoxy resin, polyimide, a bismaleimide triazine resin, a resin containing any one of them and a reinforcing filler made of a silicon dioxide, or the like (not only a thermosetting resin but also a thermoplastic resin can be used).

Each of the electronic components P 1 and P 2 has an approximately rectangular parallelepiped shape. The electronic component P 1 is configured such that one end portion and the other end portion are arranged on a straight line extending along the X-axis direction, and the other electronic component P 2 is configured such that one end portion and the other end portion are arranged on a straight line extending along the Y-axis direction. Each of the electronic components P 1 and P 2 includes a first terminal t 1 and a second terminal t 2 . The first terminal t 1 is formed at one end portion and connected to the ground wiring 15 . The second terminal t 2 is formed at the other end portion and connected to the signal wiring 14 . Each of the electronic components P 1 and P 2 is an electronic component such as a capacitor, an inductor, a resistor, and a filter and may be a combination of the same kind of electronic components or a combination of different kinds of electronic components.

As shown in FIG. 9 , the first terminal t 1 has an end surface t 11 and a side surface t 12 . The end surface t 11 can be assumed to be an end surface at one end portion of each of the electronic components P 1 and P 2 , and the side surface t 12 can be assumed to be a surface that is connected to and substantially orthogonal to the end surface t 11 . Similarly, the second terminal t 2 also has an end surface t 21 and a side surface t 22 . The end surface t 21 can be assumed to be an end surface at the other end portion of each of the electronic components P 1 and P 2 , and the side surface t 22 can be assumed to be a surface that is connected to and substantially orthogonal to the end surface t 21 .

As shown in FIG. 9 , the two electronic components P 1 and P 2 are arranged such that their first terminals t 1 face each other in the Y-axis direction and a direction connecting the first terminal t 1 and the second terminal t 2 of one of the electronic components P 1 and P 2 forms an approximately right angle with a direction connecting the first terminal t 1 and the second terminal t 2 of the other electronic component. That is, the electronic component P 1 is arranged such that the first terminal t 1 and the second terminal t 2 are arranged on a straight line along the X-axis direction (one axis direction), and the electronic component P 2 is arranged such that the first terminal t 1 and the second terminal t 2 are arranged on a straight line along the Y-axis direction (direction orthogonal to the one axis direction). Further, the side surface t 12 of the first terminal t 1 of the electronic component P 1 faces the end surface t 11 of the first terminal t 1 of the electronic component P 2 at a distance CL 7 via the insulating material 12 . The side surface t 22 of the second terminal t 2 of the electronic component P 1 faces the core material 11 b (to the inner wall of the cavity 11 a ) at a distance CL 8 larger than the distance CL 7 via the insulating material 12 , and the end surface t 21 of the second terminal t 2 of the electronic component P 2 also faces the core material 11 b (to the inner wall of the cavity 11 a ) at the distance CL 8 via the insulating material 12 . Further, the end surface t 21 of the second terminal t 2 of the electronic component P 1 and the side surface t 22 of the second terminal t 2 of the electronic component P 2 each face the core material 11 b (to the inner wall of the cavity 11 a ) at a distance (not denoted by a reference symbol) larger than the distance CL 7 via the insulating material 12 .

In the structure example shown in FIG. 10 , the first terminals t 1 of the electronic components P 1 and P 2 are connected to the common ground wiring 15 via conductor vias 15 a . Further, the second terminal t 2 of the electronic component P 1 is connected to the signal wiring 14 via a conductor via 14 a , and the second terminal t 2 of the electronic component P 2 is connected to the different signal wiring 14 (not shown in FIG. 10 ) via a conductor via 14 a . Further, each of the signal wirings 14 is connected to a corresponding conductor pad 16 via a conductor via 16 a.

In other words, in the structure example shown in FIG. 10 , the first terminals t 1 of the two electronic components P 1 and P 2 are each at a ground potential (for example, 0 V). In contrast, the second terminals t 2 of the two electronic components P 1 and P 2 are each configured to receive an input of a signal individually from the corresponding conductor pad 16 . Specifically, not only signals with different potentials (for example, +3 V, +5 V, or −3 V) but also signals with the same potential (for example, +3 V, +5 V, or −3 V) can be input to the second terminals t 2 of the electronic components P 1 and P 2 . Herein, the signals may be analog or digital.

As another structure example (referring to FIG. 10 ), the first terminals t 1 of the electronic components P 1 and P 2 are connected to the common ground wiring 15 via the conductor vias 15 a . Further, the second terminal t 2 of the electronic component P 1 is connected to the signal wiring 14 via the conductor via 14 a , and the second terminal t 2 of the electronic component P 2 is connected to the different signal wiring 14 (not shown in FIG. 10 ) via the different conductor via 14 a . Additionally, the signal wirings 14 are connected to a common conductor pad 16 via the conductor vias 16 a.

In other words, in this structure example, the first terminals t 1 of the two electronic components P 1 and P 2 stored in the cavity 11 a are each at a ground potential (for example, 0 V), and the second terminals t 2 of the two electronic components P 1 and P 2 are each configured to receive an input of a signal from the common conductor pad 16 . Specifically, signals with the same potential (for example, +3 V, +5 V, or −3 V) can be input to the second terminals t 2 of the electronic components P 1 and P 2 . Herein, the signals may be analog or digital.

According to the substrate with built-in electronic component in this embodiment, the following effects can be obtained.

(d1) One cavity 11 a stores the two electronic components P 1 and P 2 , and thus the electronic components P 1 and P 2 in the cavity 11 a can have a high degree of freedom in arrangement (degree of freedom in position or orientation). Further, the two electronic components P 1 and P 2 stored in one cavity 11 a are arranged such that the first terminals t 1 on the ground potential side face each other in a non-contact manner. Consequently, compared with the case where the first terminal t 1 on the ground potential side and the second terminal t 2 on the signal potential side are arranged so as to face each other, mutual interference, such as crosstalk, between the electronic components P 1 and P 2 can be suppressed.

(d2) The first terminals t 1 of the two electronic components P 1 and P 2 on the ground potential side face each other, and thus the distance CL 7 between the first terminals t 1 can be reduced as much as possible and the length of the cavity 11 a in the Y-axis direction can be reduced. This allows a reduction in area of the horizontal cross-section of the cavity 11 a to be achieved, resulting in a contribution to the downsizing of the substrate with built-in electronic component.

(d3) The second terminals t 2 of the two electronic components P 1 and P 2 on the signal potential side each face the core material 11 b (to the inner wall of the cavity 11 a ) at the distance CL 8 larger than the distance CL 7 , or the like. This arrangement can avoid bringing the second terminals t 2 of the electronic components P 1 and P 2 on the signal potential side into contact with the core material 11 b that is kept at a ground potential, if the positions of the electronic components P 1 and P 2 are somewhat displaced in a process of manufacturing the substrate with built-in electronic component. Consequently, an electromagnetic failure due to such a contact can be prevented, and defects or the like of the electronic components P 1 and P 2 can be prevented. Further, if the first terminals t 1 that are each kept at a ground potential are brought into contact with or close to each other, an electromagnetic failure does not occur. This also allows the defects or the like of the electronic components P 1 and P 2 to be prevented.

(d4) The electronic components P 1 and P 2 are arranged such that a direction connecting the first terminal t 1 and the second terminal t 2 of one of the electronic components P 1 and P 2 forms an approximately right angle with a direction connecting the first terminal t 1 and the second terminal t 2 of the other electronic component. This allows the shape of the cavity 11 a to be set according to the outline that surrounds both of the electronic components P 1 and P 2 . This allows a further reduction in area of the horizontal cross-section of the cavity 11 a to be achieved, resulting in a further contribution to the downsizing of the substrate with built-in electronic component.

Fifth Embodiment

FIGS. 11 to 13

FIG. 11 is a horizontal cross-sectional view showing an arrangement of electronic components in a substrate with built-in electronic component according to a fifth embodiment of the present disclosure. FIG. 12 is a vertical cross-sectional view showing a structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 11 . FIG. 13 is a vertical cross-sectional view showing another structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 11 . It should be noted that FIG. 11 corresponds to a cross-sectional view taken along the line E-E of FIGS. 12 and 13 .

As shown in FIGS. 11 to 13 , the substrate with built-in electronic component in this embodiment includes a core layer 11 including a core material 11 b and a cavity 11 a , insulating layers 13 and 17 formed on the core layer 11 , and four electronic components P 1 to P 4 stored in the cavity 11 a.

The insulating layer 13 includes signal wirings 14 and ground wirings 15 and is provided on the upper surface of the core layer 11 . The signal wirings 14 and the ground wirings 15 are each formed in one wiring layer arranged in the insulating layer 13 . Conductor pads 16 connected to the signal wirings 14 are provided on the upper surface of the insulating layer 13 .

As in the insulating layer 13 , the insulating layer 17 includes signal wirings 18 and a ground wiring 19 and is provided on the lower surface of the core layer 11 . The signal wirings 18 and the ground wiring 19 are each formed in one wiring layer arranged in the insulating layer 17 . Conductor pads 20 connected to the signal wirings 18 are provided on the lower surface of the insulating layer 17 .

The insulating layers 13 and 17 each have the thickness of 30 to 90 μm, for example. Further, each of the signal wirings 14 and 18 , ground wirings 15 and 19 , and conductor pads 16 and 20 is made of metal such as copper and an copper alloy and has the thickness of 5 to 25 μm, for example.

The core material 11 b is made of a conductor such as copper and a copper alloy and has the thickness of 100 to 400 μm, for example. The core material 11 b is connected to the ground wiring 19 and is kept at a ground potential. The cavity 11 a has a horizontal cross section with an approximately rectangular shape and is formed by penetrating the core material 11 b in the Z-axis direction (thickness direction). The cavity 11 a contains an insulating material 12 that fills a gap between the inner side surface of the core material 11 b and each of the electronic components P 1 to P 4 . The insulating material 12 and the insulating layers 13 and 17 are each made of a synthetic resin of an epoxy resin, polyimide, a bismaleimide triazine resin, a resin containing any one of them and a reinforcing filler made of a silicon dioxide, or the like (not only a thermosetting resin but also a thermoplastic resin can be used).

Each of the electronic components P 1 to P 4 has an approximately rectangular parallelepiped shape and is configured such that one end portion and the other end portion of the electronic component are arranged on a straight line extending along the X-axis direction in this embodiment. Each of the electronic components P 1 to P 4 includes a first terminal t 1 and a second terminal t 2 . The first terminal t 1 is formed at the one end portion and connected to the ground wiring 15 . The second terminal t 2 is formed at the other end portion and connected to the signal wiring 14 . That is, the first terminal t 1 is used as a terminal on a ground potential side and the second terminal t 2 is used as a terminal on a signal potential side. Each of the electronic components P 1 to P 4 is an electronic component such as a capacitor, an inductor, a resistor, and a filter and may be a combination of the same kind of electronic components or a combination of different kinds of electronic components.

As shown in FIG. 11 , the first terminal t 1 has an end surface t 11 and a side surface t 12 . The end surface t 11 can be assumed to be an end surface at one end portion of each of the electronic components P 1 to P 4 , and the side surface t 12 can be assumed to be a surface that is connected to and substantially orthogonal to the end surface t 11 . Similarly, the second terminal t 2 also has an end surface t 21 and a side surface t 22 . The end surface t 21 can be assumed to be an end surface at the other end portion of each of the electronic components P 1 to P 4 , and the side surface t 22 can be assumed to be a surface that is connected to and substantially orthogonal to the end surface t 21 .

As shown in FIG. 11 , the four electronic components P 1 to P 4 are arranged such that the first terminals t 1 of the electronic components P 1 and P 2 face each other and the first terminals t 1 of the electronic components P 3 and P 4 face each other in the X-axis direction (one axis direction), and the first terminal t 1 and the second terminal t 2 of each of the four electronic components P 1 to P 4 are arranged on a straight line along the X-axis direction. Further, in this embodiment, the four electronic components P 1 to P 4 include a set G 1 including the electronic components P 1 and P 3 and a set G 2 including the electronic components P 2 and P 4 . The second terminals t 2 of the electronic components P 1 and P 3 in the set G 1 are connected to each other. The second terminals t 2 of the electronic components P 2 and P 4 in the set G 2 are connected to each other. In the electronic components P 1 and P 3 of the set G 1 , the side surfaces t 12 of the first terminals t 1 face each other via the insulating material 12 , and the side surfaces t 22 of the second terminals t 2 face each other via the insulating material 12 . Similarly, in the electronic components P 2 and P 4 of the set G 2 , the side surfaces t 12 of the first terminals t 1 face each other via the insulating material 12 , and the side surfaces t 22 of the second terminals t 2 face each other via the insulating material 12 .

In the two sets G 1 and G 2 , the end surfaces t 11 of the first terminals t 1 of the electronic components P 1 and P 3 included in the set G 1 face the end surfaces t 11 of the first terminals t 1 of the electronic components P 2 and P 4 included in the set G 2 in the X-axis direction. That is, the end surface t 11 of the first terminal t 1 of the electronic component P 1 and the end surface t 11 of the first terminal t 1 of the electronic component P 2 face each other at a distance CL 9 , and the end surface t 11 of the first terminal t 1 of the electronic component P 3 and the end surface t 11 of the first terminal t 1 of the electronic component P 4 face each other at the distance CL 9 . Further, the end surfaces t 21 of the second terminals t 2 are each arranged to face the core material 11 b (to the inner wall of the cavity 11 a ) at a distance CL 10 larger than the distance CL 9 via the insulating material 12 . Furthermore, among the side surfaces t 12 and t 22 of the first terminals t 1 and the second terminals t 2 , the side surfaces t 12 and t 22 that do not face other side surfaces t 12 and t 22 each face the core material 11 b (to the inner wall of the cavity 11 a ) at a distance (not denoted by a reference symbol) larger than the distance CL 9 via the insulating material 12 .

In the structure example shown in FIG. 12 , the first terminals t 1 of the electronic components P 1 and P 3 are connected to the common ground wiring 15 (on the left-hand side of FIG. 12 ) via conductor vias 15 a , and the first terminals t 1 of the electronic components P 2 and P 4 are connected to the different common ground wiring 15 (on the right-hand side of FIG. 12 ) via conductor vias 15 a . Further, the second terminal t 2 of the electronic component P 1 is connected to the signal wiring 14 (on the left-hand side of FIG. 12 ) via a conductor via 14 a , the second terminal t 2 of the electronic component P 2 is connected to the different signal wiring 14 (on the right-hand side of FIG. 12 ) via a conductor via 14 a , the second terminal t 2 of the electronic component P 3 is connected to another signal wiring 14 (not shown in FIG. 12 ) via a conductor via 14 a , and the second terminal t 2 of the electronic component P 4 is connected to another signal wiring 14 (not shown in FIG. 12 ) via a conductor via 14 a . Furthermore, the signal wiring 14 of the electronic component P 1 and the signal wiring 14 of the electronic component P 3 are connected to a common conductor pad 16 via corresponding conductor vias 16 a . In contrast, the signal wiring 14 of the electronic component P 2 and the signal wiring 14 of the electronic component P 4 are connected to a common conductor pad 16 via corresponding conductor vias 16 a.

In such a manner, the second terminals t 2 of the electronic components P 1 and P 3 , the side surfaces t 22 of which face each other in the Y-axis direction, are connected to each other and the second terminals t 2 of the electronic components P 2 and P 4 , the side surfaces t 22 of which face each other in the Y-axis direction, are connected to each other. Consequently, in this structure example, the electronic components P 1 and P 3 are connected parallel to each other and the electronic components P 2 and P 4 are connected parallel to each other.

In other words, in the structure example shown in FIG. 12 , the first terminals t 1 of the four electronic components P 1 to P 4 stored in the cavity 11 a are each at a ground potential (for example, 0 V). In contrast, the second terminals t 2 of the electronic components P 1 and P 3 facing each other in the Y-axis direction are each configured to receive an input of a signal from the common conductor pad 16 . Similarly, the second terminals t 2 of the electronic components P 2 and P 4 facing each other in the Y-axis direction are each also configured to receive an input of a signal from the common conductor pad 16 . Specifically, signals with the same potential (for example, +3 V, +5 V, or −3 V) can be input to the second terminals t 2 of the electronic components P 1 and P 3 , and signals with the same potential can be input to the second terminals t 2 of the electronic components P 2 and P 4 . Herein, the signals may be analog or digital.

As another structure example, as shown in FIG. 13 , the first terminals t 1 of the electronic components P 1 to P 4 on the ground potential side are connected to the common ground wiring 15 via the conductor vias 15 a . Further, the second terminal t 2 of the electronic component P 1 is connected to the signal wiring 14 (on the left-hand side of FIG. 13 ) via the conductor via 14 a , the second terminal t 2 of the electronic component P 2 is connected to the different signal wiring 14 (on the right-hand side of FIG. 13 ) via the conductor via 14 a , the second terminal t 2 of the electronic component P 3 is connected to another signal wiring 14 (not shown in FIG. 13 ) via the conductor via 14 a , and the second terminal t 2 of the electronic component P 4 is connected to another signal wiring 14 (not shown in FIG. 13 ) via the conductor via 14 a . Additionally, the signal wirings 14 are connected to a common conductor pad 16 via the conductor vias 16 a.

In such a manner, in the structure example shown in FIG. 13 , the second terminals t 2 of the electronic components P 1 to P 4 are connected to each other, the electronic components P 1 to P 4 including the electronic components P 1 and P 3 in which the side surfaces t 22 face each other in the Y-axis direction and the electronic components P 2 and P 4 in which the side surfaces t 22 face each other in the Y-axis direction. Consequently, in this structure example, the four electronic components P 1 to P 4 are connected parallel to each other.

In other words, in the structure example shown in FIG. 13 , the first terminals t 1 of the four electronic components P 1 to P 4 are each at a ground potential (for example, 0 V), and the second terminals t 2 of the four electronic components P 1 to P 4 are each configured to receive an input of a signal from the common conductor pad 16 . Specifically, signals with the same potential (for example, +3 V, +5 V, or −3 V) can be input to the second terminals t 2 of the respective electronic components P 1 to P 4 . Herein, the signals may be analog or digital.

It should be noted that as another structure example (referring to FIG. 12 ), the second terminals t 2 of the four electronic components P 1 to P 4 may be connected to different conductor pads 16 . In this case, the conductor pads 16 of the electronic components P 1 and P 3 may be connected to each other via a common wiring or the like and the conductor pads 16 of the electronic components P 2 and P 4 may be connected to each other via another common wiring or the like, and thus those second terminals t 2 in each set of the electronic components can be connected to each other. This also allows the signals with the same potential to be input to the second terminals t 2 of the electronic components P 1 and P 3 and to the second terminals t 2 of the electronic components P 2 and P 4 , as in the structure example shown in FIG. 12 . Alternatively, in the case where the second terminals t 2 of the four electronic components P 1 to P 4 are connected to different conductor pads 16 , the conductor pads 16 of the electronic components P 1 to P 4 may be connected to one another via a common wiring or the like (not shown in the figure), and thus those second terminals t 2 may be connected to one another. This also allows the signals with the same potential to be input to the second terminals t 2 of the electronic components P 1 to P 4 as in the structure example shown in FIG. 13 .

In such a manner, in this embodiment, the electronic components included in each of the sets G 1 and G 2 are connected parallel to each other and used as a functional circuit. Consequently, in each of the sets G 1 and G 2 , mutual interference such as crosstalk is not seen as a problem, and thus the second terminals t 2 on the signal potential side may be arranged adjacently to each other. In contrast, mutual interference such as crosstalk may be problematic between the two sets G 1 and G 2 and between each of the electronic components P 1 and P 4 and the core material 11 b . In this regard, in this embodiment, such mutual interference is intended to be suppressed by the arrangement of the electronic components P 1 to P 4 as described above.

According to the substrate with built-in electronic component in this embodiment, the following effects can be obtained.

(e1) One cavity 11 a stores the four electronic components P 1 to P 4 , and thus the electronic components P 1 to P 4 in the cavity 11 a can have a high degree of freedom in arrangement (degree of freedom in position or orientation). Further, the four electronic components P 1 to P 4 stored in the cavity 11 a are arranged such that the first terminals t 1 on the ground potential side face each other in a non-contact manner. Consequently, compared with the case where the first terminal t 1 on the ground potential side and the second terminal t 2 on the signal potential side are arranged so as to face each other, mutual interference, such as crosstalk, between the two sets G 1 and G 2 can be suppressed.

(e2) The first terminals t 1 of the electronic components P 1 and P 2 on the ground potential side face each other and the first terminals t 1 of the electronic components P 3 and P 4 on the ground potential side face each other, and thus the distance CL 9 between the first terminals t 1 can be reduced as much as possible and the length of the cavity 11 a in the X-axis direction can be reduced. This allows a reduction in area of the horizontal cross-section of the cavity 11 a to be achieved, resulting in a contribution to the downsizing of the substrate with built-in electronic component.

(e3) The second terminals t 2 of the four electronic components P 1 to P 4 on the signal potential side each face the core material 11 b (to the inner wall of the cavity 11 a ) at the distance CL 10 larger than the distance CL 9 , or the like. This arrangement can avoid bringing the second terminals t 2 of the electronic components P 1 to P 4 into contact with the core material 11 b that is kept at a ground potential, if the positions of the electronic components P 1 to P 4 are somewhat displaced in a process of manufacturing the substrate with built-in electronic component. Consequently, an electromagnetic failure due to such a contact can be prevented, and defects or the like of the electronic components P 1 to P 4 can be prevented. Further, if the first terminals t 1 that are each kept at a ground potential are brought into contact with or close to each other, an electromagnetic failure does not occur. This also allows the defects or the like of the electronic components P 1 to P 4 to be prevented.

(e4) The four electronic components P 1 to P 4 are arranged such that a direction connecting the first terminals t 1 and the second terminals t 2 of the two electronic components P 1 and P 2 is on an approximately straight line and a direction connecting the first terminals t 1 and the second terminals t 2 of the other two electronic components P 3 and P 4 is on an approximately straight line and such that those directions are parallel to each other. Thus, the length of the cavity 11 a in the Y-axis direction can be reduced. This allows a further reduction in area of the horizontal cross-section of the cavity 11 a to be achieved, resulting in a further contribution to the downsizing of the substrate with built-in electronic component.

(e5) The structure example shown in FIG. 12 has a wiring structure in which the ground wirings 15 are interposed between the four signal wirings 14 connected to the second terminals t 2 of the electronic components P 1 to P 4 . Consequently, also when signals with different potentials or with the same potential are individually input to the respective second terminals t 2 of the electronic components P 1 to P 4 , the generation of noise interference between the four signal wirings 14 can be suppressed.

Sixth Embodiment

FIGS. 14 and 15

FIG. 14 is a horizontal cross-sectional view showing an arrangement of electronic components in a substrate with built-in electronic component according to a sixth embodiment of the present disclosure. FIG. 15 is a vertical cross-sectional view showing a structure example of the substrate with built-in electronic component that has the arrangement shown in FIG. 14 . It should be noted that FIG. 14 corresponds to a cross-sectional view taken along the line F-F of FIG. 15 .

As shown in FIGS. 14 and 15 , the substrate with built-in electronic component in this embodiment includes a core layer 11 including a core material 11 b and a cavity 11 a , insulating layers 13 and 17 formed on the core layer 11 , and four electronic components P 1 to P 4 stored in the cavity 11 a.

The insulating layer 13 includes signal wirings 14 and ground wirings 15 and is provided on the upper surface of the core layer 11 . The signal wirings 14 and the ground wirings 15 are each formed in one wiring layer arranged in the insulating layer 13 . Conductor pads 16 connected to the signal wirings 14 are provided on the upper surface of the insulating layer 13 .

As in the insulating layer 13 , the insulating layer 17 includes signal wirings 18 and a ground wiring 19 and is provided on the lower surface of the core layer 11 . The signal wirings 18 and the ground wiring 19 are each formed in one wiring layer arranged in the insulating layer 17 . Conductor pads 20 connected to the signal wirings 18 are provided on the lower surface of the insulating layer 17 .

The insulating layers 13 and 17 each have the thickness of 30 to 90 μm, for example. Further, each of the signal wirings 14 and 18 , ground wirings 15 and 19 , and conductor pads 16 and 20 is made of metal such as copper and an copper alloy and has the thickness of 5 to 25 μm, for example.

The core material 11 b is made of a conductor such as copper and a copper alloy and has the thickness of 100 to 400 μm, for example. The core material 11 b is connected to the ground wiring 19 and is kept at a ground potential. The cavity 11 a has a horizontal cross section with an approximately rectangular shape and is formed by penetrating the core material 11 b in the Z-axis direction (thickness direction). The cavity 11 a contains an insulating material 12 that fills a gap between the inner side surface of the core material 11 b and each of the electronic components P 1 to P 4 . The insulating material 12 and the insulating layers 13 and 17 are each made of a synthetic resin of an epoxy resin, polyimide, a bismaleimide triazine resin, a resin containing any one of them and a reinforcing filler made of a silicon dioxide, or the like (not only a thermosetting resin but also a thermoplastic resin can be used).

Each of the electronic components P 1 to P 4 has an approximately rectangular parallelepiped shape and is configured such that one end portion and the other end portion of the electronic component are arranged on a straight line extending along the X-axis direction in this embodiment. Each of the electronic components P 1 to P 4 includes a first terminal t 1 and a second terminal t 2 . The first terminal t 1 is formed at the one end portion and connected to the ground wiring 15 . The second terminal t 2 is formed at the other end portion and connected to the signal wiring 14 . That is, the first terminal t 1 is used as a terminal on a ground potential side and the second terminal t 2 is used as a terminal on a signal potential side. Each of the electronic components P 1 to P 4 is an electronic component such as a capacitor, an inductor, a resistor, and a filter and may be a combination of the same kind of electronic components or a combination of different kinds of electronic components.

As shown in FIG. 14 , the first terminal t 1 has an end surface t 11 and a side surface t 12 . The end surface t 11 can be assumed to be an end surface at one end portion of each of the electronic components P 1 to P 4 , and the side surface t 12 can be assumed to be a surface that is connected to and substantially orthogonal to the end surface t 11 . Similarly, the second terminal t 2 also has an end surface t 21 and a side surface t 22 . The end surface t 21 can be assumed to be an end surface at the other end portion of each of the electronic components P 1 to P 4 , and the side surface t 22 can be assumed to be a surface that is connected to and substantially orthogonal to the end surface t 21 .

As shown in FIG. 14 , the four electronic components P 1 to P 4 are arranged such that the second terminals t 2 of the electronic components P 1 and P 2 face each other and the second terminals t 2 of the electronic components P 3 and P 4 face each other in the X-axis direction (one axis direction), and the first terminal t 1 and the second terminal t 2 of each of the four electronic components P 1 to P 4 are arranged on a straight line along the X-axis direction. Further, in this embodiment, the four electronic components P 1 to P 4 include a set G 1 including the electronic components P 1 and P 3 and a set G 2 including the electronic components P 2 and P 4 . The second terminals t 2 of the electronic components P 1 and P 3 in the set G 1 are connected to each other. The second terminals t 2 of the electronic components P 2 and P 4 in the set G 2 are connected to each other. In the electronic components P 1 and P 3 of the set G 1 , the side surfaces t 12 of the first terminals t 1 face each other via the insulating material 12 , and the side surfaces t 22 of the second terminals t 2 face each other via the insulating material 12 . Similarly, in the electronic components P 2 and P 4 of the set G 2 , the side surfaces t 12 of the first terminals t 1 face each other via the insulating material 12 , and the side surfaces t 22 of the second terminals t 2 face each other via the insulating material 12 .

In the two sets G 1 and G 2 , the end surfaces t 21 of the second terminals t 2 of the electronic components P 1 and P 3 included in the set G 1 face the end surfaces t 21 of the second terminals t 2 of the electronic components P 2 and P 4 included in the set G 2 in the X-axis direction. That is, the end surface t 21 of the second terminal t 2 of the electronic component P 1 and the end surface t 21 of the second terminal t 2 of the electronic component P 2 face each other at a distance CL 12 , and the end surface t 21 of the second terminal t 2 of the electronic component P 3 and the end surface t 21 of the second terminal t 2 of the electronic component P 4 face each other at the distance CL 12 . Further, the end surfaces t 11 of the first terminals t 1 are each arranged to face the core material 11 b (to the inner wall of the cavity 11 a ) at a distance CL 11 smaller than the distance CL 12 via the insulating material 12 . Furthermore, among the side surfaces t 12 and t 22 of the first terminals t 1 and the second terminals t 2 , the side surfaces t 12 and t 22 that do not face other side surfaces t 12 and t 22 each face the core material 11 b (to the inner wall of the cavity 11 a ) at a distance (not denoted by a reference symbol) larger than the distance CL 11 via the insulating material 12 .

In the structure example shown in FIG. 15 , the first terminals t 1 of the two electronic components P 1 and P 3 are connected to the ground wiring 15 (on the left-hand side of FIG. 15 ) via conductor vias 15 a , and the first terminals t 1 of the other two electronic components P 2 and P 4 are connected to the ground wiring 15 (on the right-hand side of FIG. 15 ) via conductor vias 15 a . Further, the second terminal t 2 of the electronic component P 1 is connected to the signal wiring 14 (on the left-hand side of FIG. 15 ) via a conductor via 14 a , the second terminal t 2 of the electronic component P 2 is connected to the different signal wiring 14 (on the right-hand side of FIG. 15 ) via a conductor via 14 a , the second terminal t 2 of the electronic component P 3 is connected to another signal wiring 14 (not shown in FIG. 15 ) via a conductor via 14 a , and the second terminal t 2 of the electronic component P 4 is connected to another signal wiring 14 (not shown in FIG. 15 ) via a conductor via 14 a . Furthermore, the signal wiring 14 of the electronic component P 1 and the signal wiring 14 of the electronic component P 3 are connected to a common conductor pad 16 via corresponding conductor vias 16 a . In contrast, the signal wiring 14 of the electronic component P 2 and the signal wiring 14 of the electronic component P 4 are connected to a common conductor pad 16 via corresponding conductor vias 16 a.

In such a manner, the second terminals t 2 of the electronic components P 1 and P 3 , the side surfaces t 22 of which face each other in the Y-axis direction, are connected to each other and the second terminals t 2 of the electronic components P 2 and P 4 , the side surfaces t 22 of which face each other in the Y-axis direction, are connected to each other. Consequently, in this structure example, the electronic components P 1 and P 3 are connected parallel to each other and the electronic components P 2 and P 4 are connected parallel to each other.

In other words, in the structure example shown in FIG. 15 , the first terminals t 1 of the four electronic components P 1 to P 4 are each at a ground potential (for example, 0 V). In contrast, the second terminals t 2 of the electronic components P 1 and P 3 facing each other in the Y-axis direction are each configured to receive an input of a signal from the common conductor pad 16 . Similarly, the second terminals t 2 of the electronic components P 2 and P 4 facing each other in the Y-axis direction are each configured to receive an input of a signal from the common conductor pad 16 . Specifically, signals with the same potential (for example, +3 V, +5 V, or −3 V) can be input to the second terminals t 2 of the electronic components P 1 and P 3 , and signals with the same potential can be input to the second terminals t 2 of the electronic components P 2 and P 4 . Herein, the signals may be analog or digital.

In such a manner, in this embodiment, the electronic components included in each of the sets G 1 and G 2 are connected parallel to each other and used as a functional circuit. Consequently, in each of the sets G 1 and G 2 , mutual interference such as crosstalk is not seen as a problem, and thus the second terminals t 2 on the signal potential side may be arranged adjacently to each other. In contrast, mutual interference such as crosstalk may be problematic between the two sets G 1 and G 2 and between each of the electronic components P 1 to P 4 and the core material 11 b . In this regard, in this embodiment, such mutual interference is intended to be suppressed by the arrangement of the electronic components P 1 to P 4 as described above.

According to the substrate with built-in electronic component in this embodiment, the following effects can be obtained.

(f1) One cavity 11 a stores the four electronic components P 1 to P 4 , and thus each of the electronic components P 1 to P 4 in the cavity 11 a can have a high degree of freedom in arrangement (degree of freedom in position or orientation). Further, the four electronic components P 1 to P 4 stored in the cavity 11 a are arranged such that the second terminals t 2 on the signal potential side face each other in a non-contact manner. Consequently, compared with the case where the first terminal t 1 on the ground potential side and the second terminal t 2 on the signal potential side are arranged so as to face each other, mutual interference, such as crosstalk, between the two sets G 1 and G 2 stored in the cavity 11 a can be suppressed.

(f2) The first terminals t 1 of the four electronic components P 1 to P 4 on the ground potential side each face the core material 11 b , and thus the distance CL 11 between each of the first terminals t 1 and the core layer 11 (the inner wall of the cavity 11 a ) can be reduced as much as possible and the length of the cavity 11 a in the X-axis direction can be reduced. This allows a reduction in area of the horizontal cross-section of the cavity 11 a to be achieved, resulting in a contribution to the downsizing of the substrate with built-in electronic component.

(f3) The second terminals t 2 of the four electronic components P 1 to P 4 on the signal potential side face each other at the distance CL 12 larger than the distance CL 11 and each face the core material 11 b at a distance larger than the distance CL 11 . This arrangement can avoid bringing the second terminals t 2 of the electronic components P 1 to P 4 into contact with each other and with the core material 11 b that is kept at a ground potential, if the positions of the electronic components P 1 to P 4 are somewhat displaced in a process of manufacturing the substrate with built-in electronic component. Consequently, an electromagnetic failure due to such a contact can be prevented, and defects or the like of the electronic components P 1 to P 4 can be prevented. Further, if the first terminals t 1 are brought into contact with or close to the core material 11 b (the inner wall of the cavity 11 a ) that is also kept at a ground potential, an electromagnetic failure does not occur because the first terminals t 1 are each kept at a ground potential. This also allows the defects or the like of the electronic components P 1 to P 4 to be prevented.

(f4) The four electronic components P 1 to P 4 are arranged such that a direction connecting the first terminals t 1 and the second terminals t 2 of the two electronic components P 1 and P 2 is on an approximately straight line and a direction connecting the first terminals t 1 and the second terminals t 2 of the other two electronic components P 3 and P 4 is on an approximately straight line and such that those directions are parallel to each other. Thus, the length of the cavity 11 a in the Y-axis direction can be reduced. This allows a further reduction in area of the horizontal cross-section of the cavity 11 a to be achieved, resulting in a further contribution to the downsizing of the substrate with built-in electronic component.

(f5) The distance CL 11 between the first terminal t 1 and the core material 11 b can be reduced in each of the four electronic components P 1 to P 4 , and thus the distance CL 12 between the second terminals t 2 can be further increased. Consequently, in the structure example shown in FIG. 14 , also when signals with different potentials or with the same potential are individually input to the respective second terminals t 2 of the electronic components P 1 to P 4 , a distance between the four signal wirings 14 connected to the respective second terminals t 2 of the electronic components P 1 to P 4 can be increased as much as possible and the generation of noise interference between the four signal wirings 14 can be suppressed.

Other Embodiments

No Figure

(1) The first to sixth embodiments each describe the cavity 11 a that is formed by penetrating the core material 11 b in the Z-axis direction (thickness direction). Also in the case where the cavity 11 a is formed of a concave portion that does not penetrate the core material 11 b in the Z-axis direction (thickness direction), the same effects as the above-mentioned effects a1 to a5, b1 to b5, c1 to c4, d1 to d4, e1 to e5, and f1 to f5 can be produced.

(2) The first to sixth embodiments each describe the substrate in which the signal wiring 14 and the ground wiring 15 are provided in one wiring layer arranged in the insulating layer 13 located on the upper surface of the core layer 11 and the signal wiring 20 and the ground wiring 19 are provided in one wiring layer arranged in the insulating layer 17 located on the lower surface of the core layer 11 . Also in the cases where a different signal wiring and a different ground wiring are provided in the insulating layer 13 separately from the signal wiring 14 and the ground wiring 15 , where a different signal wiring and a different ground wiring are provided in the insulating layer 17 separately from the signal wiring 20 and the ground wiring 19 , and where the signal wiring 20 and the ground wiring 19 are eliminated from the insulating layer 17 on the lower surface of the core layer 11 , the same effects as the above-mentioned effects a1 to a5, b1 to b5, c1 to c4, d1 to d4, e1 to e5, and f1 to f5 can be produced.

(3) The first to sixth embodiments each describe the core material 11 b that is made of metal such as copper and a copper alloy and connected to the ground wiring 19 , but the core material 11 b may be a conductor made of a material other than the metal described above. Further, also in the case where the core material 11 b is made of a material other than the metal, for example, made of ceramics or a synthetic resin, the same effects as the above-mentioned effects a1 and a2, b1 and b2, c1 and c2, d1 and d2, e1 and e2, and f1 and f2 can be produced.

(4) Also in the case where one electronic component faces another electronic component in a direction that is orthogonal to a direction connecting the first terminal t 1 and the second terminal t 2 of the other electronic component (see FIGS. 7 and 11 ), the present disclosure is not limited to the structures in which the side surfaces t 12 of the first terminals t 1 face each other and the side surfaces t 22 of the second terminals t 2 face each other. For example, those electronic components may be arranged so as to be displaced in a direction connecting the first terminal t 1 and the second terminal t 2 (in the X-axis direction). Alternatively, two electronic components may have different sizes and the first terminals t 1 or the second terminals t 2 may face each other.