Image sensor having NMOS source follower with P-type doping in polysilicon gate

The present document relates to the field of CMOS image sensors.

CMOS image sensor array integrated circuits typically have at least two basic types of transistors, a P-type transistor having a P-doped poliysilicon gate, and an N-type transistor having an N-doped polysilicon gate. It is known that thresholds of N and P devices may be adjusted using an ion implant. CMOS image sensor array integrated circuits may have N and P type transistors with two or more threshold voltages determined by appropriately masked implants.

A common architecture for CMOS image sensor arrays uses a tiling unit within the sensor array. This tiling unit has at least one photodiode coupled to one or more transistors arranged to charge, or reset, an electrode of the photodiode to reverse-bias the photodiode to a known “reset” charge level. The photodiode is then exposed to a portion of a lit image, which may discharge some of the charge on the photodiode. The tiling unit also has a source follower coupled or coupleable to the photodiode and to a column sense line; the source follower serves as a buffer that allows reading of remaining charge on the photodiode.

In order to get good photodiode sensitivity, it is desirable to bias the photodiode to a high “reset” level. Black pixels, however, return nearly as high a voltage when read to the source follower as when charged. Should the reset charge level be near the power voltage to the source follower, and with a low threshold in the source-follower, this can give a low drop in the source-follower stage. With typical N-channel thresholds on the source follower, the follower has a low power-supply rejection ratio, potentially causing noise in pictures.

An image sensor array has a tiling unit comprising a source follower stage coupled to buffer signals from a photodiode when the unit is read onto a sense line. The source follower stage differs from conventional sensor arrays because it uses an N-channel transistor having a P-doped polysilicon gate. In embodiments, other transistors of the array have conventional N-channel transistors with N-doped polysilicon gates.

FIG. 1 is a schematic diagram of a tiling unit for a CMOS image sensor array.

FIG. 2 is an exemplary cross-section of a PRIOR ART conventional N-channel transistor with N-channel polysilicongate.

FIG. 3 is an exemplary cross-section of a modified N-channel transistor with P-channel polysilicon gate.

An embodiment of a tiling unit 100 for a CMOS image sensor array has a schematic diagram illustrated in FIG. 1 . This tiling unit has at least one pair of row-selection transistor 102 , and photodiode 104 . The row-selection transistor is enabled by a row-select line 103 . A precharge or reset 106 transistor, enabled by a reset signal 108 , is provided to couple a reset power supply 110 through a floating node 112 and row-selection transistor 102 to precharge or reset the photodiode 104 . Once the photodiode 104 is exposed to light, it is coupled through row selection transistor 102 and floating node 112 onto a gate of a source-follower transistor 114 , and read through a readout row selection transistor 116 onto a column data line 118 . The source follower 114 is powered by a power supply 120 . The floating node 112 of the tiling unit may, in some embodiments, also operate with one or a few additional pairs of photodiode and row selection transistor, such as second photodiode 122 , second row selection transistor 124 , third photodiode 126 , third row selection transistor 128 , fourth photodiode 130 , and fourth row selection transistor 132 . The circuitry of FIG. 1 is called a tiling unit because an image sensor array often has many similar units laid out in the array in a manner resembling tiles on a floor, although these units may be found upright as well as in orientations mirrored about one or more axes. Such an array is typically surrounded by row and column decoders, sense amplifiers, and other circuitry for controlling the array and for scanning captured images out of the array.

In an embodiment, most N-channel transistors, including row selection transistors 102 , 124 , 128 , 132 , reset transistor 106 , and readout row selection transistor 116 , are N-channel transistors as known in the prior art having low threshold voltages, and some of these are fabricated with N-doped polysilicon gate structures 208 , over thin gate oxide 210 , and N-doped source and drain 206 , located in a lightly-doped P-type well 204 , on substrate 202 , as shown in FIG. 2 .

The tiling unit 100 of FIG. 1 , however, uses a modified N-channel transistor for source-follower transistor 114 only. The modified N-channel transistor has a higher threshold voltage, and is fabricated with P-doped polysilicon gate structures 258 , over thin gate oxide 260 , an N-doped source and drain 256 , located in a lightly-doped P-type well 204 , on substrate 202 , as shown in FIG. 2 . While P-poly N-channel transistors are known, they have not previously been combined with conventional N-poly N-channel transistors in a tiling unit of a photosensor array integrated circuit.

It has been found that the higher threshold of the modified N-channel source-follower transistor lowers the output voltage of source-follower 114 , thereby increasing the source-to-drain voltage of source-follower 114 . In turn, this improves power supply rejection ratio of the source follower, and reduces noise at the column sense line 118 over a similar tiling unit having a conventional source-follower stage.

In operation, each photodiode in the tiling unit of the photodiode array image sensor is read by passing charge remaining after exposure to light from the photodiode, such as photodiode 104 , through a pass device, such as pass device 102 , to the source follower device 114 of the tiling unit, and as heretofore described the pass device is a silicon device having a same polarity channel as dopant in a gate of the pass device; in most cases both source and gate will have a primary dopant of arsenic for N-channel devices, although in alternative processes the primary dopant for a gate of an N-channel device is phosphorous while the source and drain are doped with arsenic. Signal as passed by the pass device is then buffered in the source-follower device 114 , the source follower device having an opposite polarity channel as dopant in a gate of the source follower; in most cases the source and drain of the source-follower have a primary dopant of arsenic, while the gate has a primary dopant of boron.

While the device as described has N-channel devices with conventional N-doped, and unconventional P-doped gates, the device can be built in complementary form. In complementary form, devices described above as N-channel with N-doped gates are replaced with P-channel devices with P-doped gates, and those that are described as N-channel with P-doped gates replaced with P-channel devices with N-doped gates; the P-channel devices in most instances will be doped with Boron.

While the invention has been particularly shown and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that various other changes in the form and details may be made without departing from the spirit and scope of the invention. It is to be understood that various changes may be made in adapting the invention to different embodiments without departing from the broader inventive concepts disclosed herein and comprehended by the claims that follow.