Dual-port positive level sensitive preset data retention latch

This application claims priority from Provisional Application No. 61/867,741, filed Aug. 20, 2013, currently pending.

Several trends presently exist in the semiconductor and electronics industry. Devices are continually being made smaller, faster and requiring less power. One reason for these trends is that more personal devices are being fabricated that are relatively small and portable, thereby relying on a battery as theft primary supply. For example, cellular phones, personal computing devices, and personal sound systems are devices that are in great demand in the consumer market. It is also important that data on these devices be retained even when no power is supplied to the electronic device. Non-volatile memory circuits and non-volatile logic circuits are often used to meet these requirements.

Non-volatile logic implementation often requires updating sequential elements, such as latches, from a source external to the sequential element, such as a non-volatile memory. When non-volatile logic circuits are implemented to allow the updating of sequential elements, it is desired that the implementation of the non-volatile logic circuit does not significantly slow the operation of a sequential element.

FIG. 1 is a block diagram of a dual-port positive level sensitive preset data retention latch according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a clocked inverter according to an embodiment of the invention.

FIG. 3 is a schematic diagram of a dual-port latch according to an embodiment of the invention.

FIG. 4 is a schematic diagram of a tri-state inverter. (Prior Art)

FIG. 5 is a schematic diagram of a clocked inverter according to an embodiment of the invention.

FIG. 6 is a schematic diagram of a tri-state inverter. (Prior Art)

FIG. 7 is a timing diagram showing signals SS, RET, PRE, D 1 , CKT, QN and the output of the latch Q according to an embodiment of the invention.

FIG. 8 is a timing diagram showing signals RET, CKT, PRE, D 2 , SS, SX, QN, and Q according to an embodiment of the invention.

FIG. 9 is a timing diagram showing signals RET, PRE, D 2 , SS, SX, QN, and Q according to an embodiment of the invention.

In an embodiment of the invention a dual-port positive level sensitive preset data retention latch 100 contains a clocked inverter 102 , an inverter 110 , a dual-port latch 108 and a logic circuit 112 used to create internal clocks CLKZ and CKT from an external clock CLK. The clocked inverter 102 is configured to receive a first data bit D 1 , a preset control signal PRE and internal clock signals CLKZ and CKT. The dual-port latch 108 is configured to receive the output QN from the clocked inverter 102 , data input D 2 , clock signals CLKZ and CKT, the retain control signals RET and RETN, the preset control signal PRE and control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output QN of the clocked inverter 102 , the second data bit D 2 , or a logic one is latched in the dual-port latch 108 .

Non-volatile logic implementations often require updating sequential elements (e.g. latches) from an external source (e.g. non-volatile memory). In an embodiment of the invention, the dual-port latch includes 108 a second data input (port) D 2 . The second data input D 2 is used to insert data from an external source. A tri-state inverter is added to the dual-port latch 108 to accommodate the second data input. This will be explained in more detail later in the specification. When external data needs to be inserted into the dual-port latch, the tri-state inverter is enabled. During this time, the latch feedback is disabled by causing a forward inverter to be tri-stated with the opposite control signal as the former tri-state inverter.

The circuitry used to add the second input to the dual-port latch 108 is not part of the critical timing path of the dual-port positive level sensitive preset data retention latch 100 . As a result, change to the regular performance of the dual-port positive level sensitive preset data retention latch 100 is negligible.

FIG. 1 is a block diagram of a dual-port positive level sensitive preset data retention latch 100 according to an embodiment of the invention. In a functional (i.e. normal) mode of operation, the retention mode signal RET is held at a logical low level, the retention mode signal RETN is held at a logical high level, the preset control signal PRE is held at a logical low level, the control signal SS is held at a logical low level and the binary compliment signal SSN of the control signal SS is held at a logical high level. Power is needed for functional mode operation so power supply VDD 1 and power supply VDD 2 are applied to the dual-port positive level sensitive preset data retention latch 100 .

FIG. 7 is a timing diagram showing data bit D 1 , clock signals CKT and CLKZ and the output Q of the dual-port positive level sensitive preset data retention latch 100 during the functional mode of operation. Because the RETN is held at a logical high level and PRE is held at a logical low value, the binary logical compliment of D 1 is passed to the node QN when clock signal CKT transitions from a low to high logical value. FIG. 2 illustrates an embodiment of a clocked inverter 102 . QN is then presented to an input of the dual-port latch 108 and the inverter 110 . The output of inverter 110 drives the signal Q.

FIG. 3 is a schematic diagram of a dual-port latch 108 according to an embodiment of the invention. The dual-port latch 108 includes a first tri-state inverter 302 (see FIG. 4 for an embodiment of the first tri-state inverter 302 ) with tri-state controls SS and SSN, a clocked inverter 304 (see FIG. 5 for an embodiment of the clocked inverter 304 ) with controls RET, RETN and PRE and a second tri-state inverter 306 (see FIG. 6 for an embodiment of the second tri-state inverter 306 ) with tri-state controls SS and SSN.

When the dual-port positive level sensitive preset data retention latch 100 is operating in the functional mode and the clock signal CKT is at a high logic level (logic one), the tri-state inverter 302 is active and drives node SX of the dual-port latch 108 to the complimentary logical value of QN. When the clock signal CKT transitions from a high logical level to a low logical level, the logical level on the QN is latched by the clocked inverter 304 . In this embodiment of the invention, an inverter 110 is used to buffer QN. However, non-inverting buffers may be used as well. The tri-state inverter 306 is tri-stated in this mode because SS is a logical low level and SSN is a logical high level. As a result, D 2 is not transferred to node SX.

However, during another functional mode of operation, data D 2 may be written directly to the dual-port latch 108 (See FIG. 8 ). During this functional mode, the clock signal CKT is held at a low logical level, CLKZ is held at a high logical level, control signal PRE is held at a logical low level, control signal RET is held inactive (i.e. logic zero) and control signal RETN is held inactive (i.e. logic one) with control signal SS held at a logical high level and control signal SSN held at logical low level. All other inputs to the dual-port latch 108 are don't-cares.

When control signal SS is held at a logical high level and control signal SSN is held at logical low level, tri-state inverter 306 is able to drive the complimentary value of D 2 onto node SX of the dual-port latch 108 . Because CKT, PRE and RET are held at logical low levels and CLKZ is held at logical high level, the clocked inverter 304 is active and drives node QN to the logical value of D 2 . The inverter 110 then inverts the logical value on node QN to its compliment. In this example, the compliment of D 2 is presented on node Q. Data signal D 2 must be held for the period t 3 to insure that the correct value of D 2 is latched. Also, control signal SS must remain at logical high value for time t 2 to insure that the correct value D 2 is latched.

When control signal SS is driven from a logical high level to a logical low level and SSN is driven from a logical low level to a logical high level, the tri-state inverter 306 is tri-stated and tri-state inverter 302 becomes active latching the logical value on node QN of the dual-port latch 108 .

The dual-port positive level sensitive latch 100 can also be operated to retain data (RET mode) in the dual-port latch 108 (power supply VDD 2 is active) when clocked inverter 102 , logic circuit 112 and inverter 110 are powered off (i.e. power supply VDD 1 is inactivated). Because the dual-port positive level sensitive latch 100 is being operated in the RET mode, the retention mode signal RET is held at a logical high level, the retention mode signal RETN is held at a logical low level and the control signal PRE is held at logical low level. Because power is not supplied to clocked inverter 102 , QN is not actively driven by clocked inverter 102 . In this manner, the data being retained in the dual-port latch 108 will not be inadvertently corrupted by the indeterminate output value of the clocked inverter 102 (the input is indeterminate as the supply VDD 1 is inactive or floating).

During retention mode of operation, data D 2 may be written directly to the dual-port latch 108 . During this retention mode, the control signal SS is driven to a logical high level following RET being driven to a logical high value (see FIG. 9 ). The clock signals CKT and CLKZ and the preset signal PRE are don't cares in this mode of operation in this embodiment. Before time t 1 , D 2 does not have to be driven to a logical level (i.e. D 2 may be a logical one, a logical zero, floating or tri-stated). D 2 must be driven to a logical one or a logical zero some time t 1 before the control signal SS transitions from a logical zero to a logical one. D 2 must be stable for time t 4 before the control signal SS transitions from a logical one to a logical zero and remain stable for time t 3 afterwards in order to ensure D 2 will be correctly latched.

Because the control signal SS is driven to a logical high level following RET being driving to a logical high value, the tri-state inverter 302 is tri-stated and does not drive node SX of the dual-port latch 108 . Because the control signal SS is driven to a logical high and control signal SSN is driven to a logical low value, the tri-state inverter 506 is active and drives node SX to the complimentary value presented on D 2 . Because RET is a logical high value, the clocked inverter 304 is active and drives node QN. When the control signal SS returns to a logic low level and SSN returns to a logic high level, the value stored on node QN is latched between tri-state inverter 302 and clocked inverter 304 while tri-state inverter 306 is tri-stated. Data signal D 2 must be held for the period t 3 to insure that the correct value of D 2 is latched. Also, control signal SS must remain at logical high value for time (t 2 +t 4 ) to insure that the correct value D 2 is latched. Under this condition, the data written from D 2 remains latched in the dual-port latch 108 during retention mode.

When an embodiment of the invention is asynchronously (i.e. the active preset signal PRE can be issued at any time irrespective of the logical value of the clock signals CKT and CLKZ) preset during functional mode (i.e. RET remains a logical zero), the dual-port latch 108 shown in FIG. 1 may be preset to a logical zero on its output QN by driving PRE to a logical one. The clocked inverter 102 will not “fight” QN being driven to a logical low value because the pull-up leg is disconnected from VDD 1 .

The foregoing description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiments were chosen and described in order to best explain the applicable principles and their practical application to thereby enable others skilled in the art to best utilize various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments except insofar as limited by the prior art.