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Inventor

Sudhanshu Khanna

Inventor
Richardson, TX, US

Overview

39→
Patents
2014–2020
Patent span
Physics
Primary field (CPC G)

Patents· 39 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary
H03KPulse technique34%
G11CStatic stores20%
G06FElectric digital data processing16%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use13%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications9%
G01RMeasuring electric variables2%
B06BMethods or apparatus for generating or transmitting mechanical vibrations of infrasonic, sonic, or ultrasonic frequency, e.g. for performing mechanical work in general1%
G01HMeasurement of mechanical vibrations or ultrasonic, sonic or infrasonic waves1%
G08CTransmission systems for measured values, control or similar signals1%
H01LSemiconductor devices1%
PatentTitleYear
10,873,020Piezoelectric sensing apparatus and method202010,796,738Priority based backup in nonvolatile logic arrays202010,545,728Non-volatile counter system, counter circuit and power management circuit with isolated dynamic boosted supply202010,541,012Nonvolatile logic array based computing over inconsistent power supply202010,468,079Processing device with nonvolatile logic array backup201910,452,594Nonvolatile logic memory for computing module reconfiguration201910,331,203Compute through power loss hardware approach for processing device having nonvolatile logic memory201910,102,889Processing device with nonvolatile logic array backup20189,899,066'Priority based backup in nonvolatile logic arrays'20189,830,964Non-volatile array wakeup and backup sequencing control20179,715,911'Nonvolatile backup of a machine state when a power supply drops below a threshhold'20179,711,196'Configuration bit sequencing control of nonvolatile domain and array wakeup and backup'20179,520,863'Dual-port negative level sensitive preset data retention latch'20169,520,862'Dual-port negative level sensitive reset preset data retention latch'20169,454,437'Non-volatile logic based processing device'20169,342,259'Nonvolatile logic array and power domain segmentation in processing device'20169,335,954'Customizable backup and restore from nonvolatile logic array'20169,270,257'Dual-port positive level sensitive reset data retention latch'20169,160,314'Negative edge flip-flop with dual-port slave latch'20159,099,998'Positive edge preset reset flip-flop with dual-port slave latch'20159,088,271'Dual-port positive level sensitive data retention latch'20159,083,328'Positive edge flip-flop with dual-port slave latch'20159,058,126'Nonvolatile logic array with retention flip flops to reduce switching power during wakeup'20159,018,976'Dual-port positive level sensitive reset preset data retention latch'20159,013,217'Dual-port negative level sensitive data retention latch'20159,013,218'Dual-port negative level sensitive reset data retention latch'20159,007,111'Negative edge reset flip-flop with dual-port slave latch'20159,007,091'Dual-port positive level sensitive preset data retention latch'20158,897,088'Nonvolatile logic array with built-in test result signal'20148,854,858'Signal level conversion in nonvolatile bitcell array'20148,854,079'Error detection in nonvolatile logic arrays using parity'20148,836,398'Negative edge flip-flop with dual-port slave latch'20148,836,400'Positive edge preset flip-flop with dual-port slave latch'20148,836,399'Positive edge flip-flop with dual-port slave latch'20148,829,963'Negative edge preset reset flip-flop with dual-port slave latch'20148,817,520'Two capacitor self-referencing nonvolatile bitcell'20148,803,582'Positive edge reset flip-flop with dual-port slave latch'20148,797,783'Four capacitor nonvolatile bit cell'20148,792,288'Nonvolatile logic array with built-in test drivers'2014

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2014–2020Patents assigned to TEXAS INSTRUMENTS INC (39)· patent assignee history
2014–2020Based in Richardson, TX, US· patent location history
2016Patents assigned to TEXAS INSTRUMENTS DEUTSCHLAND (1)· patent assignee history
2019–2020Based in Plano, TX, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TEXAS INSTRUMENTS INC392014–2020
TEXAS INSTRUMENTS DEUTSCHLAND12016
Locations
LocationPatentsSpan
Richardson, Texas, US352014–2020
Plano, Texas, US42019–2020