Semiconductor device having identification information generating function and identification information generation method for semiconductor device

The disclosure of Japanese Patent Application No. 2012-122080 filed on May 29, 2012 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

1. Field of the Invention

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an identification information generation circuit that generates identification information (ID) specific to a chip and an identification information generation method for a semiconductor device.

2. Description of the Background Art

As a countermeasure against imitation semiconductor devices and frauds in electronic commerce service over the Internet, specific identification information is assigned to each semiconductor chip. For example, a system is known in which, in a manufacturing process of a semiconductor chip, different data per semiconductor chip is written into a fuse or a nonvolatile memory. Another system is known in which random data held by a SRAM cell after power-on is utilized as a “fingerprint” of a semiconductor chip.

Japanese Patent Laying-Open No. 2002-278934 discloses an invention of a security protection system for a handy terminal. The handy terminal generates device identification information based on positional information on a defective block held by a built-in NAND chip.

Japanese Patent Laying-Open No. 2001-101083 discloses an invention in which a defective address of a semiconductor memory is used as a key. A server device holding contents receives a key transmitted from a client device and transmits the contents with the key inserted therein to the client device. H. Fujiwara, M. Yabuuchi, H. Nakano, H. Kawai, K. Nii, and K. Arimoto, “A Chip-ID Generating Circuit for Dependable LSI using Random Address Errors on Embedded SRAM and On-Chip Memory BIST”, 2011 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 15-17, 2011, pp. 76-77 (Non-Patent Document 1) discloses a configuration in which chip ID of LSI (semiconductor integrated circuit) is generated based on a defective cell address of an embedded SRAM and an I/O bit position to which the defective cell belongs.

Y. Su, J. Holleman, B. Otis, “A 1.6 pJ/bit 96% Stable Chip-ID Generating Circuit using Process Variations”, 2007 IEEE International Solid-State Circuits Conference, pp. 406-407 and p. 611 (Non-Patent Document 2) discloses a configuration in which an original identification number (ID) is generated for each f chip using a latch circuit in which NOR logic gates are cross coupled.

In Non-Patent Document 2, an exclusive latch circuit for generating an original identification number for each chip is provided on a chip. In order to generate an identification number having a sufficient bit length, it is necessary to provide a plurality of latch circuits accordingly, thus resulting in a problem of increased chip area.

A semiconductor device of an aspect includes an identification information generation circuit including a power supply control circuit having a first input node to which a first control signal is applied, a first power supply voltage output node and a second power supply voltage output node, and a memory array having a bit line pair, a word line, a memory cell connected to the bit line pair and the word line, a first cell power line connected to the memory cell, and a second cell power line connected to the memory cell. The first cell power line and the second cell power line are connected to the first power supply voltage output node and the second power supply voltage output node, respectively. The memory cell has a first conductivity type MOS transistor and a second conductivity type MOS transistor. The power supply control circuit is configured to output a first supply voltage and a second supply voltage to the first power supply voltage output node and the second power supply voltage output node, respectively, when the first control signal is in a first state, and output an intermediate voltage to the first power supply voltage output node and the second power supply voltage output node when the first control signal is in a second state.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 is a circuit diagram of an identification information generation circuit included in a semiconductor device according to first embodiment.

FIG. 2 is a circuit diagram of an intermediate voltage generation circuit according to the first embodiment.

FIG. 3 is a circuit diagram of an amplifier circuit constituting the intermediate voltage generation circuit according to the first embodiment.

FIG. 4 is a circuit diagram of a memory cell according to the first embodiment.

FIG. 5 is a detailed circuit diagram of a power supply control circuit and a memory array according to the first embodiment.

FIG. 6 is an operation timing chart of the power supply control circuit according to the first embodiment.

FIG. 7 is an operation timing chart of the identification information generation circuit included in the semiconductor device according to the first embodiment.

FIG. 8 is a circuit diagram of a power supply control circuit according to a first modification of the first embodiment.

FIG. 9 is an operation timing chart of the power supply control circuit according to the first modification of the first embodiment.

FIG. 10 is a circuit diagram of a power supply control circuit according to a second modification of the first embodiment.

FIG. 11 is an operation timing chart of the power supply control circuit according to the second modification of the first embodiment.

FIG. 12 is a circuit diagram of an identification information generation circuit included in a semiconductor device according to a second embodiment.

FIG. 13 is a circuit diagram of a power supply control circuit according to the second embodiment.

FIG. 14 is an operation timing chart of the power supply control circuit according to the second embodiment.

FIG. 15 illustrates a data pattern of chip-specific identification information generated by the identification information generation circuit according to the second embodiment.

FIG. 16 is a circuit diagram of an identification information generation circuit included in a semiconductor device according to a third embodiment.

FIG. 17 is a detailed circuit diagram of a power supply control circuit and a memory array according to the third embodiment.

FIG. 18 is an operation timing chart of the power supply control circuit according to the third embodiment.

FIG. 19 is an operation timing chart of a memory cell according to the third embodiment.

FIG. 20 is a circuit diagram of an identification information generation circuit included in a semiconductor device according to a fourth embodiment.

FIG. 21 is a circuit diagram of a memory array according to the fourth embodiment.

FIG. 22 is an operation timing chart of a power supply control circuit and the memory array according to the fourth embodiment.

The embodiments of the present invention will be described below with reference to the drawings. When the number, an amount or the like is mentioned in the embodiments described below, the scope of the present invention is not necessarily limited to that number, that amount or the like, unless otherwise specified. In the drawings, the same or corresponding portions shall have the same reference characters or reference numbers allotted. Moreover, in the description of the embodiments, repeated description of portions allotted the same reference characters and the like may not be given.

[First Embodiment]

Referring to FIG. 1 , a configuration of an identification information generation circuit 100 _ 1 included in a semiconductor device according to a first embodiment of the present invention will be described.

The semiconductor device (not shown) includes identification information generation circuit 100 _ 1 . The semiconductor device is implemented by a system LSI (Large Scale Integration), such as a microcomputer or SoC (System-on-a-Chip), for example.

Identification information generation circuit 100 _ 1 has an authentication control circuit 101 , a BIST (Built-in-Self-Test) control circuit 102 , an intermediate voltage generation circuit 110 , a power supply control circuit 140 _ 1 , memory macros 150 to 180 , and an internal bus I-Bus connected to memory macros 150 to 180 .

Authentication control circuit 101 generates an authentication control signal CTLv having a binary value in response to an authentication request signal Arq input to the semiconductor device. Intermediate voltage generation circuit 110 generates an intermediate voltage between a supply voltage Vdd applied to power supply control circuit 140 _ 1 and a supply voltage Vss which is lower than Vdd. Supply voltage Vss is a so-called ground voltage, and is usually 0 V. The intermediate voltage refers to a value lower than supply voltage Vdd and higher than supply voltage Vss. As a suitable example, the intermediate voltage in this embodiment is set at a value obtained by dividing the difference between supply voltages Vdd and Vss by 2. Therefore, the intermediate voltage will be denoted by “Vdd/2” for the sake of convenience.

Power supply control circuit 140 _ 1 has an input node Nc 1 and an intermediate voltage input node Nd. Authentication control signal CTLv is applied to input node Nc 1 , and intermediate voltage Vdd/2 is applied to intermediate voltage input node Nd. Power supply control circuit 140 _ 1 further has power supply voltage output nodes Nn and Np.

When authentication control signal CTLv is at the low level, supply voltages Vss and Vdd are output to power supply voltage output nodes Nn and Np, respectively. When authentication control signal CTLv is at the high level, intermediate voltage Vdd/2 is output to both power supply voltage output nodes Nn and Np.

Each of memory macros 150 to 180 has a memory array 151 , a data output circuit 152 and a peripheral circuit 153 . Cell power lines Vssn and Vddp are connected to memory array 151 arranged in each memory macro.

Peripheral circuit 153 selects one of a plurality of memory cells (which will be described later in detail) included in memory array 151 . Data output circuit 152 outputs data on the memory cell selected by peripheral circuit 153 as output data Dout.

Selection of a memory cell by peripheral circuit 153 is performed based on a read signal Rd and an address signal Add output from authentication control circuit 101 . Each memory macro is connected to internal bus I-Bus.

BIST control circuit 102 stores output data Dout from memory macros 150 to 180 . Upon receipt of a request signal RQ from authentication control circuit 101 , BIST control circuit 102 returns output data Dout as memory data MD. Authentication control circuit 101 outputs chip-specific identification information Chip_id as specific identification information on the semiconductor device based on this memory data MD.

Referring to FIG. 2 , a circuit diagram of intermediate voltage generation circuit 110 will be described.

Intermediate voltage generation circuit 110 is a typical band gap reference circuit, to which supply voltages Vdd and Vss are applied. Between the output terminal of an amplifier circuit 111 and supply voltage Vss, resistors R 1 , R 2 and a diode D 1 are connected in series in this order. A node N 1 between resistors R 1 and R 2 is connected to the inverting input terminal of amplifier circuit 111 . Between the output terminal of amplifier circuit 111 and supply voltage Vss, a resistor R 3 and a diode D 2 are connected in series in this order in parallel with the aforementioned circuit. A node N 2 between resistor R 3 and the anode of diode D 2 is connected to the non-inverting input terminal of amplifier circuit 111 .

Referring to FIG. 3 , a specific circuit configuration of amplifier circuit 111 will be described.

Amplifier circuit 111 is a current mirror type differential amplifier circuit. A p-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) M 1 is a constant current source that operates in a saturation region. Supply voltage Vdd is applied to its source, and supply voltage Vss is applied to its gate. Hereinafter, the “p-type MOS transistor” will be referred to as a “p-type transistor.” An n-type MOSFET will be similarly referred to as an n-type transistor. Both the transistors may also be simply referred to as MOS transistors.

A p-type transistor M 2 has its source connected to the drain of a p-type transistor M 1 and its gate serving as inverting input terminal N 1 . A p-type transistor M 3 also has its source connected to the drain of p-type transistor M 1 and its gate serving as non-inverting input terminal N 2 . P-type transistors M 2 and M 3 have their drains connected to the drains of n-type transistors M 4 and M 5 , respectively.

Supply voltage Vss is applied to the sources of n-type transistors M 4 and M 5 , and n-type transistor M 4 has its gate and drain connected to the gate of n-type transistor M 5 in common. Therefore, n-type transistors M 4 and M 5 operate as a current mirror circuit. This current mirror circuit is a current mirror type differential amplifier circuit, and receives differential signals applied to non-inverting input terminal N 2 and inverting input terminal N 1 to output intermediate voltage Vdd/2 from a common node between the drains of p-type transistor M 3 and n-type transistor M 5 .

The value of this intermediate voltage Vdd/2 is set appropriately in intermediate voltage generation circuit 110 of FIG. 2 based on the values of resistors R 1 , R 2 and R 3 . In the present first embodiment, the value of intermediate voltage Vdd/2 shall be equal to the value obtained by dividing the difference between supply voltages Vdd and Vss by 2.

Referring to FIG. 4 , a configuration of a memory cell MC included in memory array 151 shown in FIG. 1 will be described.

Memory cell MC includes cross-coupled inverters In 0 and In 1 , an n-type transistor M 04 connected between an output node N 00 of inverter In 0 and a bit line BL, and an n-type transistor M 05 connected between an output node N 01 of inverter In 1 and a bit line /BL.

Inverter In 0 includes a p-type transistor M 00 and an n-type transistor M 02 . P-type transistor M 00 has its source connected to cell power line Vddp, and n-type transistor M 02 has its source connected to cell power line Vssn. P-type transistor M 00 and n-type transistor M 02 have their drains connected in common as output node N 00 .

Inverter In 1 includes a p-type transistor M 01 and an n-type transistor M 03 . P-type transistor M 01 has its source connected to cell power line Vddp, and n-type transistor M 03 has its source connected to cell power line Vssn. P-type transistor M 01 and n-type transistor M 03 have their drains connected in common as output node N 01 .

P-type transistor M 00 and n-type transistor M 02 constituting inverter In 0 have their gates connected in common to output node N 01 . P-type transistor M 01 and n-type transistor M 03 constituting inverter In 1 have their gates connected in common to output node N 00 .

These cross-coupled inverters In 0 and In 1 constitute a latch circuit. Output node N 00 or N 01 is held at supply voltage Vss or Vdd, and the nodes store data while maintaining a complementary relation with their output nodes. In the present specification, output nodes N 00 and N 01 will be hereinafter also referred to as storage nodes N 00 and N 01 , respectively.

N-type transistors MO 4 and M 05 have their gates connected to a word line WL. Rising of the electric potential at word line WL brings n-type transistors M 04 and M 05 into a conducting state, so that data is read out from storage nodes N 00 and N 01 to the respective bit lines, or data is written into storage nodes N 00 and N 01 from respective bit lines.

Referring to FIG. 5 , a detailed configuration of power supply control circuit 140 _ 1 and memory array 151 according to the first embodiment of the present invention will be described.

Power supply control circuit 140 _ 1 has input node Nc 1 , intermediate voltage input node Nd and power supply voltage output nodes Nn, Np. An n-type transistor Mvn 0 has its drain connected to power supply voltage output node Nn, and supply voltage Vss is applied to its source. A p-type transistor Mvp 0 has its drain connected to power supply voltage output node Np, and supply voltage Vdd is applied to its source. N-type transistor Mvn 0 and p-type transistor Mvp 0 have their drains connected through a p-type transistor Mhs.

Power supply voltage output nodes Nn and Np are connected to the drains of p-type transistors Mhd and Mhu, respectively. P-type transistors Mhd and Mhu have their sources connected in common to intermediate voltage input node Nd. P-type transistors Mhd, Mhu and Mhs have their gates connected in common, and a signal S which will be described later is applied thereto.

Authentication control signal CTLv applied to input node Nc 1 is applied to the gate of p-type transistor Mvp 0 and inverter IV 0 . Inverter IV 0 inverts the logic level of authentication control signal CTLv to output a signal /CTLv to the gate of n-type transistor Mvn 0 . Inverters IV 0 , IV 1 and IV 2 are connected sequentially to constitute a three-stage inverter, which inverts the logic level of authentication control signal CTLv to generate a signal a.

Signal a output from inverter IV 2 is input to a pulse generation circuit OSP. Pulse generation circuit OSP has a delay circuit DLY, inverter IV 3 , a NOR circuit NR 0 , and inverter IV 4 . Delay circuit DLY delays signal a by a delay time Tdly to output a signal adly. Inverter IV 3 inverts the logic level of signal adly to output a signal /adly. NOR circuit NR 0 obtains the NOR logic of signals a and /adly to output a signal /S. Inverter IV 4 inverts the logic level of signal /S to output signal S.

Memory array 151 has a multi-bit memory cells obtained by arranging memory cells MC in an array along bit lines BL and /BL or word line WL, or along both the bit lines and word line. In FIG. 5 , memory cells from a memory cell MC 00 (word address: 0, bit address: 0) to a memory cell MC 0 (n−1) (word address: 0, bit address: (n−1)) are arranged only along the bit lines. It is noted that respective memory cells MC 00 to MC 0 (n−1) will be generically called memory cell MC.

Supply voltages Vdd and Vss output from power supply control circuit 140 _ 1 are applied to memory cell MC through cell power lines Vddp and Vssn, respectively. Cell power lines Vssn and Vddp are routed to each memory cell in memory array 151 . In memory array 151 shown in FIG. 5 , a bit line pair has a configuration corresponding to 1-bit data. In a memory cell array having bit line pairs for multi-bit data along the word line, each of cell power lines Vssn and Vddp extends along word line WL to connect to each memory cell.

Parasitic capacitances of cell power lines Vssn and Vddp are referred to as a parasitic capacitance Cd and a parasitic capacitance Cu, respectively. Although not shown in FIG. 5 , cell power lines Vssn and Vddp have parasitic resistances, respectively.

Referring to FIG. 6 , the operation of power supply control circuit 140 _ 1 will be described.

As shown in FIG. 6 at (a), at time t 1 , authentication control signal CTLv is changed from the low level to the high level in response to authentication request signal Arq. P-type transistor Mvp 0 receiving authentication control signal CTLv at its gate is changed from the conducting state to the non-conducting state. Therefore, after time t 1 , supply of supply voltage Vdd to cell power line Vddp is interrupted.

As shown in FIG. 6 at (b), at time t 2 , inverter IV 0 receiving authentication control signal CTLv inverts the input signal to output an output signal /CTLv. N-type transistor Mvn 0 receiving this signal at its gate is changed from the conducting state to the non-conducting state. Therefore, after time t 2 , supply voltage Vss supplied to cell power line Vssn is interrupted.

Signal /CTLv passes through inverters IV 1 and IV 2 , and output signal a is changed from the high level to the low level at time t 3 shown in FIG. 6 at (c). As shown in FIG. 6 at (c) and (d), signal a is changed to the low level at time t 3 , and signal /adly is changed to the high level at time t 5 . During the period from time t 3 to time t 5 , there are circuit delays caused by delay circuit DLY and inverter IV 3 . NOR circuit NR 0 obtains the NOR logic of signals a and /adly, and brings signal /S into the high level during a period in which both the signals are at the low level.

As shown in FIG. 6 at (e), in a delay time Tdly from time t 4 to time t 6 , inverter IV 4 inverts input signal /S to obtain output signal S and maintains the low level. This low level period is a period obtained by shifting the above period from t 3 to time t 5 by the circuit delays caused by NOR circuit NR 0 and inverter IV 4 , and is dominantly determined by delay time Tdly caused by delay circuit DLY. This is because the delay caused by delay circuit DLY is extremely longer than the circuit delay caused by inverter IV 3 . Therefore, in the following description, the low level period of signal S will be regarded as being substantially equal to delay time Tdly produced by delay circuit DLY.

As shown in FIG. 6 at (f), when signal S is changed from the high level to the low level at time t 4 , the electric potentials at cell power lines Vssn and Vddp start rising and dropping toward intermediate voltage Vdd/2 from supply voltages Vss and Vdd, respectively. The change of signal S to the low level brings p-type transistor Mhs shown in FIG. 5 into the conducting state to short-circuit power supply voltage output nodes Nn and Np. P-type transistors Mhu and Mhd are also brought into the conducting state. As a result, intermediate voltage Vdd/2 generated by intermediate voltage generation circuit 110 is supplied to power supply voltage output nodes Nn and Np.

As shown in FIG. 6 at (a), (b) and (e), in delay time Tdly from time t 4 to time t 6 , authentication control signal CTLv and signal /CTLv are maintained at the high level and the low level, respectively, and signal S is maintained at the low level. Therefore, the electric potentials at cell power lines Vssn and Vddp are maintained at intermediate voltage Vdd/2.

After certain delay time Tdly, signal S is changed from the low level to the high level. This change occurs because signal /adly is changed to the high level at time t 5 . Accordingly, p-type transistors Mhs, Mhu and Mhd are brought into the non-conducting state. As shown in FIG. 6 at (a), (b) and (c), authentication control signal CTLv is changed from the high level to the low level at time t 7 , and signals /CTLv and a are inverted in logic level at time t 8 and time t 9 , respectively. Therefore, p-type transistor Mvp 0 and n-type transistor Mvn 0 are changed from the non-conducting state to the conducting state at time t 7 and time t 8 , respectively.

P-type transistor Mvp 0 in the conducting state raises the electric potential at cell power line Vddp from intermediate voltage Vdd/2 to supply voltage Vdd. N-type transistor Mvn 0 in the conducting state drops the electric potential at cell power line Vssn from intermediate voltage Vdd/2 to supply voltage Vss. It is noted that in FIG. 6 at (a) and (b), the time difference between time t 7 and time t 8 is a circuit delay caused by inverter IV 0 , which is shorter than the circuit delay caused by delay circuit DLY or the like. Thus, time t 7 and time t 8 can be regarded as substantially the same time.

Referring to FIG. 7 , the operation of identification information generation circuit 100 _ 1 included in the semiconductor device according to the first embodiment of the present invention will be described.

In FIGS. 7 , (a), (b), (e), and (f) correspond to (a), (b), (e), and (f) in FIG. 6 , respectively. As shown in FIG. 7 at (e), in delay time Tdly from time t 4 to time t 6 , signal S is maintained at the low level.

As shown in FIG. 7 at (f), at time t 4 , the electric potentials at cell power lines Vssn and Vddp start rising and dropping from supply voltages Vss and Vdd to intermediate voltage Vdd/2, respectively, and reach intermediate voltage Vdd/2 at time t 41 . In the period from time t 41 to time t 7 in which authentication control signal CTLv is maintained at the high level, the electric potentials at cell power lines Vssn and Vddp are maintained at intermediate voltage Vdd/2. It is noted that, as already described, time t 8 is substantially the same time as time t 7 , and is regarded as the same time in FIG. 7 .

Referring to FIG. 4 , the electric potentials at storage nodes N 00 and N 01 of memory cell MC just before time t 7 will be described. In the period from time t 4 to time t 13 , the electric potential at word line WL is set at supply voltage Vss. That is, n-type transistors M 04 and M 05 are in the non-conducting state, and storage nodes N 00 and N 01 of memory cell MC are electrically disconnected from bit lines BL and /BL, respectively.

During delay time Tdly from time t 4 to time t 6 , signal S is at the low level, and intermediate voltage Vdd/2 is applied to cell power lines Vssn and Vddp. As a result, the electric potentials at the drain, source and gate of each of four MOS transistors constituting inverters In 0 and In 1 in memory cell MC are maintained at intermediate voltage Vdd/2. The electric potentials at storage nodes N 00 and N 01 in memory cell MC also reach intermediate voltage Vdd/2.

At this time, the case in which the electric potential at storage node N 00 or N 01 becomes higher or lower than intermediate voltage Vdd/2 by a threshold voltage of any of the four MOS transistors is of concern. However, current leakage (gate leakage and subthreshold leakage) occurs in the MOS transistors, so that the electric potentials at two storage nodes N 00 and N 01 reach intermediate voltage Vdd/2.

As shown in FIG. 7 , in the period of transition time Tt from time t 7 to time t 13 , the electric potentials at cell power lines Vssn and Vddp are returned to their original potentials, supply voltages Vss and Vdd, respectively, from intermediate voltage Vdd/2.

Description of the chip-specific identification information generating function of the semiconductor device according to the first embodiment of the present invention is premised on the following relationship as an example. A threshold voltage Vth 00 of p-type transistor M 00 constituting memory cell MC is higher than a threshold voltage Vth 01 of p-type transistor M 01 , and a threshold voltage Vth 03 of n-type transistor M 03 is higher than a threshold voltage Vth 02 of n-type transistor M 02 . Furthermore, the threshold voltage of an n-type transistor shall be higher than that of a p-type transistor. That is, the following relationship shall be a precondition.

Vth01<Vth00<Vth02<Vth03

Here, the sign “<” is a sign of inequality indicating that the left part is smaller than the right part.

It is noted that this precondition is a condition for simplifying the description of the present embodiment, and is not an essential condition. The threshold voltage (Vthn) of an n-type transistor has a positive value, while the threshold voltage (Vthp) of a p-type transistor has a negative value. In the present specification and the accompanying drawings, the expression “the threshold voltage of a p-type transistor” (e.g., Vth 00 ) refers to the absolute value of the threshold voltage unless otherwise specifically stated.

In FIG. 7 at (f), at time t 7 , the electric potentials at cell power lines Vssn and Vddp are intermediate voltage Vdd/2, and drop and rise after time t 7 , respectively. On the other hand, the gate electric potentials at the four MOS transistors are maintained at intermediate voltage Vdd/2 until the gate-source voltage of these four MOS transistors exceeds any lowest threshold voltage.

Since the sources of n-type transistors (MO 2 , M 03 ) constituting memory cell MC are controlled by cell power line Vssn and the sources of p-type transistors (M 00 , M 01 ) are controlled by cell power line Vddp, the electric potential difference between the gate and source of the four MOS transistors starts increasing after time t 7 .

Suppose that the electric potential difference between the gate and source of p-type transistor M 01 reaches threshold voltage Vth 01 at time t 9 . This means that p-type transistor M 01 having the lowest threshold voltage among the four MOS transistors (M 00 , M 01 , M 02 , and M 03 ) is first brought into the conducting state.

As a result, the electric potential at storage node N 01 maintained at intermediate voltage Vdd/2 starts rising at time t 9 with the conducting state of p-type transistor M 01 . On the other hand, p-type transistor M 00 whose gate is connected to storage node N 01 is maintained in the non-conducting state because the electric potential at storage node N 01 (gate electric potential at M 00 ) rises even if the source potential (electric potential at cell power line Vddp) rises.

After time t 7 , the electric potential at cell power line Vssn also starts dropping from intermediate voltage Vdd/2. This drop in electric potential at cell power line Vssn results in an increase in the source-gate voltage of two n-type transistors (MO 2 , M 03 ).

At time t 10 , the difference between the electric potential at storage node N 01 and the electric potential at cell power line Vssn, that is, the gate-source voltage of n-type transistor M 02 reaches threshold voltage Vth 02 . At this time, the electric potential at storage node N 01 has a value exceeding intermediate voltage Vdd/2.

At time t 10 , the gate electric potential at the other n-type transistor M 03 is maintained at intermediate voltage Vdd/2. This is because p-type transistor M 00 is in the non-conducting state and the electric potential at storage node N 00 is maintained at the value shown at time t 7 .

At time t 10 , the electric potential at storage node N 00 is maintained at intermediate voltage Vdd/2, and the electric potential at storage node N 01 is a value exceeding intermediate voltage Vdd/2. Since threshold voltage Vth 02 is lower than threshold voltage Vth 03 as a precondition, n-type transistor M 02 is brought into the conducting state, and n-type transistor M 03 is maintained in the non-conducting state. As a result, the electric potential at storage node N 00 maintained at intermediate voltage Vdd/2 starts dropping at time t 10 with the conducting state of n-type transistor M 02 .

Here, even if threshold voltage Vth 02 is higher than threshold voltage Vth 03 , the electric potential difference between storage node N 00 and cell power line Vssn is smaller than the electric potential difference between storage node N 01 and cell power line Vssn. Therefore, n-type transistor M 02 is brought into the conducting state earlier than n-type transistor M 03 . The above-described operation will be established under the condition that the difference between variations in threshold voltages Vth 03 and Vth 02 is smaller than at least threshold voltage Vth 01 .

In addition, a variation in threshold voltage of an n-type transistor will not become higher than the threshold voltage of a p-type transistor. Furthermore, also when an n-type transistor among the four MOS transistors has the minimum threshold voltage, the operation is achieved similarly to the above description, and data stored in a memory cell appears.

At time t 11 , the electric potential at storage node N 01 and the electric potential at cell power line Vddp become equal, and after time tll, the electric potentials at storage node N 01 and cell power line Vddp transition to be equal. At time t 13 , the electric potential at storage node N 01 reaches supply voltage Vdd.

Similarly, at time t 12 , the electric potential at storage node N 00 and the electric potential at cell power line Vssn become equal, and after time t 12 , storage node N 00 and cell power line Vssn transition to be equal. At time t 13 , the electric potential at storage node N 00 reaches supply voltage Vss.

After time t 13 , supply voltages Vss and Vdd are applied to cell power lines Vssn and Vddp, respectively. Data (electric potential information) at storage nodes N 00 and N 01 held by each memory cell MC constituting memory array 151 is selected by word line WL and output to bit lines BL and /BL. As shown in FIG. 1 , data output circuit 152 outputs data in each memory cell MC as output data Dout to BIST control circuit 102 based on the data in bit lines BL and /BL.

In response to request signal RQ from authentication control circuit 101 , BIST control circuit 102 returns the data in each memory cell MC to authentication control circuit 101 as memory data MD. Authentication control circuit 101 outputs this memory data MD as chip-specific identification information Chip_id.

As the above description indicates, power supply control circuit 140 _ 1 sets the electric potentials at the source, drain and gate of each of the four MOS transistors in the latch circuit constituting memory cell MC at intermediate voltage Vdd/2 until a predetermined time set by delay time Tdly elapses. Then, power supply control circuit 140 _ 1 raises the electric potentials at the sources of the p-type transistors of inverters In 0 and In 1 from intermediate voltage Vdd/2 to supply voltage Vdd.

Similarly, power supply control circuit 140 _ 1 drops the electric potentials at the sources of the n-type transistors of inverters In 0 and In 1 from intermediate voltage Vdd/2 to supply voltage Vss.

As a result, storage node N 00 or N 01 connected to the drain of a MOS transistor having the minimum threshold voltage among the four MOS transistors is connected to the source of that MOS transistor. For example, when the threshold voltage of p-type transistor M 01 included in inverter In 1 is the minimum, the electric potential at storage node N 01 starts rising from intermediate voltage Vdd/2 toward supply voltage Vdd.

Among the four MOS transistors in the latch circuit constituting a memory cell, when a MOS transistor (e.g., p-type) having the minimum threshold voltage is brought into the conducting state, another MOS transistor of the other conductivity type (e.g., n-type) of an inverter paired with an inverter to which the MOS transistor having the minimum threshold voltage belongs starts conduction.

The electric potentials at storage nodes N 00 and N 01 which are the drains of these transistors having started conduction become the electric potentials at the respective sources. Therefore, data generated in memory cell MC is determined by the variations in the threshold voltages of the MOS transistors in inverters In 0 and In 1 constituting the memory cell. Since these threshold voltages vary at random, data appearing in the memory cell is random data. Furthermore, since this data is determined by the threshold voltages of the four MOS transistors constituting the two inverters in the memory cell, reproducibility of generating identical data when the operation is performed again is high.

[First Modification of First Embodiment]

Referring to FIG. 8 , a circuit block configuration of a power supply control circuit 140 _ 11 according to a first modification of the first embodiment of the present invention will be described.

Power supply control circuit 140 _ 11 has a configuration in which a delay control circuit DLn is added to power supply control circuit 140 _ 1 according to the first embodiment shown in FIG. 5 . In power supply control circuit 140 _ 11 , functional blocks, transistors, signal lines and the like denoted by the same reference characters as those shown in FIG. 5 are identical in function and configuration to those of power supply control circuit 140 _ 1 , and description thereof will not be repeated.

In this modification, as an operation for generating random data in a memory cell, a time difference is provided between the timing at which the electric potential at cell power line Vddp rises from intermediate voltage Vdd/2 to supply voltage Vdd and the timing at which the electric potential at cell power line Vssn drops from intermediate voltage Vdd/2 to supply voltage Vss. Accordingly, the factor that determines data appearing in storage nodes N 00 and N 01 depends only on the difference between the threshold voltages of two p-type transistors, which further increases reproducibility of data appearance.

Delay control circuit DLn includes a delay circuit DLY 1 and a NOR circuit NR 1 . Delay circuit DLY 1 delays authentication control signal CTLv applied to input node Nc 1 by delay time Tdly 1 to output a signal CLdly 1 . NOR circuit NR 1 obtains the NOR logic of authentication control signal CTLv and signal CLdly 1 , and outputs the result as a signal CLn.

Memory array 151 has the same configuration as memory array 151 shown in FIG. 5 . Memory cell MC included in memory array 151 has the same configuration as memory cell MC shown in FIG. 4 , and only inverters In 0 and In 1 in memory cell MC are shown in FIG. 8 .

FIG. 9 shows schematic operation waves of power supply control circuit 140 _ 11 according to the first modification of the first embodiment shown in FIG. 8 . Referring to FIG. 9 , the operation of power supply control circuit 1 z 40 _ 11 will be described.

As shown in FIG. 9 at (a), authentication control signal CTLv is changed from the low level to the high level at time t 1 in response to authentication request signal Arq. P-type transistor Mvp 0 receiving this authentication control signal CTLv at its gate interrupts supply voltage Vdd supplied to power supply voltage output node Np.

As shown in FIG. 9 at (a) and (b), authentication control signal CTLv is changed from the low level to the high level at time t 1 , and output signal CLn of NOR circuit NR 1 is changed from the high level to the low level. At this time, the delay from time t 1 to time t 2 is the circuit delay caused by NOR circuit NR 1 . With this change in signal CLn, n-type transistor Mvn 0 interrupts supply of supply voltage Vss to power supply voltage output node Nn.

When authentication control signal CTLv is changed from the low level to the high level at time t 1 , pulse generation circuit OSP changes signal S, having been at the high level similarly to FIG. 5 , to the low level and maintains the low level in the period of delay time Tdly from time t 3 to time t 5 .

As shown in FIG. 9 at (d), at time t 3 , the electric potential at cell power line Vssn starts rising from supply voltage Vss, and reaches intermediate voltage Vdd/2 at time t 4 . Similarly, at time t 3 , the electric potential at cell power line Vddp starts dropping from supply voltage Vdd, and reaches intermediate voltage Vdd/2 at time t 4 . The electric potentials at cell power lines Vssn and Vddp reach intermediate voltage Vdd/2 simultaneously at time t 4 in this figure. Actually, however, they do not necessarily reach Vdd/2 simultaneously, and the electric potentials at both the cell power lines should only reach intermediate voltage Vdd/2 by time t 6 at which the next operation is started.

At time t 6 , authentication control signal CTLv is changed from the high level to the low level, and p-type transistor Mvp 0 receiving authentication control signal CTLv at its gate starts supply of supply voltage Vdd to power supply voltage output node Np. Therefore, the electric potentials at the sources of p-type transistors M 00 and M 01 of memory cell MC rise from intermediate voltage Vdd/2 toward supply voltage Vdd. On the other hand, when signal CLn is changed from the low level to the high level at time t 8 , the electric potential at cell power line Vssn having been maintained at intermediate voltage Vdd/2 starts dropping.

The above-described changes in the electric potential at cell power line Vssn will be described below. Attention is focused on delay control circuit DLn shown in FIG. 8 . As shown in FIG. 9 at (a) and (b), authentication control signal CTLv is changed from the high level to the low level at time t 6 . NOR circuit NR 1 maintains output signal CLn at the low level until both authentication control signal CTLv and delay signal CLdly 1 are changed to the low level. When authentication control signal CTLv is changed from the high level to the low level at time t 6 , delay signal CLdly 1 is maintained at the high level until time t 8 at which delay time Tdly 1 elapses. Therefore, n-type transistor Mvn 0 receiving output signal CLn at its gate is maintained in the non-conducting state.

At time t 8 at which delay time Tdly 1 elapses from time t 6 , delay signal CLdly 1 is changed from the high level to the low level. As a result, output signal CLn of NOR circuit NR 1 is changed from the low level to the high level, and n-type transistor Mvn 0 is brought into the conducting state. The electric potential at cell power line Vssn starts dropping from intermediate voltage Vdd/2 to the electric potential at supply voltage Vss through n-type transistor Mvn 0 .

In FIG. 9 at (d), the changes in electric potentials at storage nodes N 00 and N 01 of the memory cell after time t 6 will be described with reference to the circuit diagram of inverters In 0 and In 1 of FIG. 8 . Here, for ease of description, it is assumed that threshold voltage Vth 01 of p-type transistor M 01 of inverter In 1 is lower than threshold voltage Vth 00 of p-type transistor M 00 of inverter In 0 . It is noted that the electric potentials at the source, drain and gate of each of the four transistors constituting inverters In 0 and In 1 at time t 6 are all intermediate voltage Vdd/2.

Upon receipt of the electric potential at cell power line Vddp starting rising at time t 6 and Vdd/2 at which storage node N 00 is maintained, the electric potential difference between the source and gate of p-type transistor M 01 reaches threshold voltage Vth 01 of p-type transistor M 01 at time t 7 . This is because p-type transistor M 01 reaches the threshold voltage earlier than p-type transistor M 00 based on the aforementioned assumption, Vth 01 <Vth 00 . Therefore, p-type transistor M 01 is brought into the conducting state, and the electric potential at storage node N 01 starts rising at time t 7 . At time t 9 at which a transition time Ttp elapses from time t 6 , the electric potential at storage node N 01 reaches supply voltage Vdd.

When signal CLn is changed from the low level to the high level at time t 8 , n-type transistor Mvn 0 is brought into the conducting state, and supply of supply voltage Vss to power supply voltage output node Nn is started. As a result, the electric potential at the sources of n-type transistors M 02 and M 03 starts dropping from intermediate voltage Vdd/2 toward supply voltage Vss.

At time t 8 , the gate electric potential at n-type transistor M 03 equal to the electric potential at storage node N 00 is maintained at intermediate voltage Vdd/2, while the gate electric potential at n-type transistor M 02 which is equal to the electric potential at storage node N 01 is higher than intermediate voltage Vdd/2. For this reason, when p-type transistor M 01 is brought into the conducting state earlier, n-type transistor M 02 in inverter In 0 paired with and opposite to inverter In 1 is brought into the conducting state. At time t 10 at which a transition time Ttn elapses from time t 8 , the electric potential at storage node N 00 reaches supply voltage Vss.

The influence of n-type transistor M 03 in inverter In 1 on the changes in electric potentials at storage nodes N 00 and N 01 after time t 8 will be considered. Threshold voltages of n-type transistors M 02 and M 03 are denoted by Vth 02 and Vth 03 , respectively. Even if these threshold voltages vary and Vth 02 >Vth 03 or Vth 02 <Vth 03 holds, n-type transistor M 02 is brought into the conducting state earlier than n-type transistor M 03 and the electric potential at storage node N 00 drops to supply voltage Vss, unless the absolute value |Vth 02 −Vth 03 | of the difference between the threshold voltages is greater than at least threshold voltage Vth 01 of p-type transistor M 01 .

N-type transistors M 02 and M 03 are devices manufactured so as to have an equal gate size and an equal property. N-type transistors M 02 and M 03 are disposed adjacent to each other. Therefore, variations in these threshold voltages caused by manufacturing variation will not become greater than the absolute value |Vth 01 | of the threshold voltage of p-type transistor M 01 .

After time t 10 , data output circuit 152 (see FIG. 1 ) outputs data in each memory cell MC to BIST control circuit 102 as output data Dout. In response to request signal RQ from authentication control circuit 101 , BIST control circuit 102 returns the data in each memory cell MC to authentication control circuit 101 as memory data MD. Authentication control circuit 101 outputs this memory data MD as chip-specific identification information Chip_id.

In power supply control circuit 140 _ 11 according to the first modification of the first embodiment, the source, drain and gate of the four MOS transistors constituting inverters In 0 and In 1 in memory cell MC are set at an equal electric potential (intermediate voltage Vdd/2). Then, the electric potential at the common source of two p-type transistors M 00 and M 01 (electric potential at cell power line Vddp) is raised. Of the two p-type transistors, one having a lower threshold voltage is brought into the conducting state. The transistor brought into the conducting state raises the electric potential at storage node N 00 or N 01 .

By the period from time t 6 at which the electric potential at cell power line Vddp starts rising to time t 8 at which delay time Tdly 1 elapses, one of the two p-type transistors (M 00 and M 01 ) is brought into the conducting state, and the electric potential at cell power line Vssn is maintained at intermediate voltage Vdd/2. After delay time Tdly 1 elapses, the electric potential at cell power line Vssn, which is also the electric potentials at the sources of n-type transistors M 02 and M 03 , is dropped.

Accordingly, random data appearing in a memory cell can be determined only by the variations in the threshold voltages of p-type transistors, and the influence of the threshold voltages of the n-type transistors can be avoided. Moreover, since the factor that determines the data appearing in a memory cell is established by the magnitude correlation between the threshold voltages of two p-type transistors M 00 and M 01 , reproducibility of the data appearing in a storage node is better than in the first embodiment.

As described above, in the description of the present variation, it is assumed that threshold voltage Vth 01 of p-type transistor M 01 is lower than threshold voltage Vth 00 of p-type transistor M 00 . This assumption is a condition for simply describing the operation of power supply control circuit 140 _ 11 according to the first modification of the first embodiment. It is easily understood that, even if threshold voltages Vth 01 and Vth 00 do not have the magnitude correlation as assumed above, data appearing in a memory cell is determined based on the magnitude correlation between the threshold voltages of the p-type transistors.

[Second Modification of First Embodiment]

Referring to FIG. 10 , a circuit block configuration of a power supply control circuit 140 _ 12 according to a second modification of the first embodiment of the present invention will be described.

Power supply control circuit 140 _ 12 has a configuration in which a delay control circuit DLp is added to power supply control circuit 140 _ 1 according to the first embodiment shown in FIG. 5 . In power supply control circuit 140 _ 12 , functional blocks, transistors, signal lines and the like denoted by the same reference characters as those shown in FIG. 5 are identical in function and configuration to those of power supply control circuit 140 _ 1 , and description thereof will not be repeated.

Delay control circuit DLp has a delay circuit DLY 2 , inverters IV 3 , IV 4 , and a NAND circuit ND 1 . Delay circuit DLY 2 delays authentication control signal CTLv applied to input node Nc 1 by a delay time Tdly 2 to output a signal CLdly 2 . Inverter IV 3 inverts the logic level of authentication control signal CTLv to output a signal/CTLvp. Inverter IV 4 inverts the logic level of signal CLdly 2 to output a signal Cdy 2 . NAND circuit ND 1 takes the NAND logic of signals /CTLvp and Cdy 2 , and outputs an output signal CLp.

Memory array 151 has the same configuration as memory array 151 shown in FIG. 5 , and memory cell MC constituting memory array 151 is the same as memory cell MC shown in FIG. 4 . Memory cell MC is shown only with inverters In 0 and In 1 in FIG. 10 , but is actually composed of the circuit shown in FIG. 4 .

FIG. 11 shows schematic signal waveforms of main nodes in this second modification. Referring to FIG. 11 , the operation of power supply control circuit 140 _ 12 will be described.

As shown in FIG. 11 at (a), authentication control signal CTLv is changed from the low level to the high level at time t 1 in response to authentication request signal Arq. Output signal /CTLv of inverter IV 0 receiving authentication control signal CTLv is changed from the high level to the low level at time t 2 , as shown in FIG. 11 at (d). As a result, n-type transistor Mvn 0 is brought into the non-conducting state, and supply of supply voltage Vss to power supply voltage output node Nn is interrupted.

As shown in FIG. 11 at (a) and (d), at time t 1 , authentication control signal CTLv is changed to the high level, and output signal/CTLvp of inverter IV 3 in delay control circuit DLp is changed to the low level at time t 2 . Accordingly, output signal CLp of NAND circuit ND 1 is changed to the high level. As a result, p-type transistor Mvp 0 is brought into the non-conducting state, and supply of the supply voltage Vpp to power supply voltage output node Np is interrupted.

As shown in FIG. 11 at (a) and (c), with the change of authentication control signal CTLv to the high level at time t 1 , output signal S of pulse generation circuit OSP is maintained at the low level in the period of delay time Tdly from time t 3 to time t 5 . The circuit operation in this period will be described with reference to FIG. 10 . When output signal S is changed to the low level, power supply voltage output nodes Nn and Np are short-circuited by p-type transistors Mhs, Mhu and Mhd, and intermediate voltage Vdd/2 is supplied thereto.

As shown in FIG. 11 at (e), after time t 3 , in memory cell MC, the electric potential at cell power line Vssn rises from supply voltage Vss, and reaches intermediate voltage Vdd/2 at time t 4 . Similarly, after time t 3 , the electric potential at cell power line Vddp drops from supply voltage Vdd, and reaches intermediate voltage Vdd/2 at time t 4 . Actually, even if the electric potentials at cell power lines Vddp and Vssn start to transition toward intermediate voltage Vdd/2 at time t 3 , both the electric potentials will not reach intermediate voltage Vdd/2 simultaneously at time t 4 . This is because cell power lines Vddp and Vssn have different values of wiring resistance and parasitic capacitance and differ in source impedance.

There will be no problem even if a difference arises between the setup time until cell power line Vddp reaches intermediate voltage Vdd/2 and the setup time until cell power line Vssn reaches intermediate voltage Vdd/2. The electric potentials at storage nodes N 00 and N 01 of memory cell MC should only be fixed at intermediate voltage Vdd/2 by the time when the electric potential at cell power line Vssn starts dropping from intermediate voltage Vdd/2 toward supply voltage Vss.

When authentication control signal CTLv is changed from the high level to the low level at time t 6 , output signal/CTLv of inverter IV 0 is changed from the low level to the high level, and n-type transistor Mvn 0 is brought into the conducting state. N-type transistor Mvn 0 supplies supply voltage Vss to power supply voltage output node Nn, and drops the electric potential at the sources of n-type transistors M 02 and M 03 of memory cell MC from intermediate voltage Vdd/2 to supply voltage Vss. On the other hand, the electric potential at cell power line Vddp is maintained at intermediate voltage Vdd/2 in the period from time t 6 to t 8 , and rises to supply voltage Vdd after time t 8

As shown in FIG. 11 at (a) or (b), signal CLp is changed from the high level to the low level at time t 8 after the lapse of delay time Tdly 2 from the change of authentication control signal CTLv from the high level to the low level at time t 6 . This delay time Tdly 2 is set up by delay circuit DLY 2 constituting delay control circuit DLp shown in FIG. 10 . With the change of authentication control signal CTLv from the high level to the low level, output signal/CTLvp of inverter IV 3 is changed from the low level to the high level.

On the other hand, in the period from time t 6 to time t 8 at which delay time Tdly 2 elapses, output signal Cdy 2 of inverter IV 4 is maintained at the low level, and output signal CLp of NAND circuit ND 1 is maintained at the high level. Therefore, p-type transistor Mvp 0 is maintained at the non-conducting state in the period of this delay time Tdly 2 . At time t 8 at which delay time Tdly 2 (exactly, a delay time including the circuit delay caused by inverter IV 4 ) elapses, signal Cdy 2 is changed to the high level, and output signal CLp of NAND circuit ND 1 is changed to the low level. As a result, p-type MOS transistor Mvp 0 is brought into the conducting state, and the electric potential at cell power line Vddp rises toward supply voltage Vdd. Referring to FIG. 11 ( e ) and the circuit diagram of inverters In 0 and In 1 of FIG. 10 , the electric potentials appearing at storage nodes N 00 and N 01 of the memory cell after time t 6 will be described. Here, for ease of description, it is assumed that threshold voltage Vth 02 of n-type transistor M 02 constituting memory cell MC is lower than threshold voltage Vth 03 of n-type transistor M 03 . It is noted that the electric potential at the source, drain and gate of each of the four MOS transistors constituting inverters In 0 and In 1 at time t 6 is intermediate voltage Vdd/2.

The electric potential at cell power line Vssn starts dropping at time t 6 , and reaches threshold voltage Vth 02 of n-type transistor M 02 at time t 7 . Since Vth 02 <Vth 03 holds in the above-described assumption, n-type transistor M 02 is brought into the conducting state, and n-type transistor M 03 is maintained at the non-conducting state. Because n-type transistor M 02 is brought into the conducting state, storage node N 00 and cell power line Vssn are electrically connected.

After time t 7 , the electric potential at storage node N 00 starts dropping with the electric potential at cell power line Vssn. The conducting state of n-type transistor M 02 means that the gate and source of n-type transistor M 03 have a common potential, and even if the electric potential at cell power line Vssn drops further, n-type transistor M 03 transitions while maintaining the non-conducting state. At time t 9 at which transition time Ttn elapses from time t 6 , the electric potential at storage node N 00 reaches supply voltage Vss.

When signal CLp is changed from the high level to the low level at time t 8 , p-type transistor Mvp 0 is brought into the conducting state, and the electric potential at supply voltage Vdd is supplied to power supply voltage output node Np. The electric potential at the sources of p-type transistors M 00 and M 01 connected to cell power line Vddp starts rising from intermediate voltage Vdd/2 toward supply voltage Vdd.

At time t 8 , the electric potential at storage node N 01 (gate electric potential at p-type transistor M 00 ) is maintained at intermediate voltage Vdd/2. On the other hand, the electric potential at storage node N 00 (gate electric potential at p-type transistor M 01 ) is lower than intermediate voltage Vdd/2. After time t 8 , the electric potential at cell power line Vddp rises toward supply voltage Vdd. When the electric potential difference between cell power line Vddp and storage node N 00 exceeds threshold voltage Vth 01 of p-type transistor M 01 , p-type transistor M 01 is brought into the conducting state, and the electric potential at storage node N 01 starts rising.

Even when Vth 00 <Vth 01 holds for the threshold voltages at this time, p-type transistor M 01 is brought into the conducting state earlier than p-type transistor M 00 if the difference caused by variations of the threshold voltages (a value obtained by subtracting threshold voltage Vth 00 from threshold voltage Vth 01 ) is at least smaller than a value obtained by subtracting the electric potential at storage node N 00 from intermediate voltage Vdd/2 at time t 8 .

When the difference between threshold voltages Vth 00 and Vth 01 caused by their variations is relatively great, a malfunction can be eliminated by setting delay time Tdly 2 to be long. Here, the malfunction means that the factor that determines data appearing in a memory cell is not established by the magnitude correlation between the threshold voltages of two n-type transistors M 02 and M 03 . In the period of transition time Ttp from time t 8 to time t 10 , the electric potential at storage node N 01 reaches supply voltage Vdd.

After time t 10 , data output circuit 152 (see FIG. 1 ) outputs data in each memory cell MC to BIST control circuit 102 as output data Dout. In response to request signal RQ from authentication control circuit 101 , BIST control circuit 102 returns the data in each memory cell MC to authentication control circuit 101 as memory data MD. Authentication control circuit 101 outputs this memory data MD as chip-specific identification information Chip_id.

Power supply control circuit 140 _ 12 according to the second modification of the first embodiment sets the source, drain and gate of the four MOS transistors constituting inverters In 0 and In 1 included in memory cell MC at an equal electric potential (intermediate voltage Vdd/2). Then, the electric potential at the common source of two n-type transistors M 02 and M 03 (electric potential at cell power line Vssn) is dropped. Of n-type transistors M 02 and M 03 , one having a lower threshold voltage is brought into the conducting state, and the electric potential at storage node N 00 or N 01 connected to the drain of that n-type transistor starts dropping.

Delay time Tdly 2 is set at a time period in which the electric potential at cell power line Vddp is maintained at intermediate voltage Vdd/2 until one of n-type transistors M 02 and M 03 is brought into the conducting state after the electric potential at cell power line Vssn starts dropping. After the lapse of delay time Tdly 2 , the electric potential at the common source of two p-type transistors M 00 and M 01 (electric potential at cell power line Vddp) constituting inverters In 0 and In 1 is raised. By these operations, data appearing at storage nodes N 00 and N 01 of memory cell MC is determined only by the variations in the threshold voltages of n-type transistors M 02 and M 03 constituting inverters In 0 and In 1 , and is not influenced by the threshold voltages of p-type transistors M 00 and M 01 .

As described above, for ease of description, it is assumed that threshold voltage Vth 02 of n-type transistor M 02 is lower than threshold voltage Vth 03 of n-type transistor M 03 . It is easily understood that this assumption is not an essential condition in the operation of the present modification, but the data in storage nodes N 00 and N 01 of memory cell MC is determined by the magnitude correlation between threshold voltages Vth 02 and Vth 03 .

[Second Embodiment]

Referring to FIG. 12 , a configuration of an identification information generation circuit 100 _ 2 included in a semiconductor device according to a second embodiment of the present invention will be described.

Identification information generation circuit 100 _ 2 differs from identification information generation circuit 100 _ 1 of the semiconductor device according to the first embodiment of the present invention shown in FIG. 1 in that identification information generation circuit 100 _ 1 shown in FIG. 1 has authentication control circuit 101 and power supply control circuit 140 _ 1 , while identification information generation circuit 100 _ 2 shown in FIG. 12 has an authentication control circuit 101 _ 2 and a power supply control circuit 140 _ 2 .

Although authentication control circuits 101 and 101 _ 2 both output authentication control signal CTLv, authentication control circuit 101 _ 2 further outputs a P/N advance control signal CTLpn having a binary value. Although power supply control circuits 140 _ 1 and 140 _ 2 both include input node Nc 1 , power supply control circuit 140 _ 2 further includes an input node Nc 2 .

Referring to FIG. 13 , a circuit block configuration of power supply control circuit 140 _ 2 according to the second embodiment of the present invention will be described. Power supply control circuit 140 _ 2 corresponds to the configuration in which functions corresponding to delay control circuit DLn shown in FIG. 8 and delay control circuit DLp shown in FIG. 10 are added to power supply control circuit 140 _ 1 shown in FIG. 5 . In power supply control circuit 140 _ 2 , functional blocks, transistors, signal lines and the like denoted by the same reference characters as those shown in FIG. 5 are identical in function and configuration to those of power supply control circuit 140 _ 1 , and description thereof will not be repeated.

Memory array 151 has the same configuration as memory array 151 shown in FIG. 5 . Memory cell MC included in memory array 151 has the same configuration as memory cell MC shown in FIG. 4 . In memory cell MC in memory array 151 shown in FIG. 13 , only the circuit of inverters In 0 and In 1 is shown, and n-type transistors M 04 and M 05 are not shown.

Power supply control circuit 140 _ 2 has input nodes Nc 1 , Nc 2 , intermediate voltage input node Nd, power supply voltage output nodes Nn, Np, a delay control circuit DLsn, and a delay control circuit DLsp. P/N advance control signal CTLpn having a binary value is applied to input node Nc 2 .

Delay control circuit DLsn in power supply control circuit 140 _ 2 includes delay circuit DLY 1 , an inverter IV 6 and NOR circuits NR 2 , NR 1 . Delay circuit DLY 1 delays authentication control signal CTLv by delay time Tdly 1 to output delay signal CLdly 1 . Inverter IV 6 receives delay signal CLdly 1 , and outputs an inversion signal b. NOR circuit NR 2 obtains the NOR logic of P/N advance control signal CTLpn applied to input node Nc 2 and delay signal CLdly 1 , and outputs a signal Cd 1 . NOR circuit NR 1 obtains the NOR logic of authentication control signal CTLv and signal Cd 1 , and outputs signal CLn to the gate of n-type transistor Mvn 0 .

Delay control circuit DLsp includes delay circuit DLY 2 , a NAND circuit ND 2 , NAND circuit ND 1 , and an inverter IV 5 . Delay circuit DLY 2 delays authentication control signal CTLv applied to input node Nc 1 by delay time Tdly 2 to output signal CLdly 2 . NAND circuit ND 2 obtains the NAND logic of P/N advance control signal CTLpn and signal CLdly 2 , and outputs a signal Cd 2 . Inverter IV 5 receives authentication control signal CTLv, and inverts the logic to output signal/CTLvp. NAND circuit ND 1 obtains the NAND logic of signals Cd 2 and /CTLvp, and outputs signal CLp to the gate of p-type transistor Mvp 0 .

Referring to FIG. 14 , the operation of power supply control circuit 140 _ 2 will be described.

As shown in FIG. 14 at (a), P/N advance control signal CTLpn is set at the low level in a period Tpbn from time t 1 to time t 9 . P/N advance control signal CTLpn is set at the high level in a period Tnbp from time t 11 to time t 19 . This setup order of the low level period and the high level period of P/N advance control signal CTLpn is for illustration of the present embodiment. The setup period of low level and that of the high level of P/N advance control signal CTLpn may be exchanged, and it is not an essential setup for the operation of the present embodiment.

In period Tpbn, one of inputs of NAND circuit ND 2 in delay control circuit DLsp (P/N advance control signal CTLpn) is set at the low level. Output signal Cd 2 of NAND circuit ND 2 is maintained at the high level without depending on the logic level of the other input signal CLdly 2 . Therefore, as shown in FIG. 14 at (e), output signal CLp of NAND circuit ND 1 is subjected to the circuit delays caused by inverter IV 5 and NAND circuit ND 1 , and reaches the logic level of the same phase as authentication control signal CTLv.

Therefore, at time t 3 , signal CLp is changed from the low level to the high level. When signal CLp is changed to the high level, p-type transistor Mvp 0 is brought into the non-conducting state, and supply of supply voltage Vdd to power supply voltage output node Np is interrupted.

As shown in FIG. 14 at (b) and (d), when authentication control signal CTLv is changed from the low level to the high level at time t 2 , signal CLn from NOR circuit NR 1 is changed from the high level to the low level. When signal CLn is changed to the low level, n-type transistor Mvn 0 is brought into the non-conducting state, and supply of supply voltage Vss to power supply voltage output node Nn is interrupted.

As shown in FIG. 14 at (b), when authentication control signal CTLv is changed from the low level to the high level at time t 2 , signal S from inverters IV 0 , IV 1 , IV 2 and pulse generation circuit OSP is changed from the high level to the low level at time t 4 as shown in FIG. 14 ( f ) and changed from the low level to the high level at time t 5 after the lapse of delay time Tdly.

As shown at time t 4 in FIG. 14 at (f), signal S is changed from the high level to the low level. As shown in FIG. 14 at (g), the electric potentials at cell power lines Vssn and Vddp transition from supply voltages Vss and Vdd to intermediate voltage Vdd/2, respectively.

As shown in FIG. 14 at (b) and (c), authentication control signal CTLv is changed from the high level to the low level at time t 6 , and signal CLp from inverter IV 5 and NAND circuit ND 1 is changed from the high level to the low level at time t 7 . P-type transistor Mvp 0 receiving signal CLp at its gate supplies supply voltage Vdd to power supply voltage output node Np. It is noted that the circuit delays caused by inverter IV 5 and NAND circuit ND 1 in delay control circuit DLsp are shorter than that caused by delay circuit DLY 2 or the like. Therefore, signal/CTLvp, signal CLp and authentication control signal CTLv shall be changed at substantially the same timing.

As shown in FIG. 14 at (b) and (d), when authentication control signal CTLv is changed from the high level to the low level at time t 6 , signal CLn is changed from the low level to the high level at time t 8 at which delay time Tdly 1 elapses from time t 6 . This delay time Tdly 1 indicates a delay time produced when authentication control signal CTLv passes through delay circuit DLY 1 , inverter IV 6 , and NOR circuits NR 2 and NR 1 shown in FIG. 13 . It is noted that, since the circuit delays caused by inverter IV 6 and NOR circuits NR 2 and NR 1 are shorter than the delay time caused by delay circuit DLY 1 , delay time Tdly 1 is mostly determined by the delay caused by delay circuit DLY 1 .

As shown in FIG. 14 at (d) and (g), when signal CLn is changed from the low level to the high level at time t 8 , n-type transistor Mvn 0 receiving signal CLn at its gate is brought into the conducting state, and supplies supply voltage Vss to power supply voltage output node Nn. The mechanism in which data appearing at storage nodes N 00 and N 01 in memory cell MC is determined after time t 7 in the period (Tpbn) in which P/N advance control signal CTLpn is at the low level overlaps FIGS. 8 , 9 and their relevant description, and description thereof will not be repeated here.

As described above, in the present embodiment, by setting P/N advance control signal CTLpn at the low level, the time point at which cell power line Vddp starts rising from intermediate voltage Vdd/2 to supply voltage Vdd can precede the time point at which cell power line Vssn starts dropping from intermediate voltage Vdd/2 to supply voltage Vss.

Through use of this system, data in memory cell MC can be determined based on the magnitude correlation between the threshold voltages of p-type transistors M 00 and M 01 constituting inverters In 0 and In 1 in memory cell MC. Moreover, as described above, since the factor that determines the data in memory cell MC is limited to the difference between the threshold voltages of the two p-type transistors, reproducibility of data appearing in a memory cell when the identification number of a semiconductor device is re-generated by the present system is high.

Next, a system for controlling power supply control circuit 140 _ 2 by authentication control signal CTLv in period Tnbp in which P/N advance control signal CTLpn is maintained at the high level will be described.

As shown in FIG. 14 at (a) and (d), P/N advance control signal CTLpn is set at the high level in period Tnbp from time t 11 to time t 19 . Output signal Cd 1 of NOR circuit NR 2 is maintained at the low level, without depending on the logic level of the other input signal b. Therefore, signal CLn input to the gate of n-type transistor Mvn 0 has a logic level obtained by inverting authentication control signal CTLv in NOR circuit NR 1 .

As shown in FIG. 14 at (b) and (e), the change of authentication control signal CTLv at time t 12 from the low level to the high level changes signal CLp from the low level to the high level at time t 13 after subjected to the circuit delays caused by inverter IV 5 and NAND circuit ND 1 . Signal CLp is input to the gate of p-type transistor Mvp 0 , and supply of supply voltage Vdd to power supply voltage output node Np is interrupted.

When authentication control signal CTLv is changed from the low level to the high level at time t 12 , output signal CLn of delay control circuit DLsn is changed from the high level to the low level (see FIG. 14 ( d )). Signal CLn is input to the gate of n-type transistor Mvn 0 , and supply of supply voltage Vss to power supply voltage output node Nn is interrupted.

Furthermore, when authentication control signal CTLv is changed from the low level to the high level at time t 12 , output signal S obtained from inverters IV 0 , IV 1 , IV 2 and pulse generation circuit OSP is maintained at the low level in the period of delay time Tdly from time t 14 to time t 15 (see FIG. 14 ( f )).

Signal S is changed from the high level to the low level at time t 14 , and as shown in FIG. 14 at (g), the electric potentials at cell power lines Vssn and Vddp transition from supply voltages Vss and Vdd to intermediate voltage Vdd/2, respectively.

As shown in FIG. 14 at (b) and (g), when authentication control signal CTLv is changed from the high level to the low level at time t 16 , and output signal CLn is changed from the low level to the high level at time t 17 through NOR circuit NR 1 . Therefore, n-type transistor Mvn 0 receiving output signal CLn at its gate supplies supply voltage Vss to power supply voltage output node Nn. It is noted that, since the circuit delay caused by NOR circuit NR 1 in delay control circuit DLsn is shorter than that caused by delay circuit DLY 1 or the like, signal CLn is shown to be changed substantially at the same timing as authentication control signal CTLv.

When authentication control signal CTLv is changed from the high level to the low level at time t 16 , signal CLp is changed from the high level to the low level at time t 18 at which delay time Tdly 2 elapses from time t 16 (see FIG. 14 ( e )). This delay time Tdly 2 is a total sum of circuit delays caused by delay circuit DLY 2 , NAND circuit ND 2 and NAND circuit ND 1 . It is noted that, since the circuit delay caused by delay circuit DLY 2 is longer than those caused by NAND circuits ND 2 and ND 1 , delay time Tdly 2 shall be equal to the circuit delay caused by delay circuit DLY 2 .

As shown in FIG. 14 at (e), when signal CLp is changed from the high level to the low level at time t 18 , p-type transistor Mvp 0 receiving signal CLp at its gate is brought into the conducting state, and supplies supply voltage Vdd to power supply voltage output node Np. The mechanism in which data appearing at storage nodes N 00 and N 01 in memory cell MC is determined after time t 17 in the period (Tnbn) in which P/N advance control signal CTLpn is at the high level overlaps FIGS. 8 , 9 and their relevant description, and description thereof will not be repeated here.

As described above, in the present embodiment, by setting P/N advance control signal CTLpn at the high level, the time point at which cell power line Vssn starts dropping from intermediate voltage Vdd/2 to supply voltage Vss can precede the time point at which cell power line Vddp starts rising from intermediate voltage Vdd/2 to supply voltage Vdd.

With this system, data in memory cell MC can be determined based on the magnitude correlation between the threshold voltages of n-type transistors M 02 and M 03 constituting inverters In 0 and In 1 in memory cell MC. Moreover, in the present embodiment, since appearing data is determined by the aforementioned factor, reproducibility of data appearing in a memory cell when the identification number of a semiconductor device is re-generated by the present system is high.

Referring to FIG. 15 , a data pattern of chip-specific identification information Chip_id generated by identification information generation circuit 100 _ 2 according to the second embodiment of the present invention will be described.

FIG. 15 schematically shows at (a), (b) and (c) memory arrays each having m-bit memory cells along the word line and n-bit memory cells along the bit line. FIG. 15 shows at (a) an example data pattern in which the timing of supplying supply voltage Vdd to cell power line Vddp precedes the timing of supplying supply voltage Vss to cell power line Vssn. This data pattern is determined based on the magnitude correlation between the threshold voltages of two p-type transistors in memory cell MC.

The address of the left upper memory cell MC is (0, 0), and the address of the right upper memory cell MC is (m−1, 0). The address of the left lower memory cell MC is (0, n−1), and the address of the right lower memory cell MC is (m−1, n−1). Here, X address and Y address are indicated in the parenthesis.

A memory array subjected to detection of the data pattern shown in FIG. 15 at (a) may be all the memory cells MC included in memory array 151 of FIG. 12 or some memory cells MC included in memory array 151 .

In FIG. 15 at (a), hatched cells are intended to indicate that data “1” is held therein, and blank cells are intended to indicate that data “0” is held therein. Data “0” and data “1” represent the electric potentials complementarily held at storage nodes N 00 and N 01 (supply voltage Vss or supply voltage Vdd). Data “0” corresponds to the case where storage node N 00 is at supply voltage Vss, and data “1” corresponds to the case where storage node N 00 is at supply voltage Vdd.

FIG. 15 shows at (b) an example data pattern in which the timing of supplying supply voltage Vss to cell power line Vssn precedes the timing of supplying supply voltage Vdd to cell power line Vddp. This data pattern is determined based on the magnitude correlation between the threshold voltages of two n-type transistors in memory cell MC.

The data patterns shown in FIG. 15 at (a) and (b) are obtained in time series. When the data shown in FIG. 15 at (a) is obtained, data output circuit 152 outputs output data Dout to BIST control circuit 102 . In response to request signal RQ output from authentication control circuit 101 _ 2 , BIST control circuit 102 returns the data pattern to authentication control circuit 101 _ 2 as memory data MD. Authentication control circuit 101 _ 2 outputs the data pattern as chip-specific identification information Chip_id (see FIG. 12 ). Next, when the data shown in FIG. 15 at (b) is obtained, data output circuit 152 outputs the data pattern as chip-specific identification information Chip_id similarly to the above.

A service provider having received the respective data patterns shown in FIG. 15 at (a) and (b) as chip-specific identification information Chip_id generates new chip-specific identification information based on these two data patterns.

FIG. 15 shows at (c) an example of new chip-specific identification information generated by the service provider based on the respective data patterns shown in FIG. 15 at (a) and (b). The data pattern shown in FIG. 15 at (c) is the result of performing an OR operation on each piece of data held at an identical memory cell address in FIG. 15 at (a) and (b). Not only an OR operation but also an AND operation or another logical operation may be applied to operation of each piece of data.

Identification information generation circuit 100 _ 2 according to the second embodiment of the present invention generates two data patterns from memory array 151 . Therefore, it is still more difficult for an attacker to read chip-specific identification information. Furthermore, since chip-specific identification information is generated by performing a logical operation between these two data patterns, an attacker cannot derive the chip-specific identification information unless he/she obtains this logical operation. Therefore, the chip-specific identification information generated through use of the present system is improved in resistance to tampering (reliability).

[Third Embodiment]

Referring to FIG. 16 , a configuration of an identification information generation circuit 100 _ 3 included in a semiconductor device according to a third embodiment of the present invention will be described.

Identification information generation circuit 100 _ 3 differs from identification information generation circuit 100 _ 1 of the semiconductor device according to the first embodiment of the present invention shown in FIG. 1 in the configuration of a power supply control circuit 140 _ 3 and a memory array 151 _ 3 .

Referring to FIG. 17 , a circuit block configuration of power supply control circuit 140 _ 3 and memory array 151 _ 3 according to the third embodiment of the present invention will be described.

Power supply control circuit 140 _ 3 has input node Nc 1 , intermediate voltage input node Nd, and power supply voltage output nodes Nn 0 , Nn 1 and Np. Authentication control signal CTLv is applied to input node Nc 1 , and intermediate voltage Vdd/2 is applied to intermediate voltage input node Nd.

In power supply control circuit 140 _ 3 , n-type transistor Msn 0 has its drain connected to power supply voltage output node Nn 0 , and supply voltage Vss is applied to the source. An n-type transistor Myn 00 has its drain connected to power supply voltage output node Nn 0 , and its source connected to one end of a resistor R 00 . Supply voltage Vss is applied to the other end of resistor R 00 .

An n-type transistor Msn 1 has its drain connected to power supply voltage output node Nn 1 , and supply voltage Vss is applied to the source. An n-type transistor Mvn 01 has its drain connected to power supply voltage output node Nn 1 , and its source connected to one end of a resistor R 01 . Supply voltage Vss is applied to the other end of resistor R 01 .

P-type transistor Mvp 0 has its drain connected to power supply voltage output node Np, and supply voltage Vdd is applied to the source. P-type transistor Mhs is interposed between power supply voltage output nodes Np and Nn 0 , and has its source and drain connected to power supply voltage output node Np and Nn 0 , respectively. A p-type transistor Mhsd is interposed between power supply voltage output nodes Nn 0 and Nn 1 , and has its source and drain connected to power supply voltage output node Nn 0 and Nn 1 , respectively.

P-type transistors Mhu and Mhd 0 having a common drain are interposed between power supply voltage output nodes Nn 0 and Np, and have their sources connected to power supply voltage output nodes Np and Nn 0 , respectively. The common drain of p-type transistors Mhu and Mhd 0 is connected to intermediate voltage input node Nd. P-type transistor Mhd 1 has its source connected to intermediate voltage input node Nd, and its drain connected to power supply voltage output node Nn 1 .

Signal S is applied to the gate of each of p-type transistors Mhs, Mhu, Mhd 0 , Mhd 1 , and Mhsd. The same circuit configuration as pulse generation circuit OSP shown in FIG. 5 is used for pulse generation circuit OSP that generates signal S.

Authentication control signal CTLv applied to input node Nc 1 is applied to the gate of p-type transistor Mvp 0 and inverter IV 0 . Inverter IV 0 inverts the logic of authentication control signal CTLv to output control signal /CTLv. Control signal /CTLv is applied to the gate of each of n-type transistors Myn 00 and Mvn 01 .

Authentication control signal CTLv passes through inverters IV 0 , IV 1 , and IV 2 to generate signal a. Signal a is applied to the input of pulse generation circuit OSP and the gate of each of n-type transistors Msn 0 and Msn 1 .

Unlike the first embodiment shown in FIG. 5 , supply voltage Vss is supplied to memory array 151 _ 3 through two power supply voltage output nodes Nn 0 and Nn 1 included in power supply control circuit 140 _ 3 . This memory cell is indicated as MC_ 3 , and the bit number corresponding to a bit line pair is set at 1 bit. To indicate the address of a memory cell, the following notation system is adopted. A memory cell MC 300 is expressed as (word address: 0, bit address: 0), and a memory cell MC_ 30 (n−1) is expressed as (word address: 0, bit address: (n−1)). A total of n memory cells MC_ 3 are arrayed.

It is noted that, although memory array 151 _ 3 is configured such that a bit line pair corresponds to 1 bit in the third present embodiment, the object and effects of the present patent application will not be affected even with a configuration for more than 1 bit or even if the memory array has a configuration different from that of the present embodiment.

Memory cell MC_ 3 has inverters Im 0 and Im 1 . The sources of n-type transistors M 02 and M 03 of inverters Im 0 and Im 1 are separated, and supply voltage Vss is supplied to each inverter.

In FIG. 17 , n-type transistor M 02 included in inverter Im 0 and n-type and transistor M 03 included in inverter Im 1 have their sources connected to cell power lines Vssn 0 and Vssn 1 , respectively. Cell power lines Vssn 0 and Vssn 1 are connected to power supply voltage output nodes Nn 0 and Nn 1 , respectively. P-type transistor M 00 included in inverter Im 0 and p-type transistor M 01 included in inverter Im 1 have their sources connected in common to cell power line Vddp. Cell power line Vddp is connected to power supply voltage output node Np.

As shown in FIG. 17 , cell power lines Vssn 0 , Vssn 1 and Vddp have parasitic capacitances Cd 0 , Cd 1 and Cu, respectively.

Referring to FIG. 18 , the operation of power supply control circuit 140 _ 3 will be described.

As shown in FIG. 18 at (a) and (b), when authentication control signal CTLv is changed from the low level to the high level at time t 1 , signal /CTLv is changed from the high level to the low level at time t 2 .

As shown in FIG. 18 at (b), (c) and (d), the logic level of signal /CTLv changes at time t 2 , and output signal a is changed from the high level to the low level at time t 3 through inverters IV 1 and IV 2 . Output signal S of pulse generation circuit OSP receiving signal a is maintained at the low level in the period of delay time Tdly from time t 4 to time t 5 .

As shown in FIG. 18 at (a) and (c), in the period until time t 3 , signal a is maintained at the high level in accordance with the low level of authentication control signal CTLv. In this period, n-type transistors Msn 0 and Msn 1 shown in FIG. 17 are in the conducting state. Therefore, the electric potentials at cell power lines Vssn 0 and Vssn 1 are maintained at supply voltage Vss.

As shown in FIG. 18 at (b) to (e), after time t 3 , signal /CTLv and signal a are maintained at the low level, and n-type transistors Myn 00 , Mvn 01 , Msn 0 , and Msn 1 are in the non-conducting state. When signal S is changed from the high level to the low level at time t 4 , p-type transistors Mhs and Mhsd are brought into the conducting state to short-circuit each of power supply voltage output nodes Np, Nn 0 and Nn 1 . P-type transistors Mhu, Mhd 0 and Mhd 1 are also brought into the conducting state, and intermediate voltage Vdd/2 is supplied to all of power supply voltage output nodes Nn 0 , Nn 1 and Np.

As shown in FIG. 18 at (a) and (b), when authentication control signal CTLv is changed from the high level to the low level at time t 6 , signal /CTLv is changed from the low level to the high level after subjected to the circuit delay caused by inverter IV 0 . Since the circuit delay caused by inverter IV 0 is shorter than the delay time caused by delay circuit DLY or the like, the timing at which this signal /CTLv is changed is shown to be substantially the same as time t 6 .

As shown in FIG. 18 at (e), when signal /CTLv is changed from the low level to the high level at time t 6 , n-type transistors Mvn 00 and Mvn 01 shown in FIG. 17 are brought into the conducting state. The electric potential at power supply voltage output node Nn 0 drops from intermediate voltage Vdd/2 to supply voltage Vss through n-type transistor Mvn 00 and resistor R 00 . The electric potential at power supply voltage output node Nn 1 also drops from intermediate voltage Vdd/2 to supply voltage Vss through n-type transistor Mvn 01 and resistor R 01 .

The present embodiment is intended to adjust appearance ratio of data “0” or “1” in memory cell MC_ 3 . For example, for the threshold voltages of n-type transistors M 02 and M 03 in the memory cell, if an imbalanced tendency of variation in threshold voltage Vth 02 <variation in threshold voltage Vth 03 is fixed due to a mask displacement in the manufacturing process or the like, randomness of data appearance will be impaired.

Then, this randomness is restored by setting resistors R 00 and R 01 to have different resistance values. The paths from the nodes of the sources of n-type transistors M 02 and M 03 included in inverters Im 0 and Im 1 in memory cell MC_ 3 to supply voltage Vss have different impedance values. Supply voltage Vss is applied to cell power line Vssn 0 through n-type transistor Mvn 00 and resistor ROD, and supply voltage Vss is applied to cell power line Vssn 1 through n-type transistor Mvn 01 and resistor R 01 .

As shown in FIG. 18 at (b), when signal /CTLv is changed from the low level to the high level at time t 6 , electric charge in each line set at intermediate voltage Vdd/2 is discharged, so that the electric potentials at cell power lines Vssn 0 and Vssn 1 drop to supply voltage Vss. The discharge speed of each line is expressed by the time constants of resistance and capacitance of the path. Therefore, the difference between discharge speeds of electric charges charged at the sources of n-type transistors M 02 and M 03 is the difference between the resistance values of resistors RO 0 and R 01 , assuming that the parasitic resistance and parasitic capacitance of cell power lines Vssn 0 and Vssn 1 are in the same conditions.

As to the n-type transistors of the first and second embodiments, data appearing in a memory cell is determined by the contribution of the magnitude correlation between the threshold voltages of n-type transistors M 02 and M 03 . However, in consideration of the aforementioned discharge speeds, randomness of data appearing in a memory cell can be maintained by a design under the condition that the resistance value of resistor R 00 >the resistance value of resistor R 01 even if there is an imbalanced tendency of variation in threshold voltage Vth 02 <variation in threshold voltage Vth 03 . In FIG. 18 at (e), the portion enclosed with a dashed ellipse shows the state of the electric potentials at cell power lines Vssn 0 and Vssn 1 after time t 6 . FIG. 19 shows that portion on an enlarged scale.

Referring to FIG. 19 , the operation of memory cell MC_ 3 after time t 6 will be described.

For ease of description of the present embodiment, it is assumed that the resistance value of resistor R 00 shown in FIG. 17 is higher than that of resistor R 01 , and that threshold voltage Vth 01 of p-type transistor M 01 in memory cell MC_ 3 is lower than threshold voltage Vth 00 of p-type transistor M 00 . It is also assumed that threshold voltage Vth 02 of n-type transistor M 02 is lower than threshold voltage Vth 03 of n-type transistor M 03 . Furthermore, the threshold voltage of a p-type transistor shall be higher than that of an n-type transistor. On these assumptions, the threshold voltage of n-type transistor M 02 is the lowest on the premise that data appearing in a memory cell is determined by the magnitude correlation between threshold voltages. Therefore, the electric potential at supply voltage Vss will necessarily appear at storage node N 00 .

As shown in FIG. 18 at (e), at time t 6 , the electric potentials at the source, drain and gate of each of the four transistors constituting inverters Im 0 and Im 1 are maintained at intermediate voltage Vdd/2. When authentication control signal CTLv is changed from the high level to the low level at time t 6 , cell power line Vddp starts rising from intermediate voltage Vdd/2 toward supply voltage Vdd, and the electric potentials at cell power lines Vssn 0 and Vssn 1 start dropping from intermediate voltage Vdd/2 toward supply voltage Vss.

Cell power line Vssn 0 is connected to n-type transistor Mvn 00 through resistor R 00 , and cell power line Vssn 1 is connected to power line Vss through n-type transistor Mvn 01 and resistor R 01 . In the present embodiment, it is assumed that resistor R 00 has a resistance greater than that of resistor R 01 . For this reason, the electric potential at cell power line Vssn 0 has a dropping transition speed slower than that of the electric potential at cell power line Vssn 1 . Similarly to the first and second embodiments, the electric potential at cell power line Vddp rises quickly to supply voltage Vdd by p-type transistor Mvp 0 being brought into the conducting state.

In FIG. 19 , at time t 61 , the electric potentials at storage nodes N 00 and N 01 are maintained at intermediate voltage Vdd/2, and the electric potential at cell power line Vssn 1 is lower than that of cell power line Vssn 0 . This is because the electric potential at cell power line Vssn 0 has a dropping transition speed slower than that of the electric potential at cell power line Vssn 1 .

At this time, it is of concern which one of n-type transistors M 02 and M 03 has been brought into the conducting state earlier at time t 61 . In the description of the present third embodiment, it is assumed that, at time t 61 , the electric potential difference between intermediate voltage Vdd/2 (electric potential at storage nodes N 00 and N 01 ) and cell power line Vssn 1 reaches Vth 03 , and the electric potential difference between intermediate voltage Vdd/2 and cell power line Vssn 0 has not reached Vth 02 . Accordingly, n-type transistor M 03 is brought into the conducting state, and the electric potential at storage node N 01 drops to the electric potential at cell power line Vssn 1 .

As to the p-type transistors, the threshold voltage of p-type transistor M 00 is higher than that of p-type transistor M 01 , but the electric potential at storage node N 01 is lower than intermediate voltage Vdd/2 at time t 62 . Therefore, the electric potential difference between the gate and source of p-type transistor M 00 reaches threshold voltage Vth 00 , and p-type transistor M 00 is brought into the conducting state. On the other hand, the electric potential at storage node N 00 is intermediate voltage Vdd/2, and the electric potential difference from cell power line Vddp has not reached threshold voltage Vth 01 of p-type transistor M 01 . Therefore, p-type transistor M 01 is in the non-conducting state.

After time t 62 , the electric potential at storage node N 01 becomes equal to that of cell power line Vssn 1 , and the electric potential at storage node N 00 becomes equal to that of cell power line Vddp. Therefore, n-type transistors M 02 and M 01 are maintained in the non-conducting state, the electric potentials at cell power lines Vssn 0 and Vssn 1 transition to supply voltage Vss, and the electric potential at cell power line Vddp transitions to supply voltage Vdd.

Returning to time t 61 , the case where n-type transistor M 02 is brought into the conducting state earlier is now considered. After time t 61 , the electric potential at storage node N 01 is maintained at intermediate voltage Vdd/2, and the electric potential at storage node N 00 becomes equal to and transitions with that of cell power line Vssn 0 . In the process in which the electric potential at cell power line Vddp rises after time t 61 , it is clear that p-type transistor M 01 is brought into the conducting state earlier than p-type transistor M 00 , and the electric potential at storage node N 01 becomes equal to and transitions with that of cell power line Vddp.

As described above, if there is an imbalanced tendency in magnitude correlation between threshold voltages of paired MOS transistors, randomness of data appearing in a memory cell can be improved by adjusting the resistance values in accordance with the present system. The threshold voltage of a p-type transistor shall be higher than that of an n-type transistor in the present embodiment. If the threshold voltage of a p-type transistor is lower than that of an n-type transistor, appearing data is determined by variations in threshold voltage of the p-type transistor. Randomness is thus ensured. If there is an imbalanced tendency in threshold voltage of the p-type transistor, randomness can be adjusted by adopting the power supply control circuit of the second modification of the first embodiment shown in FIG. 10 to separate power line Vddp for each inverter and insert a resistor between the source of a p-type transistor and supply voltage Vdd similarly to the present embodiment.

After time t 7 , data output circuit 152 shown in FIG. 16 outputs data appearing at storage nodes N 00 and N 01 shown in FIG. 19 , held by each of memory cells MC _ 300 to MC_ 30 (n−1), to BIST control circuit 102 as output data Dout. In response to request signal RQ output from authentication control circuit 101 , BIST control circuit 102 returns data in each memory cell MC to authentication control circuit 101 as memory data MID. Authentication control circuit 101 outputs this memory data MD as chip-specific identification information Chip_id.

In the present embodiment, a resistor is connected to the source of each of n-type transistors Mvn 00 and Mvn 01 . As another embodiment that achieves effects similar to those of the present embodiment, a system in which a capacitance is connected to each of power supply voltage output nodes Nn 0 and Nn 1 and the power lines are varied in time constant may be adopted. Moreover, in the configuration of this system, the above-mentioned resistance values may be zero or may have an equal value.

[Fourth Embodiment]

Referring to FIG. 20 , a configuration of an identification information generation circuit 100 _ 4 included in a semiconductor device according to a fourth embodiment of the present invention will be described.

Identification information generation circuit 100 _ 4 differs from identification information generation circuit 100 _ 1 of the semiconductor device according to the first embodiment of the present invention shown in FIG. 1 in the configuration of a memory array 151 _ 4 .

Referring to FIG. 21 , a circuit block configuration of memory array 151 _ 4 according to the fourth embodiment of the present invention will be described.

Memory array 151 _ 4 has n memory cells MC arranged along bit lines BL and /BL and m memory cells MC arranged along word line WL. The number of memory cells MC in memory array 151 _ 4 is expressed as n X m. It should be noted that the value of m is 1 in memory array 151 _ 4 shown in FIG. 21 . Memory cell MC has the same circuit configuration as that of FIG. 4 , and description of the circuit configuration and the function of each MOS transistor will not be repeated. Cell power line Vssn of each memory cell (MC 00 to MC 0 (n−1)) is connected to power supply voltage output node Nn, and cell power line Vddp is similarly connected to power supply voltage output node Np.

Memory array 151 _ 4 further has a bit line intermediate voltage supply circuit EQhvd connected to each bit line pair (BL, /BL).

Bit line intermediate voltage supply circuit EQhvd includes p-type transistors Mbt 0 , Mbb 0 and Mbs 0 . P-type transistors Mbt 0 and Mbb 0 have a common source, and intermediate voltage input node Nd through which intermediate voltage Vdd/2 is supplied is connected to the node of the common source. P-type transistor Mbt 0 has its drain connected to bit line BL[ 0 ], and p-type transistor Mbb 0 has its drain connected to a bit line /BL[ 0 ]. P-type transistor Mbs 0 has its source and drain connected to bit lines BL and /BL, respectively. Signal S generated by power supply control circuit 140 _ 1 is applied to the gates of p-type transistors Mbt 0 , Mbb 0 and Mbs 0 .

Referring to FIG. 22 , the operation of power supply control circuit 140 _ 1 and memory array 151 _ 4 will be described.

As shown in FIG. 22 at (a) and (c), authentication control signal CTLv is changed from the low level to the high level at time t 1 , and signal S is maintained at the low level in the period of delay time Tdly from time t 3 to time t 4 . Therefore, as shown in FIG. 22 at (d), after time t 3 , the electric potentials at cell power lines Vssn and Vddp transition from supply voltages Vss and Vdd to intermediate voltage Vdd/2, respectively.

A precharge circuit (not shown) having the same circuit configuration as bit line intermediate voltage supply circuit EQhvd and supplying supply voltage Vdd is connected to bit lines BL[ 0 ] and /BL[ 0 ] shown in FIG. 21 . As shown in FIG. 22 at (e), in the preparatory step before starting access to a memory cell (read operation or write operation), the above-mentioned precharge circuit precharges one pair of bit lines BL[ 0 ] and /BL[ 0 ] to supply voltage Vdd. Then, at time t 3 when signal S is changed from the high level to the low level, the electric potential at one pair of bit lines BL and /BL starts transitioning toward intermediate voltage Vdd/2. This is because three p-type transistors Mbt 0 , Mbb 0 and Mbs 0 in bit line intermediate voltage supply circuit EQhvd shown in FIG. 21 short-circuit one pair of bit lines BL and /BL with the low level of signal S functioning as a trigger signal and supply intermediate voltage Vdd/2 to each bit line.

As shown in FIG. 22 at (f), in a period Tw from time tw 0 s to time tw 0 e, a pulse signal for raising the electric potential to supply voltage Vdd is applied to word line WL[ 0 ]. As a result, intermediate voltage Vdd/2 output from bit line intermediate voltage supply circuit EQhvd is applied to storage nodes N 00 and N 01 through access MOS transistors (n-type transistors M 04 and M 05 ) of memory cell MC shown in FIG. 4 .

In the power supply control circuits according to the first to third embodiments, the electric potentials at storage nodes N 00 and N 01 are set at Vdd/2 by setting cell power lines Vssn and Vddp to have intermediate voltage Vdd/2 while maintaining the access MOS transistors (M 04 and M 05 ) in the non-conducting state. With this system in which the access MOS transistors (M 04 and M 05 ) are maintained in the non-conducting state, the electric potential at storage node N 00 or N 01 may be lower than intermediate voltage Vdd/2 by the threshold voltage of any of the four MOS transistors except the access MOS transistors in a memory cell or higher than intermediate voltage Vdd/2 by the threshold voltage.

This is because either a p-type transistor or an n-type transistor is brought into the non-conducting state before the electric potentials at the storage nodes reach intermediate voltage Vdd/2. However, this electric potential shifted from intermediate voltage Vdd/2 by the threshold voltage is a temporary electric potential, and the electric potentials at storage nodes N 00 and N 01 eventually reach intermediate voltage Vdd/2 because of current leakage (subthreshold leakage and gate leakage) brought about in MOS transistors. According to the present fourth embodiment, however, the electric potentials at the storage nodes can reach intermediate voltage Vdd/2 within an estimated period.

In FIG. 22 at (f), a period Tsw from time t 3 to time tw 0 s is a period for setting the electric potentials at cell power lines Vssn, Vddp and bit lines BL, /BL at intermediate voltage Vdd/2. When adopting a clock synchronization type SRAM, it is only necessary to take a sufficient clock cycle and set period Tsw in the design stage. Moreover, as shown in FIG. 22 at (c) and (f), it is only necessary to design a period Tew from time tw 0 e to time t 5 so as to ensure that signal S is at the low level until time tw 0 e at which the electric potential at word line WL 0 is completely brought into the low level.

As shown in FIG. 22 , random data appearing in a memory cell can be read by starting a Read cycle after one cycle of data generation. Assuming the data generation cycle and the Read cycle as one set, random data can be generated in and read from all the memory cells by repeating one set for each of word lines WL 0 to WL(n−1).

In the first to fourth embodiments of the present invention and the modifications, the value of intermediate voltage Vdd/2 shall be obtained by dividing the difference between supply voltages Vdd and Vss by 2. The reason is that data appearing in a memory cell is determined by the magnitude correlation among the threshold voltages of the four MOS transistors constituting the inverters in the memory cell. For example, if intermediate voltage Vdd/2 is set at supply voltage Vdd, cell power line Vddp will be continuously fixed at supply voltage Vdd, and the gates of the four MOS transistors will also be maintained fixed at supply voltage Vdd even if the electric potential at cell power line Vssn drops. After all, data is determined by one of two n-type transistors being brought into the conducting state.

Moreover, setting intermediate voltage Vdd/2 at the value obtained by dividing the difference between supply voltages Vdd and Vss by 2 allows the electric potentials at the storage nodes in a memory cell to transition from intermediate voltage Vdd/2 to supply voltage Vdd or from intermediate voltage Vdd/2 to Vss at the earliest. Furthermore, although not set forth in the description of the present invention, it is assumed that a p-type transistor is formed in an N well. Thus, the N well and the source of the p-type transistor will be set at a common electric potential. Therefore, even if the electric potential at cell power line Vddp which is the electric potential at the source of the p-type transistor is controlled to rise/drop, no electric potential difference arises between the source of the p-type transistor and the N well.

A substrate for an n-type transistor is a p-type silicon substrate without using a special well, and is fixed at supply voltage Vss. With the present system in which the electric potential at the source of the n-type transistor connected to cell power line Vssn becomes higher than the electric potential at a silicon substrate, a junction withstand voltage is of concern. Therefore, as shown in the previous embodiments, the intermediate voltage is set at Vdd/2, so that the electric potential difference produced between the source and the substrate can be made relatively small.

In view of the above-described reason for setting the intermediate voltage, when the generation speed of data appearing at a storage node in a memory cell is not essential, the value of intermediate voltage Vdd/2 in the present embodiment is not limited to the value obtained by dividing the difference between supply voltages Vdd and Vss by 2. Moreover, the following are not restrictive conditions when appearing data is determined by one of a p-type transistor and an n-type transistor. However, for determining appearing data by the magnitude correlation among the threshold voltages of the four MOS transistors as described above, the following conditions are necessary.

It is preferable to set the intermediate voltage lower than threshold Vthp of a p-type transistor with reference to supply voltage Vdd and higher than threshold Vthn of an n-type transistor with reference to supply voltage Vss. The intermediate voltage in this case can be expressed as follows:

Vss+Vthn <intermediate voltage Vdd/ 2 <Vdd−|Vthp|

The value of intermediate voltage Vdd/2 adopted in the previous embodiments can be set by the resistance values of resistors R 1 , R 2 and R 3 in intermediate voltage generation circuit 110 shown in FIG. 2 .

In the first to fourth embodiments of the present invention and the modifications, identification information generation circuits 100 _ 1 to 100 _ 4 are described as having four memory macros ( 150 , 160 , 170 , and 180 shown in FIGS. 1 , 12 , 16 , and 20 ). However, the number of memory macros is not limited to four, and can be set at one or more according to necessity without affecting the object, functions and effects of the present invention.

In the first to fourth embodiments of the present invention and the modifications, a single circuit block is used for a plurality of memory macros in power supply control circuits 140 _ 1 , 140 _ 11 , 140 _ 12 , 140 _ 2 , and 140 _ 3 , however, a circuit block may be used for each of the plurality of memory macros. Furthermore, a power supply control circuit may be used for each memory macro.

Memory array 151 _ 4 according to the fourth embodiment of the present invention has bit line intermediate voltage supply circuit EQhvd connected to each bit line pair (BL, /BL). This bit line intermediate voltage supply circuit EQhvd can be arranged similarly in the other embodiments of the present invention and the modifications.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being interpreted by the terms of the appended claims.