Low voltage bandgap reference circuit

1. Field of the Invention

The present invention generally relates to a bandgap reference circuit, which can successfully operate with a low supply-voltage below 1.25V, and more specifically to a bandgap reference circuit having a single stable operating point to avoid startup failure.

2. The Prior Arts

General high performance electronic circuits greatly need a stable reference voltage without suffering from different variations caused by the power source, loading level or operating temperature. For example, the reference voltage can be used as an input signal of a comparator to compare with another internal or external signal. The reference voltage is often generated by a reference circuit with complicated structure so as to block all the inevitable variations due to the power source, loading or temperature.

In the prior arts, electronic manufacturers have successfully developed many reference circuits which can prevent the influence caused by the power source and loading level. Additionally, the variation of the temperature is blocked by using a differential operational amplifier as well as resistors and diodes to assemble a specific circuit having both the positive and negative temperature coefficients, and in particular, the positive and negative temperature coefficients are signed to almost the same in the magnitude such that the temperature effect is greatly reduced. Specifically, the first and second orders of the temperature coefficient for the reference circuit are almost zero.

Please refer to FIG. 1 . The bandgap reference circuit in the prior arts comprises a differential operational amplifier OP, a metal-oxide-semiconductor (MOS) P, a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a first diode D 1 and a second diode D 2 . The reference voltage Vref is generated at the drain terminal of the MOS P, and the second diode D 2 is implemented by several diodes connected in parallel and each identical to the first diode D 1 in electrical property.

More specifically, the bandgap reference circuit is configured such that the output end of the differential operational amplifier OP is connected to the gate terminal of the MOS P, the source terminal of the MOS P is connected to the power source Vcc, the first resistor R 1 is connected between the drain terminal of the MOS P and the positive end of the first diode D 1 , and the second resistor R 2 and the third resistor R 3 are connected in series between the drain terminal of the MOS P and the positive end of the second diode D 2 . Particularly, the positive end of the first diode D 1 is further connected to the inverting input end of the differential operational amplifier OP, and the connection point of the second resistor R 2 and the third resistor R 3 is further connected to the non-inverting input end of the differential operational amplifier OP, thereby providing a feedback control loop.

The detailed operation of the bandgap reference circuit in FIG. 1 will be described as follows.

First, the current of the diode in accordance with the current-voltage characteristic is illustrated by equation (1):

I = ⁢ Is · ( ⅇ q · Vf k · T - 1 ) ≅ ⁢ Is · ⅇ q · Vf k · T ⁢ VF >> k · T q , ( 1 )

where q is the electrical charge per electron (1.6×10 −19 C), K is the Boltzmann constant (1.38×10 −23 J/K), T is the absolute temperature, Is is the reverse saturation current, and Vf is the thermal voltage (26 mV at 25° C.). The thermal voltage Vf can be expressed by equation (2):

Therefore, when the differential operational amplifier OP is operated at a steady-state, the inverting input voltage Va is equal to the non-inverting input voltage Vb, that is I 1 ·R 1 =I 2 ·R 2 , and the first current I 1 and the second current I 2 flow through the first resistor R 1 and the second resistor R 2 , respectively. Thus, the following equations are obtained from equation (2):

Vf ⁢ ⁢ 1 = V T · In ⁡ ( I ⁢ ⁢ 1 I ⁢ ⁢ s ) Vf ⁢ ⁢ 2 = V T · In ⁡ ( I ⁢ ⁢ 2 N · Is )

and equation (3) results:

The reference voltage Vref shown in FIG. 1 can be expressed by equation (4):

Subsequently, equation (5) is resulted in by combining equations (3) and (4):

V ref = V f ⁢ ⁢ 1 + V T · ( R ⁢ ⁢ 2 R ⁢ ⁢ 3 ) · ln ⁡ ( N · R ⁢ ⁢ 2 R ⁢ ⁢ 1 ) . ( 5 )

V f1 in equation (5) is the built-in voltage, which has a negative temperature coefficient (−2.2 mV/° C.) and V T has a positive temperature coefficient (+0.085 mV/° C.). Further, equation (6) is derived by putting these parameters into equation (5):

Therefore, if the temperature coefficient of Vref(T) is zero, then

and equation (7) is thus obtained:

At this time, V f10 is about 0.6V, and V T0 is about 0.026V for the temperature 25° C., and equation (8) is derived from equations (6) and (7):

V ref=0.6+0.026·25.88=1.27  (8).

From the above-mentioned, the bandgap reference circuit shown in FIG. 1 generates the reference voltage, 1.27V, regardless of the first, second and third resistors. That is, the reference voltage may suffer some variation due to different semiconductor processes, but not much. For example, the reference voltage Vref possibly varies between 1.17V˜1.37V when V f10 is 0.5V˜0.7V.

However, one of the shortcomings of the bandgap reference circuit in the prior arts is that the bandgap reference circuit can not normally operate if the power source Vcc is less than the reference Vref, such as 1.27V, because the differential operational amplifier OP and the MOS P do not properly work.

For further illustration, please refer to another example in the prior arts as shown in FIG. 2 . Similar to the structure in FIG. 1 , the bandgap reference circuit in FIG. 2 generally comprises a differential operational amplifier OP, a first transistor P 1 , a second transistor P 2 , a third transistor P 3 , a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a fourth resistor R 4 , a first diode D 1 and a second diode D 2 . The second diode D 2 is implemented by several diodes connected in parallel and each identical to the first diode D 1 in electrical property.

Specifically, the output end of the differential operational amplifier OP is connected to the gate terminals of the first transistor P 1 , the second transistor P 2 and the third transistor P 3 , the source terminals of the a first transistor P 1 , the second transistor P 2 and the third transistor P 3 are connected to the power source Vcc. The positive end of the first diode D 1 and one end of the first resistor R 1 are connected to the drain terminal of the first transistor P 1 . One end of the second resistor R 2 and one end of the third resistor R 3 are connected to the drain terminal of the second transistor P 2 , the other end of the third resistor R 3 is connected to the positive end of the second diode D 2 , and one end of the fourth resistor R 4 is connected to the drain terminal of the third transistor P 3 . Furthermore, the other end of the first resistor R 1 , the negative end of the first diode D 1 , the negative end of the second diode D 2 , the other end of the second resistor R 2 and the other end of the fourth resistor R 4 are grounded.

Particularly, the drain terminal of the first transistor P 1 is further connected to the inverting input end of the differential operational amplifier OP, and the drain terminal of the second transistor P 2 is further connected to the non-inverting input end of the differential operational amplifier OP, thereby providing feedback control loop and the reference voltage Vref at the drain terminal of the third transistor P 3 .

Hereafter, the operation of the bandgap reference circuit in FIG. 2 will be described in detail.

Each of the transistors P 1 , P 2 and P 3 has identical electrical property such that the inverting input voltage Va is equal to the non-inverting input voltage Vb when the differential operational amplifier OP is operated at the steady state, that is, I 1 a =I 2 a and I 1 b =I 2 b , where the current I 1 a flows through the first diode D 1 , the current I 2 a flows through the third resistor R 3 , the current I 1 b flows through the first resistor R 1 , and the current I 2 b flows through the second resistor R 2 . Therefore, the following equation (9) is obtained:

And, the reference voltage Vref can be expressed as equation (10):

Moreover, equation (11) is thus derived from equations (4) and (8):

At this time, equation (11) is put into equation (10) to acquire the reference voltage Vref as shown by equation (12):

Therefore, the reference voltage Vref is changed by adjusting the ratio of R 4 /R 2 such that the bandgap reference circuit can still properly function at the power source Vcc less than 1.27V.

However, the shortcoming of the above bandgap reference circuit is that if R 1 =R 2 and Va and Vb do not attain the corresponding cut-in voltage Vth of the diodes D 1 and D 2 , respectively, at the beginning of starting, I 1 b >>I 1 a and I 2 b >>I 1 a such that Va is almost equal to Vb, and the differential operational amplifier OP does not normally work. Thus, start failure results. Another problem is that the bandgap reference circuit has more than one stable operating point, that is, several intersection points of the inverting input voltage Va and the non-inverting input voltage Vb, as shown in FIG. 3 . More specifically, the bandgap reference circuit can normally perform at the stable operating point A. But, the bandgap reference circuit fails at the multiple stable operating points B, that is, the points when the inverting input voltage Va and the non-inverting input voltage Vb are the same. This is because the bandgap reference circuit may perform at the stable operating points B before the inverting input voltage Va and the non-inverting input voltage Vb attain the corresponding cut-in voltage Vth of the diodes D 1 and D 2 , respectively. Consequently, the whole electrical function of the bandgap reference circuit fails.

Therefore, it is greatly needed for a low voltage bandgap reference circuit, which is able to adjust the reference voltage generated and has a single stable operating point less than the power source so as to avoid the start failure at low voltage, thereby solving the above problems of the bandgap reference circuit in the prior arts.

The primary objective of the present invention is to provide a low voltage bandgap reference circuit for operating at a low voltage and providing a stable reference voltage. The low voltage bandgap reference circuit comprises a positive temperature coefficient circuit unit generating a current with a positive temperature coefficient, a negative temperature coefficient circuit unit generating a current with a negative temperature coefficient, and a load unit through which the currents flow to generate the reference voltage, so as to avoid any influence of the variation of the operating temperature by appropriately cancelling the positive and negative temperature coefficients each other.

The positive temperature coefficient circuit unit comprises a first differential operational amplifier, a first transistor, a second transistor, a third transistor, a first resistor, a first diode and a second diode. The source terminals of the first, second and third transistors are connected to a power source. The gate terminals of the first, second and third transistors are in parallel connected to an output terminal of the first differential operational amplifier. A drain terminal of the first transistor is connected to a positive end of the first diode, a drain terminal of the second transistor is connected to one end of the first resistor, and the other end of the first resistor is connected to a positive end of the second diode. The negative ends of the first and second diodes are grounded.

The drain terminal of the first transistor is further connected to an inverting input end of the first differential operational amplifier, and the drain terminal of the second transistor is further connected to a non-inverting input end of the first differential operational amplifier.

The negative temperature coefficient circuit comprises a second differential operational amplifier, a fourth transistor, a fifth transistor, a sixth transistor, a second resistor and a third diode. The source terminals of the fourth, fifth and sixth transistors are connected to the power source. The gate terminals of the fourth, fifth and sixth transistors are in parallel connected to an output terminal of the second differential operational amplifier. The drain terminal of the fourth transistor is connected to a positive end of the third diode. A negative end of the third diode is grounded, a drain terminal of the fifth transistor is connected to one end of the second resistor, and the other end of the second resistor is grounded.

The drain terminal of the fourth transistor is further connected to an inverting input end of the second differential operational amplifier, and the drain terminal of the fifth transistor is further connected to a non-inverting input end of the second differential operational amplifier.

An end of the load unit is connected to a drain terminal of the third transistor and a drain terminal of the sixth transistor. Another end of the load unit is grounded. Preferably, the load unit can be simply implemented by a resistive load.

Additionally, the second diode is implemented by a plurality of diodes connected in parallel and each electrically identical to the first diode. The third diode has electrical property identical to the first diode. Each of the first differential operational amplifier and the second differential operational amplifier has identical electrical property. Further, the first, second, third, fourth, fifth and sixth transistors have identical electrical property.

Therefore, the positive temperature coefficient circuit unit uses the drain terminal of the third transistor to provide the current with the positive temperature coefficient flowing through the load unit, and simultaneously, the negative temperature coefficient circuit unit uses the drain terminal of the sixth transistor to provide the current with the negative temperature coefficient flowing through the load unit, such that the two ends of the load unit generate the reference voltage, which is less influenced by the temperature.

Another objective of the present invention is to provide a low voltage bandgap reference circuit by replacing the above diodes with the base-emitter junction of the bipolar transistors. That is, the first and second diodes in the positive temperature coefficient circuit unit are replaced with the first and second bipolar transistors, and the third diode in the negative temperature coefficient circuit unit are replaced with the third bipolar transistor. Specifically, the base and collector terminals of the first, second and third bipolar transistors are grounded, and the emitter terminals of the first, second and third bipolar transistors are connected in the same manner the positive ends of the above-mentioned first, second and third diodes.

Moreover, the second bipolar transistor can be preferably implemented by a plurality of bipolar transistors which are connected in parallel and have electrical property identical to the first bipolar transistor. The third bipolar transistor has electrical property identical to the first bipolar transistor.

Therefore, it is possible to provide the reference voltage at the low voltage, which suffers less negative effect by the temperature. In particular, the present invention has only one stable operating point such that the operating stability of the whole electrical property is secured, thereby successfully avoiding any malfunction due to the internal operational amplifiers.

The present invention can be understood in more detail by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein:

FIG. 1 is a view showing one bandgap reference circuit in the prior arts;

FIG. 2 is a view showing another bandgap reference circuit in the prior arts;

FIG. 3 is a view showing the waveform of the bandgap reference circuit in the prior arts;

FIG. 4 shows the first embodiment of the low voltage bandgap reference circuit according to the present invention;

FIG. 5 shows the second embodiment of the low voltage bandgap reference circuit according to the present invention; and

FIG. 6 shows the waveform of the low voltage bandgap reference circuit according to the present invention.

The present invention may be embodied in various forms and the details of the preferred embodiments of the present invention will be described in the subsequent content with reference to the accompanying drawings. The drawings (not to scale) show and depict only the preferred embodiments of the invention and shall not be considered as limitations to the scope of the present invention. Modifications of the shape of the present invention shall too be considered to be within the spirit of the present invention.

Please refer to FIG. 4 . As shown in FIG. 4 , the low voltage bandgap reference circuit according to the first embodiment of the present invention comprises a positive temperature coefficient circuit unit 10 , a negative temperature coefficient circuit unit 20 and a load unit 30 to provide a stable reference voltage Vref at the power source Vcc with a low voltage. The positive temperature coefficient circuit unit 10 provides a positive temperature coefficient current Iref 1 with the positive temperature coefficient, the negative temperature coefficient circuit unit 20 provides a negative temperature coefficient current Iref 2 with the negative temperature coefficient, and the positive and negative temperature coefficient currents Iref 1 and Iref 2 are combined and flow through the load unit 30 . Specifically, the positive and negative temperature coefficients are well designed to cancel each other, and the reference voltage Vref generated at the two ends of the load unit 30 has the net temperature coefficient of zero or almost zero.

More specifically, the positive temperature coefficient circuit unit 10 may comprise a first differential operational amplifier OP 1 , a first transistor P 1 , a second transistor P 2 , a third transistor P 3 , a first resistor R 1 , a first diode D 1 and a second diode D 2 . The positive temperature coefficient current Iref 1 is generated by the positive temperature coefficient circuit unit 10 . The source terminals of the first, second and third transistors P 1 ˜P 3 are connected to a power source Vcc. The gate terminals of the first, second and third transistors P 1 ˜P 3 are in parallel connected to an output terminal of the first differential operational amplifier OP 1 . A drain terminal of the first transistor P 1 is connected to a positive end of the first diode D 1 , a drain terminal of the second transistor P 2 is connected to one end of the first resistor R 1 , and the other end of the first resistor R 1 is connected to a positive end of the second diode D 2 . The negative ends of the first and second diodes D 1 and D 2 are grounded.

Furthermore, the drain terminal of the first transistor P 1 is connected to an inverting input end of the first differential operational amplifier OP 1 as a first inverting input voltage Va 1 , and the drain terminal of the second transistor P 2 is connected to a non-inverting input end of the first differential operational amplifier OP 1 as a first non-inverting input voltage Vb 1 .

The negative temperature coefficient circuit 20 may comprise a second differential operational amplifier OP 2 , a fourth transistor P 4 , a fifth transistor P 5 , a sixth transistor P 6 , a second resistor R 2 and a third diode D 3 . The negative temperature coefficient circuit 20 generates a negative temperature coefficient current Iref 2 . The source terminals of the fourth, fifth and sixth transistors P 4 ˜P 6 are connected to the power source Vcc. The gate terminals of the fourth, fifth and sixth transistors P 4 ˜P 6 are in parallel connected to an output terminal of the second differential operational amplifier OP 2 . The drain terminal of the fourth transistor P 4 is connected to a positive end of the third diode D 3 . A negative end of the third diode D 3 is grounded, a drain terminal of the fifth transistor P 5 is connected to one end of the second resistor R 2 , and the other end of the second resistor R 2 is grounded. The drain terminal of the fourth transistor P 4 is further connected to an inverting input end of the second differential operational amplifier OP 2 as a second inverting input voltage Va 2 , and the drain terminal of the fifth transistor P 5 is further connected to a non-inverting input end of the second differential operational amplifier OP 2 as a second non-inverting input voltage Vb 2 .

One end of the load unit 30 is connected to a drain terminal of the third transistor P 3 and a drain terminal of the sixth transistor R 6 . The other end of the load unit 30 is grounded. Specifically, the load unit 30 can be simply implemented by a resistive load.

Preferably, the second diode D 2 is implemented by a plurality of diodes connected in parallel and each electrically identical to the first diode D 1 , and the third diode D 3 has electrical property identical to the first diode D 1 . Each of the first second differential operational amplifiers OP 1 and OP 2 has identical electrical property. Further, the first, second, third, fourth, fifth and sixth transistors P 1 ˜P 6 have identical electrical property.

Therefore, the positive temperature coefficient circuit unit 10 uses the drain terminal of the third transistor P 3 to provide the positive temperature coefficient current Iref 1 and the negative temperature coefficient circuit unit 20 uses the drain terminal of the sixth transistor P 6 to provide the negative temperature coefficient current Iref 2 such that the positive and negative temperature coefficient current Iref 1 and Iref 2 flow through the load unit 30 and the two ends of the load unit 30 generate the reference voltage Vref, which is less influenced by the temperature.

Hereafter, the electrical operation of the low voltage bandgap reference circuit according to the first embodiment of the present invention will be described in detail with reference to FIG. 4 . For clear explanation, the load unit 30 is implemented by the resistive load REL.

First, when the first and second differential operational amplifier OP 1 and OP 2 operate at a steady-state, the first inverting input voltage Va 1 is less than the first non-inverting input voltage Vb 1 , and the second inverting input voltage Va 2 is less than the second non-inverting input voltage Vb 2 . Thus, the current Ia 1 flowing through the drain terminal of the first transistor P 1 , the current Ib 1 flowing through the drain terminal of the second transistor P 2 , the positive temperature coefficient current Iref 1 flowing through the drain terminal of the third transistor P 3 , the current Ia 2 flowing through the drain terminal of the fourth transistor P 4 , the current Ib 2 flowing through the drain terminal of the fifth transistor P 5 , and the negative temperature coefficient current Iref 2 flowing through the drain terminal of the sixth transistor P 6 are the same in magnitude.

The reference voltage Vref can be expressed by the following equations (13) and (14):

The equation (15) is further derived by combining equations (4) and (5):

Finally, the reference voltage Vref shown in equation (16) is acquired by combining equations (14) and (15):

It is apparently from equation (16) that the reference voltage Vref can be adjusted by changing the resistive load RL and the second resistor R 2 . That is, the reference voltage Vref is independent of the absolute values of the resistive load RL and the second resistor R 2 . More particularly, for the present semiconductor processes, the ratio of the resistance values of the two resistors can be easily controlled to a considerable small value with high precision. Therefore, the precision of the reference voltage Vref is greatly improved.

Please further refer to FIG. 5 . The low voltage bandgap reference circuit shown in FIG. 5 according to the second embodiment of the present invention is similar to the first embodiment mentioned in FIG. 4 . The low voltage bandgap reference circuit of the second embodiment provides a stable reference voltage Vref at the power source Vcc with a low voltage, and comprises the positive temperature coefficient circuit unit 11 , the negative temperature coefficient circuit unit 21 and the load unit 30 . The positive temperature coefficient current Iref 1 provided by the positive temperature coefficient circuit unit 11 and the negative temperature coefficient current Iref 2 provided by the negative temperature coefficient circuit unit 21 are combined and flow through the load unit 30 to generate the reference voltage Vref at the load unit 30 , which has the net temperature coefficient of zero or almost zero.

Specifically, the positive temperature coefficient circuit unit 11 comprises the first differential operational amplifier OP 1 , the first transistor P 1 , the second transistor P 2 , the third transistor P 3 , the first resistor R 1 , the first bipolar transistor Q 1 and the second bipolar transistor Q 2 to generate the positive temperature coefficient current Iref 1 . Similarly, the negative temperature coefficient circuit 21 comprises the second differential operational amplifier OP 2 , the fourth transistor P 4 , the fifth transistor P 5 , the sixth transistor P 6 , the second resistor R 2 and the third bipolar transistor Q 3 to generate the negative temperature coefficient current Iref 2 .

It should be noted that the primary difference between the first and second embodiments is that the positive temperature coefficient circuit unit 11 of the second embodiment uses the first bipolar transistor Q 1 and the second bipolar transistor Q 2 to replace the first diode D 1 and the second diode D 2 in the first embodiment, and simultaneously, the negative temperature coefficient circuit 21 uses the third bipolar transistor Q 3 to replace the third diode D 3 in the first embodiment. Other components are the same, and the detailed description is thus emitted.

It is preferred that the first, second and third bipolar transistors Q 1 ˜Q 3 are implemented by PNP bipolar transistors, and the third bipolar transistor Q 3 is identical to the first bipolar transistor Q 1 . In particular, the base and collector terminals of the first, second and third bipolar transistors Q 1 ˜Q 3 are shorted-circuit and grounded. That is, the base-collector junction of the PNP bipolar transistor is used as a diode. Additionally, the electrical operation of the first, second and third bipolar transistors Q 1 ˜Q 3 is the same as that of the first, second and third diodes D 1 ˜D 3 . Thus, it is omitted hereafter.

It can be seen from equation (16) that the low voltage bandgap reference circuit of the second embodiment generates the reference voltage, which can be increased by a magnifying factor simply by changing the ratio of the resistances of the load unit and the second resistor, thereby acquiring the reference voltage Vref by multiplying the magnifying factor and 1.27V.

For further description of the key features of the low voltage bandgap of the present invention, please refer to FIG. 6 showing the waveform of the low voltage bandgap reference circuit. It should be noted that the waveform is applicable to the first and second embodiments. As shown in FIG. 6 , the low voltage bandgap of the present invention has only one stable operating point C, that is, the point at which the first inverting voltage Va 1 , the first non-inverting voltage Vb 1 , the second inverting voltage Va 2 and the second non-inverting voltage Vb 2 coincide. For example, the stable operating point C is 0.76V, less than 1.27V. Thus, the low voltage bandgap reference circuit of the present invention can normally operate at the power source Vcc less than 1.27V to provide the reference voltage Vref as desired so as to avoid the traditional problem caused by the internal operational amplifier not correctly starting and functioning at low voltage. Therefore, the demand of the low voltage bandgap reference circuit operable at the low voltage power source in modern electric devices is well fulfilled.

Although the present invention has been described with reference to the preferred embodiments, it will be understood that the invention is not limited to the details described thereof Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.