Inventor
Chung-Cheng Wu
Inventor
Hsinchu County, TW
Overview
Patents· 70 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices32%
H01LSemiconductor devices16%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H10BElectronic memory devices8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
B82YSpecific uses or applications of nanostructures2%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%
G05FSystems for regulating electric or magnetic variables1%
H03KPulse technique1%
PatentTitleYear
10,871,647Apparatus and method for prevention of contamination on collector of extreme ultraviolet light source202010,790,280Multi-gate device and method of fabrication thereof202010,734,500Horizontal gate all-around device having wrapped-around source and drain202010,672,742Semiconductor device and manufacturing method thereof202010,644,1682-D material transistor with vertical structure202010,535,655Integrated circuits and manufacturing methods thereof202010,535,680Integrated circuit structure and method with hybrid orientation for FinFET202010,510,866Semiconductor structure and fabrication method thereof201910,497,792Contacts for highly scaled transistors201910,438,851Threshold voltage adjustment for a gate-all-around semiconductor structure201910,290,546Threshold voltage adjustment for a gate-all-around semiconductor structure201910,134,9152-D material transistor with vertical structure201810,109,721Horizontal gate-all-around device having wrapped-around source and drain201810,096,597Re-grown gate structure and fabrication method thereof201810,008,603Multi-gate device and method of fabrication thereof20189,997,615Method for forming semiconductor structure with epitaxial growth structure20189,960,273Integrated circuit structure with substrate isolation and un-doped channel20189,941,374Contacts for highly scaled transistors20189,899,387'Multi-gate device and method of fabrication thereof'20189,754,840'Horizontal gate-all-around device having wrapped-around source and drain'20179,620,422'Semiconductor arrangement'20179,508,858'Contacts for highly scaled transistors'20169,385,213'Integrated circuits and manufacturing methods thereof'20169,356,020'Semiconductor arrangement'20169,312,260'Integrated circuits and manufacturing methods thereof'20169,018,934'Low voltage bandgap reference circuit'20158,951,875'Semiconductor structure'20158,759,943'Transistor having notched fin structure and method of making the same'20148,362,573'Integrated circuits and manufacturing methods thereof'20138,357,579'Methods of forming integrated circuits'20138,324,668'Dummy structure for isolating devices in integrated circuits'20128,278,179'LDD epitaxy for FinFETs'20127,855,586'Frequency jitter generator and PWM controller'20107,749,911'Method for forming an improved T-shaped gate structure'20107,399,679'Narrow width effect improvement with photoresist plug process and STI corner ion implantation'20087,378,889'Pulse width modulation device with a power saving mode controlled by an output voltage feedback hysteresis circuit'20087,256,569'Apparatus and method for continuous conduction mode boost voltage power factor correction with an average current control mode'20077,187,046'Method of forming an N channel and P channel finfet device on the same semiconductor substrate'20077,173,404'Auto-switching converter with PWM and PFM selection'20077,109,692'High-speed PWM control apparatus for power converters with adaptive voltage position and its driving signal generating method'20067,071,515'Narrow width effect improvement with photoresist plug process and STI corner ion implantation'20067,047,348'Method and architecture for accessing hardware devices in computer system and chipset thereof'20066,914,299'Horizontal surrounding gate MOSFETs'20056,789,564'Hose reel'20046,777,280'Method for fabricating an integrated circuit with a transistor electrode'20046,776,177'Gardening protective shelter in umbrella shape'20046,770,516'Method of forming an N channel and P channel FINFET device on the same semiconductor substrate'20046,583,014'Horizontal surrounding gate MOSFETS'20036,569,729'Method of fabricating three dimensional CMOSFET devices for an embedded DRAM application'20036,548,363'Method to reduce the gate induced drain leakage current in CMOS devices'20036,406,953'Method for fabricating an integrated circuit with a transistor electrode'20026,284,579'Drain leakage reduction by indium transient enchanced diffusion (TED) for low power applications'20016,248,673'Hydrogen thermal annealing method for stabilizing microelectronic devices'20016,175,394'Capacitively coupled field effect transistors for electrostatic discharge protection in flat panel displays'20016,164,562'Rotary type swingable sprayer'20006,144,059'Process and structure for increasing capacitance of stack capacitor'20006,133,597'Biasing an integrated circuit well with a transistor electrode'20006,069,052'Process and structure for increasing capacitance of stack capacitor'20006,063,548'Method for making DRAM using a single photoresist masking step for making capacitors with node contacts'20006,033,963'Method of forming a metal gate for CMOS devices using a replacement gate process'20005,920,780'Method of forming a self aligned contact (SAC) window'19995,895,945'Single polysilicon neuron MOSFET'19995,726,086'Method of making self-aligned cylindrical capacitor structure of stack DRAMS'19985,650,346'Method of forming MOSFET devices with buried bitline capacitors'19975,633,520'Neuron MOSFET with different interpolysilicon oxide'19975,554,545'Method of forming neuron mosfet with different interpolysilicon oxide thickness'19965,541,876'Memory cell fabricated by floating gate structure'19965,444,411'Functional MOS transistor with gate-level weighted sum and threshold operations'19955,436,190'Method for fabricating semiconductor device isolation using double oxide spacers'19955,350,700'Method of fabricating bipolar transistors with buried collector region'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2001Based in I-Lan, TW· patent location history
1995–1999Patents assigned to UNITED MICROELECTRONICS CORP (7)· patent assignee history
1995–2004Based in Tu-Cheng, TW· patent location history
1998–2004Patents assigned to MOSEL VITELIC INC (6)· patent assignee history
1999–2015Based in Hsinchu, TW· patent location history
2000–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (22)· patent assignee history
2012–2016Patents assigned to WU CHUNG-CHENG (6)· patent assignee history
2013–2020Based in Jubei, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (22)· patent assignee history
2016–2020Based in Hsinchu County, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 22 | 2000–2016 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 22 | 2016–2020 |
| UNITED MICROELECTRONICS CORP | 7 | 1995–1999 |
| MOSEL VITELIC INC | 6 | 1998–2004 |
| WU CHUNG-CHENGself | 6 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu County, TW | 19 | 2016–2020 |
| Hsinchu, TW | 12 | 1999–2015 |
| I-Lan, TW | 11 | 1994–2001 |
| Jubei, TW | 9 | 2013–2020 |
| Tu-Cheng, TW | 7 | 1995–2004 |