Flip-flop array with option to ignore control signals

This invention relates generally to configurable flip-flop arrays for integrated circuits.

Integrated circuits often include vast arrays of logic gates. Dedicated integrated circuits (ICs) may provide the smallest chip-size for various applications. For instance, only the minimum number of required gates, interconnects and other components are required according to the design. However, for many small volume operations or for testing of various circuit designs, the fabrication of dedicated integrated circuits may be too costly as well as too time consuming. As an alternative, various programmable integrated circuit (ICs), such as field-programmable gate arrays (FPGAs), are popular for testing designs and for lower volume device production, as well as for providing flexibility to configure and reconfigure embedded components. Within programmable ICs such as FPGAs, components may be grouped into various blocks or logic units, such as configurable logic blocks (CLBs) and/or slices. For example, each slice may contain a number of look-up tables (LUTs), flip-flops, storage elements, carry logic elements, and so forth, and each configurable logic block may be composed of several slices.

The present disclosure provides an integrated circuit including a first group of flip-flops and a second group of flip-flops. The flip-flops in the first group and the flip-flops in the second group share a common reset signal. The integrated circuit further includes a first selection unit for selecting a first output from among the common reset signal and a logical low signal to be sent to the second group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the second group.

In various embodiments: the first selection unit is further for selecting the first output based upon a reset ignore signal; the first group and the second group comprise a same number of flip-flops; the flip-flops in the first group share a first common clock enable signal and the flip-flops in the second group share a second common clock enable signal; the flip-flops in the first group and the flip-flops in the second group share a common clock enable signal; the flip-flops in the first group and the flip-flops in the second group share a common clock signal; a second selection unit is for selecting a second output from among the common reset signal and a logical low signal to be sent to the first group of flop-flops, wherein a selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the first group; the integrated circuit further comprises a plurality of look-up tables; each of the flip-flops in the first group and each of the flip-flops in the second group has at least one input port for receiving at least one input from at least one of the plurality of look-up tables; the integrated circuit further comprises a configuration memory; the first selection unit is further for selecting the first output based upon a reset ignore signal stored in the configuration memory; the first group and the second group comprise components of a slice of the integrated circuit; and the integrated circuit is a field-programmable gate array.

The present disclosure also provides a further integrated circuit including a first group of flip-flops and a second group of flip-flops. The flip-flops in the first group and the flip-flops in the second group share a common clock enable signal. The integrated circuit further includes a first selection unit for selecting a first output from among the common clock enable signal and a logical high signal to be sent to the second group of flip-flops. A selection of the logical high signal is for preventing the common clock enable signal from being applied to the flip-flops in the second group.

In various embodiments: the first selection unit is further for selecting the first output based upon a clock enable ignore signal; the flip-flops in the first group share a first common reset signal and the flip-flops in the second group share a second common reset signal; the flip-flops in the first group and the flip-flops in the second group share a common reset signal; the flip-flops in the first group and the flip-flops in the second group share a common clock signal; and a second selection unit is for selecting a second output from among the common clock enable signal and a logical high signal to be sent to the first group of flop-flops, wherein a selection of the logical high signal is for preventing the common clock enable signal from being applied to the flip-flops in the first group.

Still another integrated circuit is disclosed that comprises a first group of flip-flops, a second group of flip-flops, and a selection unit. The selection unit is controllable to disable one of a clock enable signal or a reset signal to the second group of flip-flops. The clock enable signal or the reset signal is shared by the first group of flip-flops or the second group of flip-flops.

The accompanying drawings show exemplary circuits and methods in accordance with one or more aspects of the disclosure; however, the accompanying drawings should not be taken to limit the disclosure to the examples shown, but are for explanation and understanding only.

FIG. 1 illustrates a block diagram of an integrated circuit;

FIG. 2 illustrates a block diagram of an additional integrated circuit;

FIG. 3 illustrates a block diagram of a method for managing, operating and/or programming an integrated circuit; and

FIG. 4 illustrates a high level block diagram of a general purpose computer or a computing device suitable for use in performing the functions described herein.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.

The present disclosure relates generally to devices having certain groups of flip-flops that are configurable to ignore control signals and methods for manufacturing such devices. For example, one or more groups of flip-flops may have an option to ignore one or more control signals, while the control signals are shared by a larger set of flip-flops. In one example, the present disclosure can be implemented within an integrated circuit (IC), e.g., a programmable IC, a programmable logic device (PLD), a dedicated IC, a field programmable gate array (FPGA), and the like.

FIG. 1 illustrates an exemplary circuit 100 . For example, circuit 100 may comprise a portion of a dedicated IC, a FPGA slice, and so forth. In one instance, circuit 100 includes a number of groups of flip-flops, e.g., D flip-flops. Circuit 100 includes four groups 110 A, 120 A, 110 B and 120 B. However, in other instances, more or less groups of flip-flops may be provided. In one embodiment, one or more of the groups may be configured as latches. For example, flip-flop 121 A may continue to function as a D flip-flop while flip-flop 111 A may instead be configured to function as a latch. In one example, the flip-flops in each of the groups may comprise positive or negative edge triggered flip-flops. In another example, the flip-flops in each of the groups may comprise different types of flip-flops, e.g., J-K flip-flops, SR flip-flops, or other types of flip-flops.

As shown in FIG. 1 , the groups are further organized into larger sets “A” and “B”. In one instance, sets “A” and “B” have independent clock signals. For example, groups 110 A and 120 A in set “A” share clock 1 (CLK 1 ), while groups 110 B and 120 B in set “B” share clock 2 (CLK 2 ). Within each of the groups are a number of flip-flops. In FIG. 1 , each group has four flip-flops. For example, group 110 A includes flip-flops 111 A- 111 D, group 120 A includes flip-flops 121 A- 121 D, group 110 B includes flip-flops 111 E- 111 H, and group 120 B includes flip-flops 121 E- 121 H. In some cases, more or less flop-flops may be included within each group. In addition, each of the groups includes a same number of flip-flops or may have different numbers of flip-flops.

Each flip-flop has a number of inputs for control signals as well as for data input and data output signals. For example, flip-flop 111 A includes a data port (D) for receiving incoming data, a clock port (CK) for receiving a clock signal, a clock enable (CE) port for receiving a clock enable signal, a reset port (R) for receiving a reset signal, a bypass input port (B) for receiving bypass input data, and an output port (Q) for a data output. In one example, the circuit 100 may also includes a plurality of look-up tables (LUTs) connected to a respective plurality of flip-flop data input ports (D) for providing input data.

Turning to set A as an example, both groups 110 A and 120 A share a common clock signal CLK 1 . It should be noted that as described herein, the sharing of a signal means that one or more devices/components are coupled to a common signal source. For instance, each of the flip-flops 111 A- 111 D in group 110 A and flip-flops 121 A- 121 D in group 120 A may be coupled by way of traces, vias, or similar connections to a source of the common clock signal CLK 1 . In addition, as shown in FIG. 1 , the flop-flops 111 A- 111 D in group 110 A share a common clock enable signal (CE 1 ), while the flip-flops 121 A- 121 D in group 120 A share a different clock enable signal (CE 2 ). Alternatively, groups 110 A and 120 A may both share a single clock enable signal. As also shown in FIG. 1 , flip-flops 111 A- 111 D in group 110 A can be controlled by a common reset signal (RST 1 ). In addition, flip-flops 121 A- 121 D in group 120 A may also be controlled by RST 1 . Thus, flip-flops 121 A- 121 D also share the common reset signal (RST 1 ). However, group 120 A may also be configured, or programmed to ignore the RST 1 signal. In particular, for group 120 A, circuit 100 further comprises a selection unit 125 A, e.g., a multiplexer for selecting among RST 1 and a logical low, or ground signal. For example, a configuration or management signal “reset ignore” (RST 1 _IGNORE 1 ) provides a signal to the selection unit 125 A to choose which of the two inputs to pass as an output R 3 . For instance, if RST 1 _IGNORE 1 is a logical low, e.g., a zero “0”, then the selection unit 125 A may select RST 1 . On the other hand, if RST 1 _IGNORE 1 is a logical high, e.g., a one “1”, then the ground signal, which may comprise a logical low signal, e.g., a zero “0”, will be selected by the selection unit 125 A. The output R 3 of selection unit 125 A is thus provided as an input to the respective reset (R) port of flip-flops 121 A- 121 D.

In one example, both of groups 110 A and 120 A are configurable, or programmable to ignore RST 1 . For instance, another selection unit 115 A may have a configuration or management signal RST 1 _IGNORE 2 which causes the selection unit 115 A to choose from among RST 1 and a logical low signal to provide output R 4 . In this way, even greater flexibility is provided where both of groups 110 A and 120 A may be separately configurable, or programmable to ignore the control signal RST 1 .

Turning to set B, groups 110 B and 120 B are similar to groups 110 A and 120 A, but have a different clock signal (CLK 2 ). As shown in FIG. 1 , flip-flops 111 E- 111 H in group 110 B share a common clock enable signal (CE 3 ), while flip-flops 121 E- 121 H in group 120 B share a different common clock enable (CE 4 ). Alternatively, groups 110 B and 120 B may both share a single clock enable signal. As also shown in FIG. 1 , flip-flops 111 E- 111 H in group 110 B share a common reset signal (RST 2 ). In addition, flip-flops 121 E- 121 H in group 120 B may also be controlled by RST 2 . Thus, flip-flops 121 E- 121 H also share the common reset signal (RST 2 ). However, group 120 B may also be configured, or programmed to ignore, block and/or disable the RST 2 signal. In particular, for group 120 B, circuit 100 further comprises a selection unit 125 B, e.g., a multiplexer for selecting among RST 2 and a logical low, or ground signal to provide output R 1 . Notably, selection unit 125 B may have the same or similar functions to selection units 115 A and 125 A described above. For example, a configuration or management signal “reset ignore” (RST 2 _IGNORE 1 ) provides a signal to the selection unit 125 B to choose which of the two inputs to pass as an output R 1 . For instance, if RST 2 _IGNORE 1 is a logical low, e.g., a zero “0”, then the selection unit 125 B may select RST 2 . On the other hand if RST 2 _IGNORE 1 is a logical high, e.g., a one “1”, then the ground signal, which may comprise a logical low signal, e.g., a zero “0”, will be selected by the selection unit 125 B. The output of selection unit 125 B thus is provided as the input to the respective reset (R) port of flip-flops 121 E- 121 H.

In one example, both of groups 110 B and 120 B are configurable, or programmable to ignore RST 2 . For example, another selection unit 1158 may have a configuration or management signal RST 2 _IGNORE 2 which causes the selection unit 1158 to choose from among RST 2 and a logical low signal to provide output R 2 . In this way, even greater flexibility is provided where both of groups 110 B and 120 B may be separately configurable, or programmable to ignore the control signal RST 2 .

Circuit 100 may also include a configuration memory to store instructions for the use of one or more reset ignore signals (e.g., RST 1 _IGNORE 1 , RST 1 _IGNORE 2 , RST 2 _IGNORE 1 and RST 2 _IGNORE 2 ). For example, circuit 100 may comprise a component of a programmable IC. Upon initialization, the programmable IC may load instructions from a configuration memory to program a large number of components within the IC. Thus, for example, RST 1 _IGNORE 1 may be implemented via an instruction from a configuration memory to determine whether or not, during operation, flip-flops 121 A- 121 D should respond to, or should ignore the RST 1 signal.

In some cases, flip-flops in one or more of the groups are configured or programmed for a pipelining operation. For instance, many applications simply require one or more flip-flops to follow a previous flip-flop, without the need for any control signal. Accordingly, any one or more of groups 110 A, 120 A, 110 B and 120 B may be programmed (e.g., through a reset ignore signal) such that flip-flops in the group can be used for pipelining. For instance, each of the flip-flops in the group may receive a data input from the data input port (D) or the bypass input port (B) and operate without the use of the reset signal.

By allowing certain groups of flip-flops from a larger set of flip-flops to ignore, block and/or disable a control signal, e.g., the reset signal or the clock enable signal, circuit 100 provides a level of control granularity that provides for advantageous use of circuit resources, while at the same time economizing circuit space, cost and ease of production. For instance, to provide full flexibility (e.g., each flip-flop individually controllable with unique control signals as compared to the other flip-flops) requires a large amount of circuit space. For example, many separate control lines may be necessary, potentially leading to a larger circuit and a higher cost. On the other extreme, the circuit may also be designed such that all flip-flops must share the same control signals. However, if the logic design of a program requires flip-flops with different control signals, then flip-flops within the same circuit cannot be used. Rather, one or more additional circuits are required having different flip-flops that can be controlled with different control signals. In other words, many flip-flops from the first circuit may be wasted. In contrast, the present disclosure provides an optimal balance between function and economy by providing the option for only a portion (broadly a subset) of the flip-flops in a circuit to ignore a control signal (e.g., a reset signal).

FIG. 2 illustrates another exemplary circuit 200 . In the previous example of FIG. 1 , different groups of flip-flops are configurable, or programmable to ignore reset signals, e.g., RST 1 and RST 2 . As shown in FIG. 2 , different groups of flip-flops are programmable to ignore clock enable signals. For example, circuit 200 may comprise a FPGA slice, a portion of a dedicated IC, and so forth. As shown in FIG. 2 , circuit 200 includes a number of groups of flip-flops, e.g., D flip-flops. Circuit 200 includes four groups 210 A, 220 A, 210 B and 220 B. However, more or less groups of flip-flops may be provided. In addition, one or more of the groups may be configured as latches. For example, flip-flop 221 A may continue to function as a D flip-flop while flip-flop 211 A may instead be configured to function as a latch. The flip-flops in each of the groups may comprise positive or negative edge triggered flip-flops. Similarly, the flip-flops in each of the groups may comprise different types of flip-flops, e.g., J-K flip-flops, SR flip-flops, or other types of flip-flops.

The groups are further organized into larger sets “A” and “B”. As shown in FIG. 2 , sets “A” and “B” have independent clock signals. For example, groups 210 A and 220 A in set “A” share clock 1 (CLK 1 ), while groups 210 B and 220 B in set “B” share clock 2 (CLK 2 ). Within each of the groups are a number of flip-flops. In FIG. 2 , each group has four flip-flops. For instance, group 210 A includes flip-flops 211 A- 211 D, group 220 A includes flip-flops 221 A- 221 D, group 210 B includes flip-flops 211 E- 211 H, and group 220 B includes flip-flops 221 E- 221 H. More or less flop-flops may be included within each group. In addition, each of the groups may include a same number of flip-flops or different groups may have different numbers of flip-flops.

Turning to set A as an example, both groups 210 A and 220 A share a common clock signal CLK 1 . As shown in FIG. 2 , the flip-flops 211 A- 211 D and 221 A- 221 D in groups 210 A and 220 A, respectively share a single common reset signal (RST 1 ). However, in another example, each of the flop-flops 211 A- 211 D in group 210 A share a common reset signal, while each of the flip-flops 221 A- 221 D in group 220 A share a different common reset signal. As also shown in FIG. 2 , flip-flops 211 A- 211 D in group 210 A share a common clock enable signal (CE 1 ). In addition, flip-flops 221 A- 221 D in group 220 A may also be controlled by CE 1 . Thus, flip-flops 221 A- 221 D also share the common clock enable signal (CE 1 ). However, group 220 A may also be configured, or programmed to ignore the CE 1 signal. In particular, for group 220 A, circuit 200 further comprises a selection unit 225 A, e.g., a multiplexer for selecting among CE 1 and a logical high signal to provide an output C 3 . For example, a configuration or management signal for “clock enable ignore”, (CE 1 _IGNORE 1 ), provides a signal to the selection unit 225 A to choose which of the two inputs to pass as an output C 3 . For instance, if CE 1 _IGNORE 1 is a logical low, e.g., a zero “0”, then the selection unit 225 A may select CE 1 . On the other hand, if CE 1 _IGNORE 1 is a logical high, e.g., a one “1”, then the high signal, which may comprise a logical one “1”, will be selected by the selection unit 225 A. The output of selection unit 225 A thus is provided as the input to the respective clock enable (CE) port of flip-flops 221 A- 221 D.

In one example, both of groups 210 A and 220 A are configurable, or programmable to ignore CE 1 . For instance, another selection unit 215 A may have a configuration or management signal CE 1 _IGNORE 2 which causes the selection unit 215 A to choose from among CE 1 and a logical high signal to provide the output C 4 . In this way, even greater flexibility is provided where both of groups 210 A and 220 A may be separately configurable, or programmable to ignore the control signal CE 1 .

Turning to set B, groups 210 B and 220 B are similar to groups 210 A and 220 A, but have a different clock signal (CLK 2 ). As shown in FIG. 2 , the flip-flops 211 E- 211 H and 221 E- 221 H in groups 210 B and 220 B, respectively share a single common reset signal (RST 2 ). However, in another example the flop-flops 211 E- 211 H in group 210 B may share a common reset signal, while the flip-flops 221 E- 221 H in group 220 B share a different common reset signal. As also shown in FIG. 2 , flip-flops 211 E- 211 H in group 210 B share a common clock enable signal (CE 2 ). In addition, flip-flops 221 E- 221 H in group 220 B may also be controlled by CE 2 . Thus, flip-flops 221 E- 221 H also share the common clock enable signal (CE 2 ). However, group 220 B may also be configured, or programmed to ignore the CE 2 signal. In particular, for group 220 B, circuit 200 further comprises a selection unit 225 B, e.g., a multiplexer for selecting among CE 2 and a logical high signal to provide the output C 1 . Notably, selection unit 225 B may have the same or similar functions to selection units 215 A and 225 A described above. For example, another configuration or management signal for “clock enable ignore”, (CE 2 _IGNORE 1 ), provides a signal to the selection unit 225 B to choose which of the two inputs to pass as an output. For instance, if CE 2 _IGNORE 1 is a logical low, e.g., a zero “0”, then the selection unit 225 B may select CE 2 . On the other hand, if RST 2 _IGNORE 1 is a logical high, e.g., a one “1”, then the logical high signal, e.g., a one “1”, will be selected by the selection unit 225 B. The output of selection unit 225 B thus is provided as the input to the respective clock enable (CE) port of flip-flops 221 E- 221 H.

In one example, both of groups 210 B and 220 B are configurable, or programmable to ignore CE 2 . For instance, another selection unit 215 B may have a configuration or management signal CE 2 _IGNORE 2 which causes the selection unit 215 B to choose from among CE 2 and a logical high signal to provide the output C 2 . In this way, even greater flexibility is provided where both of groups 210 B and 220 B may be separately configurable, or programmable to ignore the control signal CE 2 .

Circuit 200 may also comprise a configuration memory to store instructions as to the use of one or more clock enable ignore signals (e.g., CE 1 _IGNORE 1 , CE 1 _IGNORE 2 , CE 2 _IGNORE 1 and CE 2 _IGNORE 2 ). For example, circuit 200 may comprise a component of a programmable IC. Upon initialization, the programmable IC may load instructions from a configuration memory to program a large number of components within the IC. Thus, for example, CE 1 _IGNORE 1 may be implemented via an instruction from a configuration memory to determine whether or not, during operation, flip-flops 221 A- 221 D should respond to, or should ignore, block and/or disable the CE 1 signal.

In some cases, flip-flops in one or more of the groups are configured or programmed for a pipelining operation, e.g., through a clock enable ignore signal. For instance, each of the flip-flops in a group may receive a data input from the data input port (D) or the bypass input port (B) and operate without the use of a clock enable signal.

FIG. 3 illustrates a block diagram of a method 400 for managing, operating and/or programming an integrated circuit. For example, method 300 can be performed by a circuit/device according to any one or more of the above described circuits. In one example, a computer-readable medium according to the present disclosure stores a series of instructions which cause a programmable device, or circuit to be programmed to perform the steps, functions operations of the method 300 . The method starts in step 305 and proceeds to step 310 .

In step 310 , a circuit receives at least one flip-flop control signal. For example, the circuit may receive a clock enable signal and/or a reset signal. At step 310 , the circuit may further receive an additional control signal, e.g., at least one clock signal. In a different example, the circuit receives two clock signals.

At optional step 320 , the circuit forwards at least one of the flip-flop control signals to a first group of flip-flops and to a second group of flip-flops. For example, the method may forward the clock enable signal to both the first and second group of flip-flops. In another example, the circuit forwards the reset signal to both the first and second group of flip-flops.

At step 330 , the circuit forwards at least a second of the flip-flop control signals to the first group of flip-flops. For example, if at step 320 , the circuit forwards the clock enable signal to both the first and second group of flip-flops, then at step 330 , the circuit forwards the reset signal only to the first group of flip-flops. Similarly, if at step 320 , the circuit forwards the reset signal to both the first and second group of flip-flops, then at step 330 , the circuit forwards the clock enable signal only to the first group of flip-flops. In cases where step 320 is omitted, step 330 may comprise either forwarding the clock enable signal or forwarding the reset signal.

At step 340 , the circuit receives a management signal, e.g., an ignore signal that indicates whether or not a control signal should be ignored for the second group of flop-flops. For instance, the circuit may receive an instruction from a configuration memory that indicates whether the second of the flip-flop control signals should be ignored or blocked to the second group of flip-flops.

At step 350 , the circuit determines whether or not the second of the flip-flop control signals should be ignored. For example, if the ignore signal comprises a zero, then the circuit may determine to not block, or to allow the second control signal to reach the second group of flop-flops. In this case, following step 350 the method proceeds to step 360 . On the other hand, if the ignore signal comprises a one, then the circuit determines to block or to disallow the second control signal from reaching the second group of flop-flops. In this case, following step 350 the method proceeds to step 370 . In one embodiment, step 350 is performed via a selection unit of the circuit, e.g., a multiplexer.

At step 360 , the circuit forwards the second flip-flop control signal to the second group of flip-flops. For example, for a particular circuit application, it may be desirable for flip-flops in both the first group and the second group to share both the first and second control signals.

On the other hand, if the ignore signal is determined to be valid, e.g., is a one, at step 350 , then the method proceeds from step 350 to step 370 . At step 370 , the circuit forwards a persistent logical high or logical low to the second group of flip-flops instead of the second flip-flop control signal. For example, if the second flip-flop control signal comprises a clock enable signal, the circuit may forward the logical high signal. On the other hand, when the second control signal comprises a reset signal, the method forwards the logical low signal. For example, the logical low signal may be provided by a connection to ground and the logical high signal may be provided by a connection to an on-chip or off-chip voltage source. In one embodiment, step 370 is performed via a selection unit of the circuit, e.g., a multiplexer.

Following step 360 or step 370 , the method proceeds to step 395 where the method ends. Advantageously, the present method 300 provides for selectively ignoring/blocking or allowing a control signal for a selected group of flip-flops within a set of flip-flops. By providing for certain groups of flip-flops from a larger set of flip-flops to selectively ignore, block and/or disable a control signal, the method 300 provides a level of control granularity that allows for advantageous use of circuit resources.

It should be noted that although not specifically specified, one or more steps, functions and/or operations of the method 300 may include a storing, displaying and/or outputting step as required for a particular application. In other words, any data, records, fields, tables, and/or intermediate results discussed in the method can be stored, displayed and/or outputted to another device as required for a particular application. Furthermore, steps, operations, or blocks in FIG. 3 that recite a determining operation or involve a decision, do not necessarily require that both branches of the determining operation be practiced. In other words, one of the branches of the determining operation can be deemed as an optional step. In addition, although the steps/functions/operations of method 300 are listed in a particular order, it should be noted that in other, further and different examples of the present disclosure, any one or more of the steps of method 300 may be performed in a different order, or even performed at the same time.

FIG. 4 depicts a high level block diagram of a general purpose computer, a computing device, or a computing system 400 suitable for use in performing some or all of the functions described herein. As depicted in FIG. 4 , the system 400 comprises a processor element 402 (e.g., a microprocessor, a central processing unit (CPU) and the like), a memory 404 (e.g., random access memory (RAM), read only memory (ROM) a disk drive, an optical drive, a magnetic drive, and/or a Universal Serial Bus (USB) drive), a module 405 for managing/programming an integrated circuit, and various input/output devices 406 (e.g., storage devices, including but not limited to, a tape drive, a floppy drive, a hard disk drive or a compact disk drive, a receiver, a transmitter, a speaker, a display, a speech synthesizer, an output port, and/or a user input device (such as a keyboard, a keypad, a mouse, and the like)).

It should be noted that the present disclosure can be implemented in software and/or in a combination of software and hardware, e.g., using application specific integrated circuits (ASIC), programmable ICs, a PLD such as an FPGA, a general purpose computer or any other hardware equivalents such as microprocessors. For example, computer readable instructions pertaining to the method discussed above can be used to configure a hardware processor to perform the steps, functions and/or operations of the above disclosed method. Thus, in one example the present module or process 405 can be loaded into memory 404 and executed by processor 402 to configure an integrated circuit to perform the functions as discussed above. As such, the present module or process 405 (including associated data structures) can be stored on a non-transitory computer readable storage medium, e.g., RAM memory, magnetic or optical drive or diskette and the like.

The exemplary methods and apparatuses may also be implemented in whole or in part by a programmable IC, e.g., a PLD and/or FPGA. A PLD is a general-purpose device that can be programmed by a user to implement a variety of selected functions. One type of PLD is a Field Programmable Gate Array (FPGA), which typically includes an array of configurable logic blocks (CLBs) and a plurality of input/output blocks (IOBs). The CLBs are individually programmable and can be configured to perform a variety of logic functions on a few input signals. The IOBs can be configured to drive output signals from the CLBs to external pins of the FPGA and/or to receive input signals from the external FPGA pins. The FPGA also includes a programmable interconnect structure that can be programmed to selectively route signals among the various CLBs and IOBs to produce more complex functions of many input signals. The CLBs, IOBs, and the programmable interconnect structure are programmed by loading configuration data into associated memory cells that control various switches and multiplexers within the CLBs, IOBs, and the interconnect structure to implement logic and routing functions specified by the configuration data to implement a user design in the FPGA. An FPGA may also include other programmable and non-programmable resources. As such, the steps, functions and/or operations shown above in connection with the method of FIG. 3 may be implemented in one or more CLBs that perform equivalent logic operations. For example, the method 300 may provide a programmable IC in which the steps of 310 - 370 are configuring steps that are applied to the IC to form the various structures as discussed in FIGS. 1-2 . Similarly, the circuits shown above in connection with FIGS. 1 and 2 may comprise components of any one or more CLBs, e.g., a slice of an FPGA, and the like. Accordingly, the method of FIG. 3 may comprise computer-readable/computer-executable instructions loaded from the memory cells to configure/program an integrated circuit such as shown in FIGS. 1 and 2 above.

While the foregoing describes illustrative examples in accordance with one or more aspects of the present invention, other and further embodiment(s) in accordance with the one or more aspects of the present invention may be devised without departing from the scope thereof, which is determined by the claim(s) that follow and equivalents thereof. Claim(s) listing steps do not imply any order of the steps. Trademarks are the property of their respective owners.