Cell sensing circuit for phase change memory and methods thereof

The present invention relates to a cell sensing circuit for a phase change memory and methods thereof. More particularly, it relates to a method for sensing a phase change memory having a multi-level cell with plural cells.

Sensing a phase change memory is always a challenge especially when the reference cell and the target cell of the phase change memory are both located at high resistance range. The traditional way of sensing a phase change memory is to provide a voltage to generate a cell current signal. When the target cell resistance and the reference resistance get higher, the cell current signals flowing through the target cell and the reference cell are too small to verify a voltage difference between the target cell and the reference cell.

The conventional method of developing a cell signal (V cell ) has the following sequence:

Providing a clamping voltage of V Clamp with any kind of pre-charge scheme for setting up a bit line voltage (V BL );

Generating a cell current (I cell ), wherein I cell relates to a bitline voltage and a cell state, and the cell state is the resistance of phase change memory (R PAR +R cell ), where R PAR is the parasitic resistance and R cell is the resistance of the cell;

Setting I cell =V BL /( R PAR +R cell ); and

Developing a cell voltage V Cell for being provided to a sense amplifier, wherein V Cell =I Cell *R Load , where R Load is the resistance of the load. This sequence can be accomplished by a circuit as shown in FIG. 1 . FIG. 1 is a schematic circuit diagram of a portion of a conventional sensing circuit on a target cell side for a phase change memory. In FIG. 1 , it includes a load having a resistance R Load with a first and a second terminals, a clamping switch MC with a first, a second and a control terminals, a parasitic resistor with a resistance R PAR and a cell resistor with a resistance R cell , wherein the first terminal of the load receives a power voltage and the second terminal of the load is electrically connected to the first terminal of the clamping switch MC at a first node for outputting a cell voltage V cell , the control terminal of the clamping switch receives a clamping voltage V clamp , and the second terminal of the clamping switch MC is electrically connected to the first terminal of the parasitic resistor at a second node for providing a bitline voltage V BL , wherein the clamping switch is a MOSFET MC with the first terminal being a drain, the second terminal being a source, and the control terminal being a gate, and V BL =V Clamp −V gsMC , where V gsMC is the voltage difference between the gate and the source of the MOSFET MC.

Keeping the drawbacks of the prior arts in mind, and employing experiments and research full-heartily and persistently, the applicant finally conceived a cell sensing circuit for a phase change memory and methods thereof.

It is therefore an object of the present invention to provide a cell sensing circuit for a phase change memory and methods for sensing a phase change memory and for sensing a phase change memory having a multi-level cell with plural cells to determine a logic state of the target cell of the phase change memory and respective logic states of the multi-level cell with plural cells respectively, wherein relatively higher voltages are provided to a target cell and a reference cell of the phase change memory to provide two identical stable currents thereto for increasing the current signals of the target cell and the reference cell so as to overcome the problem of sensing the phase change memory that when both of the target cell and the reference cell are located at high resistance range, the respective current signals flowing through the target cell and the reference cell are too small to verify a voltage difference between the target cell and the reference cell.

According to the first aspect of the present invention, a cell sensing circuit for a phase change memory includes two current sources respectively generating two identical stable currents, wherein the phase change memory has a reference cell receiving one of the two identical stable currents to set up a reference voltage and a target cell receiving the other one of the two identical stable currents to set up a cell voltage, and the cell voltage is higher than a read voltage provided to the target cell, and a sense amplifier receiving the reference voltage and the cell voltage to determine a logic state of the target cell based on a voltage difference between the reference voltage and the cell voltage.

According to the second aspect of the present invention, a method for sensing a phase change memory includes: providing a sensing circuit having a sense amplifier, and two identical stable currents respectively received by a reference cell and a target cell of the phase change memory; establishing a cell voltage of the target cell and a reference voltage of the reference cell respectively via the two identical stable currents; and using the sense amplifier to determine a logic state of the target cell based on a voltage difference between the reference voltage and the cell voltage.

According to the third aspect of the present invention, a method for sensing a phase change memory having a multi-level cell with plural cells includes: providing plural reference states; setting up all the plural cells as unmarked; and sensing and comparing the unmarked plural cells with a specific one of the plural reference states from a lowest value of the plural reference states to a highest value of the plural reference states to obtain plural cell signals to determine respective logic states of the plural cells.

The present invention may best be understood through the following descriptions with reference to the accompanying drawings, in which:

FIG. 1 is a schematic circuit diagram of a portion of a conventional sensing circuit on a target cell side for a phase change memory;

FIG. 2 is a circuit diagram showing a portion of a sensing circuit on a target cell side for a phase change memory according to the first preferred embodiment of the present invention;

FIG. 3 is a circuit diagram showing a portion of a sensing circuit on a target cell side for a phase change memory according to the second preferred embodiment of the present invention;

FIG. 4( a ) is a circuit diagram showing a portion of a sensing circuit on a reference cell side for a phase change memory according to the first preferred embodiment of the present invention;

FIGS. 4( b )- 4 ( d ) are respectively a circuit diagram showing a portion of a sensing circuit on a reference cell side for a phase change memory according to the third to the fifth preferred embodiments of the present invention;

FIG. 5 is a circuit diagram showing a portion of a sensing circuit on a target cell side for a phase change memory according to the sixth preferred embodiment of the present invention;

FIG. 6 is a circuit diagram of a sensing circuit for a phase change memory according to the fourth preferred embodiment of the present invention;

FIG. 7 is a circuit diagram of a sensing circuit for a phase change memory according to the seventh preferred embodiment of the present invention;

FIG. 8 is a circuit diagram of a sensing circuit for a phase change memory according to the eighth preferred embodiment of the present invention;

FIG. 9 is a circuit diagram of a sensing circuit for a phase change memory according to the ninth preferred embodiment of the present invention;

FIGS. 10( a )- 10 ( c ) show three respective reference cells in the chip for estimating the V Clamp voltage according to the tenth preferred embodiment of the present invention;

FIG. 10( d ) shows a schematic diagram of 4 states of a MLC having plural cells according to the tenth preferred embodiment of the present invention;

FIG. 10( e ) shows a schematic diagram of the 4 states and the steps included in the proposed method for sensing a phase change memory having a multi-level cell with plural cells according to the tenth preferred embodiment of the present invention; and

FIG. 11 is a flow chart of the proposed method for sensing a phase change memory having a multi-level cell with plural cells according to the eleventh embodiment of the present invention.

The present disclosure will be described with respect to particular embodiments and with reference to certain drawings, but the disclosure is not limited thereto but is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not necessarily correspond to actual reductions to practice.

The way to increase a current signal is to give a higher voltage which should be well controlled for preventing cell disturbance.

The present invention discloses a novel sensing scheme enhancing the sensing window. The idea is to provide two identical stable currents for a reference cell and a target cell. The two identical stable currents respectively establish a voltage level on a reference cell side and the other voltage level on a target cell side, and then a sense amplifier is used to determine a logic state of the target cell based on a voltage difference between the target cell and the reference cell.

This enhanced and wider window makes the multi-level cell sensing more practical, wherein the multi-level cell with plural cells usually involves higher resistance.

FIG. 2 is a circuit diagram showing a portion of a sensing circuit on a target cell side for a phase change memory according to the first preferred embodiment of the present invention. In FIG. 2 , it includes a current source generating one of two identical stable currents, I Target , and having a first terminal receiving a power voltage and a second terminal electrically connected to a first node providing a cell voltage V Cell , and electrically connected to a load with a parasitic resistor having a resistance R PAR and a cell resistor having a resistance R cell and electrically connected to the parasitic resistor in series, wherein the load has a first terminal electrically connected to the first node and a second terminal electrically connected to a ground, and a current I cell flows through the cell.

The cell signal developing procedure of the present invention is different from that of the prior art as shown in FIG. 1 . The cell current I Cell is forced to a higher value. By doing this, the cell current I Cell will have a value higher than a read current flowing through the target cell for providing a read voltage to the target cell with a high resistance. The target current I Target is generated in a chip, and is transferred to the memory cell. With proper design, the I Cell is equal to I Target , i.e. I Target =I Cell . The target cell is acting as a load, and V Cell is generated according to the following equation V Cell =I Target *(R PAR +R Cell ).

FIG. 3 is a circuit diagram showing a portion of a sensing circuit on a target cell side for a phase change memory according to the second preferred embodiment of the present invention. In FIG. 3 , the sensing circuit includes a pre-charge circuit and a current source. The pre-charge circuit has a clamping switch MC with a drain receiving a power voltage, a source and a gate receiving a clamping voltage V Clamp . The current source generates one of two identical stable currents, I Target , and has a first terminal receiving the power voltage, and a second terminal electrically connected to a first node providing a cell voltage V Cell , and electrically connected to the source of the switch MC. The target cell has a load with a parasitic resistor having a resistance R PAR , and a cell resistor having a resistance R cell and electrically connected to the parasitic resistor in series, wherein the load has a first terminal electrically connected to the first node and a second terminal electrically connected to a ground, and a current I cell flows through the target cell.

In FIG. 3 , it's going to be a slow process if V Cell is only established by I Target . To enhance the V Cell developing speed, a pre-charge circuit of the switch MC is employed. Higher V Clamp generates disturbance to the target cell so that the V Clamp could generate in a chip by another reference cell in the chip. The pre-charge circuit of the switch MC is turned off after V Cell is pre-charged to a certain level, and then I Target accomplishes the V Cell developing process.

FIG. 4( a ) is a circuit diagram showing a portion of a sensing circuit on a reference cell side for a phase change memory according to the first preferred embodiment of the present invention. In FIG. 4( a ), it includes a current source generating one of two identical stable currents, I Target , and having a first terminal receiving a power voltage and a second terminal electrically connected to a second node providing a reference voltage V REF , and electrically connected to a load with a parasitic resistor having a resistance R PAR , and a reference cell resistor having a resistance R REF and electrically connected to the parasitic resistor in series, wherein the load has a first terminal electrically connected to the second node and a second terminal electrically connected to a ground, and a current I REF flows through the reference cell.

FIGS. 4( b )- 4 ( d ) are respectively a circuit diagram showing a portion of a sensing circuit on a reference cell side for a phase change memory according to the third to the fifth preferred embodiments of the present invention. The difference between each of FIGS. 4( b )- 4 ( d ) and FIG. 4( a ) is that there is a selecting device electrically connected between the second terminal of the load and the ground for better signal tracking. The selecting device could be either a diode (e.g. diode Ds, see FIG. 4( b )), a MOSFET (e.g. switch SWrs receiving a control signal of REF. select, see FIG. 4( c )), or a BJT (e.g. switch SWrs receiving a control signal of REF. select, see FIG. 4( d )).

Similarly, a portion of a sensing circuit on a target cell side for a phase change memory as shown in FIGS. 2 and 3 could also further include a selecting device electrically connected between the second terminal of the load and the ground for better signal tracking and being a diode, a MOSFET, or a BJT.

FIG. 5 is a circuit diagram showing a portion of a sensing circuit on a target cell side for a phase change memory according to the sixth preferred embodiment of the present invention. The difference between FIG. 5 and FIG. 3 is that the pre-charge circuit of FIG. 5 is different from that of FIG. 3 . In FIG. 5 , there is an extra switch SWpc having a gate receiving a Precharge signal, a drain receiving a power voltage and a source electrically connected to the drain of the switch MC. FIG. 5 shows an example for enabling/disabling a pre-charge process. The Precharge signal only remains on for certain amount of time for enhancing the signal setup of V Cell and then is turned off. The difference between I Target (i.e. I REF ) and I Cell moving V Cell up or down to get the final cell signal.

FIG. 6 is a circuit diagram of a sensing circuit for a phase change memory according to the fourth preferred embodiment of the present invention. In FIG. 6 , the phase change memory and the sensing circuit 1 includes a portion of the sensing circuit on a reference cell side 11 , a portion of the sensing circuit on a target cell side 12 , a pre-charge circuit 13 and a sense amplifier 14 , and provides two identical stable currents I Target which are adjustable. The sensing circuit establishes V REF on the reference cell side, and also establishes another voltage V Cell on the target cell side. A clamping voltage V Clamp (=V REF +V gsMC ) is employed to reduce the setup time of V Cell , where V gsMC is the voltage from the gate to the source of the switch MC. The sense amplifier 14 , which could be a differential comparator or a latch, is used to determine a logic state of the target cell based on a voltage difference between the cell voltage V Cell and the reference voltage V REF . The portion of the sensing circuit on the reference cell side 11 of FIG. 6 is the same as FIG. 4( c ), and the differences between the portion of the sensing circuit on the target cell side 12 and the pre-charge circuit 13 of FIG. 6 and FIG. 3 are that there is a selecting device SWcs receiving a control signal of Cell select and electrically connected between the second terminal of the load and the ground, and Vclamp=V REF +V gsMC .

FIG. 7 is a circuit diagram of a sensing circuit for a phase change memory according to the seventh preferred embodiment of the present invention. In FIG. 7 , the phase change memory and the sensing circuit 2 includes a portion of the sensing circuit on a reference cell side 21 , a portion of the sensing circuit on a target cell side 22 , a stable current generating circuit 23 , a mirror circuit 24 , a pre-charge circuit 25 and a sense amplifier 14 . The portion of the sensing circuit on the reference cell side 21 is almost the same as the portion of the sensing circuit on the reference cell side 11 of FIG. 6 except that the current source generating I Target is omitted. The portion of the sensing circuit on the target cell side 22 is almost the same as the portion of the sensing circuit on the target cell side 12 of FIG. 6 except that the other current source generating I Target is also omitted. I Target is generated somewhere in a chip and mirrored to the reference cell and the target cell in a memory area. For the reference cell, it's going to be I REF =I Target , and also this I Target generates a reference voltage V REF for sense amplifier (SA) 14 . On the target cell side of SA 14 , I Target generates a cell voltage V Cell , V Cell was pre-charged by a clamping voltage, and then the pre-charge circuit is turned off to let I Target finish the V Cell developing process. The stable current generating circuit 23 includes a switch SWcg having a drain receiving a power voltage, a source electrically connected to a current source generating a stable current of I Target and a gate electrically connected to the source. The mirror circuit 24 includes a first mirror switch SWm 1 and a second mirror switch SWm 2 , each of which has a drain, a source and a gate. The drain of the first mirror switch SWm 1 receives a power voltage, the source of the first mirror switch SWm 1 is electrically connected to a second node of the portion of the sensing circuit on the reference cell side 21 for outputting the reference voltage V REF and the gate of the first mirror switch SWm 1 is electrically connected to the gate of the switch SWcg and the gate of the second mirror switch SWm 2 . The drain of the second mirror switch SWm 2 receives a power voltage, and the source of the second mirror switch SWm 2 is electrically connected to a first node of the portion of the sensing circuit on the target cell side 22 for outputting the cell voltage V Cell . The pre-charge circuit 25 is the same as that of FIG. 5 except that the clamping voltage Vclamp=V REF +V gsMC . The sense amplifier 14 is the same as that of FIG. 6 . The logic state of the target cell is found by comparing the voltage difference of V REF and V Cell .

FIG. 8 is a circuit diagram of a sensing circuit for a phase change memory according to the eighth preferred embodiment of the present invention. In FIG. 8 , the phase change memory and the sensing circuit 3 includes a portion of the sensing circuit on a reference cell side 21 , a portion of the sensing circuit on a target cell side 22 , a stable current generating circuit 23 , a mirror circuit 24 , a pre-charge circuit 31 and a sense amplifier 14 . The difference between FIG. 8 and FIG. 7 is that the pre-charge circuit 25 is replaced by the pre-charge circuit 31 . The pre-charge circuit 31 includes a unit gain buffer and a switch. When V Cell is precharged, V REF passes to V Cell via the unit gain buffer and the switch. Once the precharge ends, the I REF (i.e. I Target ) and I Cell accomplish the final V Cell developing process.

The mirror circuit 24 as shown in FIGS. 7 and 8 can be replaced by any kind of mirror circuit, such as a cascode current mirror, to cause the respective target currents I Target flowing through the reference cell side and the target cell side identical.

FIG. 9 is a circuit diagram of a sensing circuit for a phase change memory according to the ninth preferred embodiment of the present invention. In FIG. 9 , the phase change memory and the sensing circuit 4 includes a portion of the sensing circuit on a reference cell side 21 , a portion of the sensing circuit on a target cell side 22 , a cascode current mirror 41 and a sense amplifier 14 . The differences between FIG. 9 and FIG. 8 are that the stable current generating circuit 23 and the pre-charge circuit 41 are omitted, and the mirror circuit 24 is replaced by the cascode current mirror 41 . The cascode current mirror 41 has four mirror switches S WM1 -S WM4 . Each of the four mirror switches has a drain, a source and a gate. The drain of the switch S WM1 receives a power voltage, the gate of the switch S WM1 receives a controlled voltage and is electrically connected to the gate of the switch S WM3 , the drain of the switch S WM2 is electrically connected to the source of the switch S WM1 , the gate of the switch S WM2 receives a bias and is electrically connected to the gate of the switch S WM4 , and the source of the switch S WM2 outputs one of the two identical stable currents, I Target , and is electrically connected to a second node of the portion of the sensing circuit on the reference cell side 21 for outputting the reference voltage V REF . The drain of the switch S WM3 receives a power voltage, the drain of the switch S WM4 is electrically connected to the source of the switch S WM3 , and the source of the switch S WM4 outputs the other one of the two identical stable currents, I Target , and is electrically connected to a first node of the portion of the sensing circuit on the target cell side 22 for outputting the cell voltage V Cell .

FIGS. 10( a )- 10 ( c ) show three respective reference cells in a chip for estimating the V Clamp voltage according to the tenth preferred embodiment of the present invention. For multi-level cell (MLC) applications, FIG. 10( d ) shows a schematic diagram of 4 states of a MLC having plural cells according to the tenth preferred embodiment of the present invention as an example. In this example, V Clamp-Lo , V Clamp-Mi and V Clamp-Hi relate to V REF-Lo , V REF-Hi and V REF-Hi respectively. For phase change memory, cells with a higher resistance have a higher tolerance to the disturbance generating from higher bitline voltage. To minimize the disturbance, the cells are sensed from V REF-Lo to V REF-Hi , once determined that the cell resistance is lower than the reference resistance (or the cell voltage is lower than the reference voltage), the cell is flagged.

For example, if the reference voltage is V REF-Lo , for each of the cells having been determined to possess a resistance lower than R REF-Lo is not going to be read again with R REF-Mi . FIG. 10( e ) shows a schematic diagram of the 4 states and steps included in the above-mentioned method for sensing a phase change memory having a multi-level cell with plural cells according to the tenth preferred embodiment of the present invention. In FIG. 10( e ), the proposed method includes step 1 : using V REF-Lo to sense the cell in every group 0-3; step 2 : using V REF-Mi to sense the cell in every group 1-3; step 3 : using V REF-Hi to sense the cell in every group 2-3; and step 4 : getting a logic state for each of the cells.

FIG. 11 is a flow chart of the proposed method for sensing a phase change memory having a multi-level cell with plural cells according to the eleventh embodiment of the present invention. There is a trade-off between cell signal and disturbance. Higher voltage provides higher cell signal and higher disturbance also. Therefore, the MLC sensing has to follow the steps included in the flow chart as shown in FIG. 11 . In FIG. 11 , the flow chart includes the steps of: starting with the lowest reference state; setting up and sensing the cell signal; if the cell resistance is smaller than the reference resistance, then marking the cells as having lower resistance than the reference resistance; if all the cells are with lower resistance than the reference resistance, then finishing the method since all the cells have their respective logic states; if all the cells are not with lower resistance than the reference resistance, then checking whether the highest reference state is reached; if the highest reference state is not reached, then increasing the reference resistance; and if the highest reference state is reached, then marking the remaining cells as having higher resistance. The main idea of preventing disturbance is to sense the cell with bitline voltage from low to high. Once a cell has been verified that its resistance is lower than the current reference state, the cell gets flagged and is prevented to be pre-charged or sensed again with next higher bit line voltage.

While the invention has been described in terms of what are presently considered to be the most practical and preferred embodiments, it is to be understood that the invention need not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures. Therefore, the above description and illustration should not be taken as limiting the scope of the present invention which is defined by the appended claims.