Inventor

Chao-I Wu

Inventor

Hsinchu, TW

Overview

1994–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 112 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores43%

H10DInorganic electric semiconductor devices23%

H10BElectronic memory devices18%

H10NElectric solid-state devices not otherwise provided for5%

H01LSemiconductor devices3%

A63BApparatus for physical training, gymnastics, swimming, climbing, or fencing2%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

B27BSaws for wood or similar material1%

B82YSpecific uses or applications of nanostructures1%

PatentTitleYear

10,882,206Low profile chainsaw2021 10,158,068Resistive random access memory device and method for manufacturing the same2018 9,997,567Semiconductors structure having an RRAM structure and method for forming the same2018 9,711,217'Memory device and operating method for resistive memory cell'2017 9,627,054'Memory operating method for increasing cell capacity based on resistance characteristic of memory and associated memory device'2017 9,627,058'Resistance random access memory with accurate forming procedure, operating method thereof and operating system thereof'2017 9,620,210'Method and apparatus for healing phase change memory devices'2017 9,583,536'Memory device and method for manufacturing the same'2017 9,564,216'Stress trim and modified ISPP procedures for PCM'2017 9,558,823'Resistance drift recovery method for MLC PCM'2017 9,478,288'Method for programming memory device and associated memory device'2016 9,396,793'Phase change memory, writing method thereof and reading method thereof'2016 9,373,382'Method for healing phase-change memory device and applications thereof'2016 9,349,443'Method and system for programming multi-level cell memory'2016 9,336,879'Multiple phase change materials in an integrated circuit for system on a chip application'2016 9,336,867'Phase change memory coding'2016 9,336,878'Method and apparatus for healing phase change memory devices'2016 9,312,029'Memory device and associated controlling method'2016 8,908,426'Cell sensing circuit for phase change memory and methods thereof'2014 8,891,293'High-endurance phase change memory devices and methods for operating the same'2014 8,659,952'Method of operating non-volatile memory'2014 8,634,235'Phase change memory coding'2014 8,481,388'Non-volatile memory device having a nitride-oxide dielectric layer'2013 8,467,238'Dynamic pulse operation for phase change memory'2013 8,432,745'High second bit operation window method for virtual ground array with two-bit memory cells'2013 8,426,906'Method and structure for a semiconductor charge storage device'2013 8,378,382'High aspect-ratio PN-junction and method for manufacturing the same'2013 8,374,019'Phase change memory with fast write characteristics'2013 8,363,463'Phase change memory having one or more non-constant doping profiles'2013 8,334,182'Method for manufacturing non-volatile memory'2012 8,329,535'Multi-level-cell trapping DRAM'2012 8,295,094'Method of operating non-volatile memory cell'2012 8,263,464'Systems and methods for memory structure comprising a PPROM and an embedded flash memory'2012 8,258,029'Semiconductor structure and process for reducing the second bit effect of a memory device'2012 8,241,928'Test structure and method for detecting charge effects during semiconductor processing'2012 8,238,149'Methods and apparatus for reducing defect bits in phase change memory'2012 8,223,540'Method and apparatus for double-sided biasing of nonvolatile memory'2012 8,178,407'Systems and methods for a high density, compact memory array'2012 8,138,540'Trench type non-volatile memory having three storage locations in one memory cell'2012 8,072,810'Program and erase methods with substrate transient hot carrier injections in a non-volatile memory'2011 8,036,027'Semiconductor device and memory'2011 8,009,482'High temperature methods for enhancing retention characteristics of memory devices'2011 7,986,558'Method of operating non-volatile memory cell and memory device utilizing the method'2011 7,986,564'High second bit operation window method for virtual ground array with two-bit memory cells'2011 7,982,262'NAND memory device with inversion bit lines'2011 7,947,607'Apparatus and associated method for making a virtual ground array structure that uses inversion bit lines'2011 7,903,471'Method for improving memory device cycling endurance by providing additional pulses'2011 7,881,112'Program and erase methods with substrate transient hot carrier injections in a non-volatile memory'2011 7,839,695'High temperature methods for enhancing retention characteristics of memory devices'2010 7,817,472'Operating method of memory device'2010 7,804,711'Methods of operating two-bit non-volatile flash memory cells'2010 7,778,076'Memory unit'2010 7,773,430'Method of identifying logical information in a programming and erasing cell by on-side reading scheme'2010 7,763,927'Non-volatile memory device having a nitride-oxide dielectric layer'2010 7,759,726'Non-volatile memory device, non-volatile memory cell thereof and method of fabricating the same'2010 7,759,721'Single poly non-volatile memory device with inversion diffusion regions and methods for operating the same'2010 7,755,129'Systems and methods for memory structure comprising a PPROM and an embedded flash memory'2010 7,738,300'Memory cell and method of programming the same'2010 7,718,491'Method for making a NAND Memory device with inversion bit lines'2010 7,684,252'Method and structure for operating memory devices on fringes of control gate'2010 7,672,159'Method of operating multi-level cell'2010 7,652,923'Semiconductor device and memory and method of operating thereof'2010 7,608,886'Systems and methods for a high density, compact memory array'2009 7,599,229'Methods and structures for expanding a memory operation window and reducing a second bit effect'2009 7,596,030'Method for improving memory device cycling endurance by providing additional pulse'2009 7,593,262'Memory structure and operating method thereof'2009 7,590,005'Program and erase methods with substrate transient hot carrier injections in a non-volatile memory'2009 7,570,514'Method of operating multi-level cell and integrate circuit for using multi-level cell to store data'2009 7,561,470'Double-side-bias methods of programming and erasing a virtual ground array memory'2009 7,548,458'Methods of biasing a multi-level-cell memory'2009 7,512,013'Memory structures for expanding a second bit operation window'2009 7,501,837'Test structure and method for detecting charge effects during semiconductor processing using a delayed inversion point technique'2009 7,495,967'Method of identifying logical information in a programming and erasing cell by on-side reading scheme'2009 7,492,636'Methods for conducting double-side-biasing operations of NAND memory arrays'2009 7,486,567'Method for high speed programming of a charge trapping memory with an enhanced charge trapping site'2009 7,486,560'Apparatus and associated method for making a virtual ground array structure that uses inversion bit lines'2009 7,485,531'Fabricating method of a non-volatile memory'2009 7,483,299'Devices and operation methods for reducing second bit effect in memory device'2009 7,474,562'Method of forming and operating an assisted charge memory device'2009 7,474,567'Method for programming multi-level nitride read-only memory cells'2009 7,471,568'Multi-level cell memory structures with enlarged second bit operation window'2008 7,466,589'NAND memory cell at initializing state and initializing process for NAND memory cell'2008 7,433,238'Method of programming memory cell'2008 7,414,280'Systems and methods for memory structure comprising embedded flash memory'2008 7,411,836'Method of operating non-volatile memory'2008 7,372,732'Pulse width converged method to control voltage threshold (Vt) distribution of a memory cell'2008 7,342,264'Memory cell and method for manufacturing the same'2008 7,292,478'Non-volatile memory including charge-trapping layer, and operation and fabrication of the same'2007 7,266,014'Method of operating non-volatile memory device'2007 7,251,167'Method for programming multi-level nitride read-only memory cells'2007 7,242,052'Non-volatile memory'2007 7,218,554'Method of refreshing charge-trapping non-volatile memory using band-to-band tunneling hot hole (BTBTHH) injection'2007 7,209,390'Operation scheme for spectrum shift in charge trapping non-volatile memory'2007 7,209,385'Array structure for assisted-charge memory devices'2007 7,206,225'Method of dynamically controlling program verify levels in multilevel memory cells'2007 7,206,227'Architecture for assisted-charge memory array'2007 7,190,614'Operation scheme for programming charge trapping non-volatile memory'2007 7,151,692'Operation scheme for programming charge trapping non-volatile memory'2006 7,145,809'Method for programming multi-level cell'2006 7,139,200'Method of identifying logical information in a programming and erasing cell by on-side reading scheme'2006 7,085,165'Method and apparatus for reducing read disturb in non-volatile memory'2006 7,085,168'Programming method for controlling memory threshold voltage distribution'2006 7,054,192'Method of controlling threshold voltage of NROM cell'2006 7,038,928'Method of determining optimal voltages for operating two-side non-volatile memory and the operating methods'2006 6,952,038'3D polysilicon ROM and method of fabrication thereof'2005 6,937,511'Circuit and method for programming charge storage memory cells'2005 6,903,410'Electrically erasable programmable read only memory cell and programming method thereof'2005 6,890,819'Methods for forming PN junction, one-time programmable read-only memory and fabricating processes thereof'2005 5,344,139'Racket shaft mounting device'1994 5,322,280'Racket handle'1994 5,312,115'Racket'1994 5,310,180'Racket frame'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994Based in Taichung, TW· patent location history

2005–2018Patents assigned to MACRONIX INT CO LTD (107)· patent assignee history

2005–2018Based in Hsinchu, TW· patent location history

2005–2012Based in Tainan, TW· patent location history

2008–2016Based in Zhubei City, TW· patent location history

2011–2014Patents assigned to WU CHAO-I (20)· patent assignee history

2011–2013Patents assigned to HSU TZU-HSUAN (4)· patent assignee history

2012–2014Patents assigned to LEE MING-HSIU (5)· patent assignee history

2012–2014Patents assigned to SHIH YEN-HAO (4)· patent assignee history

2012Based in Hsinchu County, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MACRONIX INT CO LTD	107	2005–2018
WU CHAO-Iself	20	2011–2014
LEE MING-HSIU	5	2012–2014
HSU TZU-HSUAN	4	2011–2013
SHIH YEN-HAO	4	2012–2014

Locations

Location	Patents	Span
Hsinchu, TW	61	2005–2018
Tainan, TW	23	2005–2012
Zhubei City, TW	20	2008–2016
Taichung, TW	4	1994
Hsinchu County, TW	2	2012