Multicore chip with holographic optical interconnects

The present invention relates to the semiconductor industry and, in particular, to multicore chips with optical interconnects between data-processing cores formed on multicore chips of a computer or the like. More specifically, the invention relates to optical interconnects between two or more data-processing cores of a multicore chip by means of digital planar holograms.

A multicore processor is a device that contains two or more independent computing components which are known as “cores or data-processing cores” that read and execute program instructions. Manufacturers typically integrate the data-processing cores onto a host-chip multiprocessor or CMP, or in a single chip package.

At the present time, a dual-core processors are known as processors that have two cores, a quad-core processor are those that contains four cores, a hexa-core processor contains processors that contain six cores, etc., and so on up to 64 cores. It can be assumed that the number of cores on a host chip may further increase in the future.

Presently, a common network topology for interconnection involves metal interconnects of the type used inside the host chip and includes the use of buses, rings, two-dimensional meshes, and crossbars. The architecture of the network topology of multicore interconnects may be rather complicated and its development continues.

With the increase of computing power realized on a chip, the use of traditional electrical interconnects becomes a limiting factor, i.e., preventing further scaling of modern multicore processors. A solution envisioned for future generation high-performance processors involves employment of optical interconnects. Replacing conventional electrical wires with optical waveguides helps to increase the overall bandwidth of data transmission, maintains channel crosstalk at a low value, and reduces the chip footprint allocated for interconnections.

Devices for optical interconnects between various electronic components mounted on the same or different PC boards of a computer, or between two or more independent chips, etc., are known in the art. The idea of optical interconnects per se is so obvious that it emerged much earlier than the appearance of multicore processors. In the past, the problem of optical interconnect has been solved in different ways.

For example, U.S. Pat. No. 5,832,147 issued Nov. 3, 1998 to Yeh, et al, discloses a holographic optical interconnect system and method for board-to-board and chip-to-chip communication interconnections. Each circuit board has at least an optically transparent substrate mate parallel to the circuit board and extending outside a circuit board holder. Each optically transparent substrate mate has parallel sides and carries at least two holographic optical elements. The first holographic optical elements on the first optically transparent substrate mate reflects at least a predetermined portion of a first light beam transmitted by a transmitter on a corresponding circuit board to another holographic optical element, which transmits a received light beam via free space outside the circuit board holder. On the other optically transparent substrate mate, two holographic optical elements are used to receive and direct at least part of the light beam received to a detector on a corresponding circuit board via free space within the circuit board holder or reflection within the optically transparent substrate mate.

U.S. Pat. No. H738 issued Feb. 6, 1990 to McManus, et al, discloses a switched hologram for reconfigurable optical interconnect. The device uses an array of optical switches that directs a set of optical beams toward any one of a selection of holograms, and each hologram when selected deflects the input beams toward a detector. The switches are arranged in rows, each optical switch includes a liquid crystal cell and a polarizing beam splitter, and each switch of said rows has an output face through which optical parallel beams can be projected to holographic spots of a hologram plate located adjacent to said output face and further from the holographic spots to detector means

U.S. Pat. No. 5,515,462 issued May 7, 1996 to Huang, et al, discloses an optical interconnect in optical packages using holograms for interconnection of two optical elements. Light radiation from the first optical component, e.g., an optical light fiber, is directed onto the plane surface of the second optical component, e.g., a passive waveguide. The light is directed onto the second optical component at a convenient angle such that it impinges on the plane surface of the second optical component at an incident angle. An angularly selective coupling means, e.g., a volume hologram, is located between the first and second optical components for coupling the maximum amount of the light at the incident angle.

U.S. Pat. No. 5,706,114 issued Jan. 6, 1998 to Erteza discloses an optical communication system that uses holographic optical elements to provide guided wave and nonguided communication, resulting in high bandwidth and high-connectivity optical communications. Holograms within holographic optical elements route optical signals between elements and between nodes connected to elements. Angular and wavelength multiplexing allow the elements to provide high connectivity. The combination of guided and nonguided communication allows polyhedral system geometries.

U.S. Pat. No. 4,838,630 issued Jun. 13, 1989 to Jannson, et al, discloses an optical interconnect that employs planar volume Bragg hologram technology in two dimensions and comprises a dichromated gelatin planar volume Bragg hologram disposed in a glass planar optical path. Multiplexed Bragg plane sets selectively diffract information-bearing light signals such as voice, image, or computer data signals in a very large-scale integration (VLSI) system from a laser diode or a light-emitting diode (LED) source coupled to the planar optical path toward high-speed photodiodes. The holographic planar optical interconnect can interconnect up to 1000 different signals between VLSI microelectronic components and systems.

However, all optical interconnects described above accomplish merely interconnection functions without any modulation or other data control processes and also do not match with the latest developments in the field of multicore processor technique in view of limitations with regard to chip footprint allocated for interconnections. Furthermore, in spite of the fact that all known optical interconnect devices described above possess essential advantages over traditional electrical interconnects, they did not find wide practical application in the industry because they do not match the current semiconductor production technology.

The present invention provides a host multicore chip with specific optical interconnects between data-processing cores. The interconnection elements are formed on the same host chip substrate as the data-processing cores and comprise a service integral optical microchip (microchips) that is (are) located on the same host chip and is (are) based on the use of digital planar holography (DPH) technique. More specifically, the basic element of such a topology is a multiconnector hologram, which interconnects all processing cores on the chip.

The holographic service integral optical microchip (hereinafter referred to as a “holographic microchip”) performs commutation between the cores of the host chip with the use of planar digital ridge waveguides that are also formed on the same substrate as the cores and the holographic microchip. According to the invention, the holographic microchip further incorporates a function of a wavelength demultiplexer for delivery light signals that are designated to specific cores.

The holographic microchip may obtain optical signals from one or several laser light sources and may be used for interconnection of a plurality of cores, e.g., 4 to 8 cores using 4/8 laser frequencies and avoid switches. A light source may be external, and the cores may be provided with respective optical modulators/transceivers that have a function of coding the obtained optical signals by modulating these signals with the core-generated data, and with receivers that have a function of decoding the obtained data.

The device of the invention makes it possible to realize various interconnects with structures having distances between the cores as short as several millimeters to approximately 1 cm or greater.

The DPH may have dimensions in the range of 0.05×0.05 cm to 0.5×0.5 cm, typically 0.1×0.1 cm. Interconnections between the light source, holographic microchip, and the cores are carried out by means of optical planar ridge waveguides.

According to one aspect of the present invention, each core operates on a predetermined light wavelength and comprises a DC laser light input and a DC laser light modulator/transceiver for modulation of the obtained DC laser light and for transfer of the modulated light signal to each of the remaining, in this case three, cores of the host chip. Therefore, in addition to the DC input, each core should have three inputs for modulated light signals.

The input waveguide receives a DC laser light from a laser source, e.g., from an external laser system that provides four different wavelengths (e.g. in 1310 nm window). These wavelengths are split by first holographic microchip, and each of the supplied wavelengths goes to the respective DC light inputs of the corresponding processing core that operates on the obtained light of the predetermined wavelength. The optical modulator/transceiver of each core converts its data into optical form. The output of each core sends the modulated light signal to the second holographic microchip that takes these signals, splits each of them into three, and delivers these three copies to all the cores but the core that provided this signal. Thus, each of the cores is able to broadcast its data to all others. A central management is only required for selecting which signal the core should listen to at each moment.

In a general form, the host chip with holographic optical interconnects of the present invention comprises: a substrate; “N” laser light sources that generate lights of “N” different wavelength; an “N” data-processing cores that produce data and are formed on the substrate, the data processing cores comprising an optical signal receivers and modulators/transceivers that receive lights from the laser light sources and have a function of modulating the light obtained from the laser light sources with the data produced by the cores thus producing modulated light signals; first optical coupling means for optically coupling the laser light sources with the modulators/transceivers; at least one holographic microchip formed on the substrate of the host chip that comprises a first digital planar hologram; second optical coupling means for optically coupling the modulators/transceivers with the at least one holographic microchip; light splitting means on the at least one holographic microchip for spatially splitting the modulated light signals obtained from the modulators/transceivers at least into (N-1)N optical copy signals; and third optical coupling means for optically coupling the modulated optical copy signals to receivers of all data-processing cores except the one that generates said modulated optical copy signals, the receivers having a function of decoding the obtained optical copy signals.

The first, second, and third optical coupling means comprise planar optical ridge waveguides formed on the substrate of the host chip.

The light splitting means on the at least one holographic microchip comprise a first digital planar hologram.

The host chip further comprises an auxiliary holographic microchip formed on the substrate of the host chip between the “N” light sources and the data processing cores. The auxiliary holographic microchip has means for dividing the light obtained from laser light sources into “N” component laser lights of different wavelengths. The host chip further contains the fourth optical coupling means for optically coupling the “N” light sources with the auxiliary holographic microchip; and fifth optical coupling means for optically coupling the auxiliary holographic microchip with the each data processing core.

The fourth and fifth optical coupling means comprise planar optical ridge waveguides formed on the substrate of the host chip.

The means for dividing the light obtained from laser light sources into “N” component laser lights of different wavelengths comprise an auxiliary digital planar hologram.

FIG. 1 is a schematic top view of the host chip having data-processing cores and optical elements interconnected by the interconnects of the invention.

FIG. 2 is a more detailed top view of the host chip of FIG. 1 that illustrates inputs and outputs of the data-processing cores and of the main holographic microchip.

FIG. 3 is a more detailed top view of an auxiliary holographic microchip that functions as a wavelength demultiplexer that spatially separates the lights of different wavelengths.

FIG. 4 is a plan view of the area A of the main holographic microchip shown in a larger scale than in FIG. 2 .

FIG. 5 is a more detailed top view of the main holographic microchip that conventionally illustrates the process of copying of the modulated signals delivered to the digital planar hologram of this holographic microchip from the data-processing cores.

The present invention relates to a multicore host chip with holographic optically interconnects between the data-processing cores. The interconnect elements comprise optical microchips that are formed on the same host chip substrate as the data-processing cores and are based on the use of digital planar holography (DPH) technique. The interconnection elements also include ridge waveguides that are formed on the substrate and are used for linking the service integral optical microchips to respective cores.

In the context of the present invention the term “planar” in connection with the optical interconnect is conventional, because, strictly speaking the interconnection elements such as ridge waveguides and digital planar holograms are not two-dimensional but rather three-dimensional as they comprise a very thin layered structure consisting at least of a substrate, two cladding layers, and a core layer between them, etc. Furthermore, the holographic elements are formed in the core layer as grooves and projections. However, as compared to conventional multilayered integrated chips with the metallic interconnects the interconnection elements of the present invention are considered planar.

For better understanding the present invention, it is necessary first to get acquainted with the architecture and structure of the host chip with the aforementioned optical interconnection elements.

FIG. 1 is a schematic top view of the host chip 20 having a substrate 22 on which a plurality, in this modification four, data-processing cores 24 a, 24 b, 24 c, and 24 d, are formed. In the modification of FIG. 1 , the data-processing cores 24 a, 24 b, 24 c, and 24 d are shown as four symmetrically arranged square blocks, and DPH 1 and DPH 2 are shown as auxiliary and main holographic microchips, respectively. FIG. 2 is a more detailed top view of the host chip 20 that does not show the auxiliary holographic microchip DPH 1 but illustrates inputs and outputs of the data-processing cores and of the main holographic microchip DPH 2 .

Interconnection elements of the host chip 20 shown in FIG. 1 are “multi-connector” holographic microchips DPH 1 and DPH 2 , which interconnect all processing cores on the chip 20 and, in fact, comprise holographic service integral optical microchips (hereinafter referred to as a “holographic microchips”).

Reference numeral 26 ( FIG. 1 ) designates a laser light source that comprises a plurality of monochromatic lasers, e.g., four lasers that emit laser lights, e.g., of λ 1 , λ 2 , λ 3 , and λ 4 wavelengths, respectively. These monochromatic laser lights are delivered from the laser light source 26 to the inputs (not shown in FIG. 1 ) of the auxiliary holographic microchip DPH 1 via a planar ridge waveguide 28 and are demultiplexed by means of a digital planar hologram H 1 of the DPH 1 which is shown in more detail in FIG. 3 and is described in more detail later. It is understood that the DPH 1 has an auxiliary function of demultiplexing the monochromatic laser light and that these lights can be sent directly from the respective laser diodes to the inputs of the respective data-processing cores. Such a version is shown in FIG. 2 .

As mentioned above, the digital planar hologram H 1 of the auxiliary holographic microchip DPH 1 is constructed and operates on the principle close to the one described U.S. Pat. No. 7,889,336 issued Feb. 15, 2011 to Yankov. In other words, the holographic microchip DPH 1 spatially separates the lights of different wavelengths λ 1 , λ 2 , λ 3 , and λ 4 and couples them to the planar ridge waveguides 30 a, 30 b, 30 c, and 30 d ( FIG. 1 ) through which these monochromatic lights are delivered to data-processing cores 24 a, 24 b, 24 c, and 24 d that use the lights of the corresponding wavelengths for communication with the other data-processing cores 24 a, 24 b, 24 c, and 24 d formed on the substrate 22 of the multicore chip 20 . In FIG. 1 , reference numerals 23 a, 23 b, 23 c, and 23 d designate bunches of planar ridge waveguides. Each such bunch contains four planar ridge waveguides for different wavelengths.

FIG. 3 is a more detailed top view of the auxiliary microchip DHP 1 . In this drawing, the striped area is the digital planar hologram H 1 of the auxiliary holographic microchip DPH 1 , which is described in more detail later. Reference numeral 28 designates the aforementioned planar ridge waveguide that delivers the monochromatic laser lights to the inputs (not shown in FIGS. 1 and 3 ) of the auxiliary holographic microchip DPH 1 . Reference numerals 30 a, 30 b, 30 c, and 30 d designate planar ridge waveguides through which the aforementioned monochromatic lights are delivered to data-processing cores 24 a, 24 b, 24 c, and 24 d that use the lights of the corresponding wavelengths for communication with the other data-processing cores 24 a, 24 b, 24 c, and 24 d formed on the substrate 22 of the multicore chip 20 . In FIGS. 2 and 3 , the arrows I x1 , I x2 , I x3 , and I X4 show directions of the lights propagating through the respective waveguides.

The topology of the digital planar hologram H 1 is organized so that the light components with the wavelengths λ 1 , λ 2 , λ 3 , and λ 4 are collected on the inputs of the planar ridge waveguides 30 a, 30 b, 30 c, and 30 d and, after being processed by the digital planar hologram H 1 , propagate through these waveguides 30 a, 30 b, 30 c, and 30 d to the data-processing cores 24 a, 24 b, 24 c, and 24 d.

In other words, the digital planar hologram H 1 comprises a plurality of nano-features that modulate the refractive indices of planar waveguides where propagating lights are confined. The nano-features are positioned in a manner to provide resonant reflection of lights of predefined wavelengths so that multiple wavelengths are reflected to the assigned output ports and then propagate toward the inputs of the cores. The topology of the digital planar hologram H 1 is defined by solving the set of appropriate equations of the type presented in the above-mentioned U.S. Pat. No. 7,889,336 with the boundary conditions that correspond to inputs and outputs of the optical planar ridge waveguides 28 , 30 a, 30 b, 30 c, and 30 d ( FIG. 3 ).

Each data-processing core 24 a, 24 b, 24 c, and 24 d is provided with an optical modulators/transceivers, such as T x1 , T x2 , T x3 , and T x4 , respectively, that is intended for converting the core data into an optical form of modulated optical signals I x1 , I x2 , I x3 , and I x4 ( FIG. 2 ). In other words, the optical modulator/transceivers T x1 , T x2 , T x3 , and T x4 have a function of coding the obtained optical signals by modulating them with the core-generated data.

The holographic microchip DPH 2 , which is the main or indispensible holographic microchip, has a plurality of inputs which are intended for receiving the modulated signals I x1 , I x2 , I x3 , and I x4 and I x4 from the cores 24 a, 24 b, 24 c, and 24 d transmitted by their respective modulator/transceivers T x1 , T x2 , T x3 , and T x4 on respective wavelengths λ 1 , λ 2 , λ 3 , and λ 4 ( FIG. 2 ). The DPH 2 contains a main digital planar hologram H 2 of the type similar to the digital planar hologram H 1 of the DPH 1 . The DPH 2 takes the modulated signals obtained from each core, splits each of them into three copies, and delivers a copy of each modulated signal to all the cores except the core from which the copies are sent. More specifically, as shown in FIG. 2 , the core 24 a receives three modulated signals S 2 , S 3 , and S 4 on the wavelengths λ 2 , λ 3 , and λ 4 ; the core 24 b receives three modulated signals on the wavelengths λ 1 , λ 3 , and λ 4 ; the core 24 c receives three modulated signals on the wavelengths λ 1 , λ 2 , and λ 4 ; and the core 24 d receives three modulated signals on the wavelengths λ 1 , λ 2 , and λ 3 ( FIG. 2 ).

The aforementioned modulated signals I x1 , I x2 , I x3 , and I x4 are delivered from the cores 24 a, 24 b, 24 c, and 24 d to the main holographic chip DPH 2 via the respective input plane ridge waveguides 34 a, 34 b, 34 c, and 34 d. This is shown in FIG. 4 , which is a plan view of the area A of the main holographic microchip DPH 2 , which is shown on a larger scale than in FIG. 2 . More specifically, this drawing shows the main holographic microchip DPH 2 and four triplets of signal copies for the light of each wavelength. Thus, waveguides 32 b 1 , 32 c 1 , and 32 d 1 deliver three signals I x2 , I x3 , and I x4 of wavelength λ 2 , λ 3 , and λ 4 ; waveguides 32 a 2 , 32 c 2 , and 32 d 2 deliver three signals i x1 , I x3 , and I x4 of wavelength λ 1 , λ 3 , and λ 4 ; waveguides 32 a 3 , 32 b 3 , and 32 d 3 deliver three signals I x1 , I x2 , and I x4 of wavelength λ 1 , λ 2 , and λ 4 ; and waveguides 32 a 4 , 32 b 4 , and 32 c 4 deliver three signals I x1 , I x2 , and I x3 of wavelength λ 1 , λ 2 , and λ 3 .

Referring again to the waveguide bunches 23 a, 23 b, 23 d and 23 c, it should be noted that the bunch 23 a comprises the waveguides 34 a, 32 b 1 , 32 c 1 , and 32 d 1 . The bunch 23 b comprises the waveguides 34 b, 32 a 2 , 32 c 2 , and 32 d 2 . The bunch 23 c comprises the waveguides 34 c, 32 a 3 , 32 b 3 , and 32 d 3 . The bunch 23 d comprises the waveguides 34 d, 32 a 4 , 32 b 4 , and 32 c 4 ( FIG. 1 and FIG. 4 ).

FIG. 5 is a top view of the main holographic microchip DPH 2 that conventionally illustrates the process of copying of the modulated signals I x1 , Ix 2 , I x3 , and I x4 that are delivered to the digital planar hologram H 2 of the main holographic microchip DPH 2 from the data-processing cores 24 a, 24 b, 24 c, and 24 d ( FIG. 1 ). Although, similar to the digital planar hologram H 1 of the auxiliary holographic microchip DPH 2 , the digital planar hologram H 2 of the main holographic microchip DPH 2 comprises a plurality of nano-features in the form, e.g., of dashes, their topology is defined by a different function and therefore is essentially different. More specifically, according to the invention, the pattern of the nano-features of the digital planar hologram H 2 is defined by the variation Δn(x, y) of the effective refractive index of the two-dimensional planar waveguide in accordance with formula:

Δ n ( x, y )=∫ f in ( x, y, ω) f out ( x, y, ω) dω,

where f in (x, y, Ω) and f out (x, y, ω) are Fourier components of desirable incoming and outgoing waves,

f i ⁢ ⁢ n ⁡ ( x , y , ω ) ≅ ∑ n ⁢ C n ⁢ exp ⁡ ( ⅈ ⁢ ⁢ k n ⁢ r n ) ⁢ f ⁡ ( ω ) f out ⁡ ( x , y , ω ) ≅ ∑ m ⁢ C m ⁢ exp ⁡ ( - ⅈ ⁢ ⁢ k m ⁢ r m ) ⁢ f ⁡ ( ω ) ,

where k n and k m are wave vectors designated to the interconnections number n and m, and r n and r m are the distances from the incoming and outgoing ports of detectors and modulators, respectively.

The modulators/transceivers of the data-processing cores ( FIG. 2 ) are prescribed an individual lambda and frequency, so that the core m is prescribed frequency ω m , hence f(ω)

in

f out ⁡ ( x , y , ω ) ≅ ∑ m ⁢ C m ⁢ exp ⁡ ( - ⅈ ⁢ ⁢ k m ⁢ r m ) ⁢ f ⁡ ( ω )

can be approximated by the delta function f(ω)=δ(ω−ω m ).

The variation of the effective refractive index Δn(x, y) may be approximated by a composition of simplified binary structures, for example, rectangular dashes.

Furthermore, the variation of the effective refractive index Δn(x, y) may also be approximated by a composition of simplified binary structures, placed near maxima or minima of the original variation of the effective refractive index Δn(x, y) given by the above formula.

The system operates in the following way.

The input waveguide 28 receives four different monochromatic laser lights having wavelengths λ 1 , λ 2 , λ 3 , and λ 4 ( FIG. 2 ) from the laser light sources 26 , e.g., laser diodes, and delivers them to the auxiliary holographic microchip DPH 1 , where these component lights are spatially split and sent to the cores 24 a, 24 b, 24 c, and 24 d via the ridge waveguides 30 a, 30 b, 30 d, and 30 c, respectively ( FIGS. 1 and 3 ). As mentioned above, the cores 24 a, 24 b, 24 c, and 24 d contain optical modulators/transceivers T x1 , T x2 , T x3 , and T x4 that convert the data signals generated by the respective cores by modulating the assigned lights of the corresponding wavelengths into optical signals I x1 , I x2 , I x3 , and I x3 . These signals are sent to the main holographic microchip DPH 2 ( FIGS. 4 and 5 ) via the planar ridge waveguide 34 a, 34 b, 34 c, and 34 d. The digital planar hologram H 2 of the DPH 2 splits the optical signal obtained from each data-processing core into a plurality of signal copies, three in the illustrated case, and each signal copy is sent to all other data-processing cores, i.e., to the cores other than one that generates the original signal. More specifically, the modulated signal I x1 obtained from the core 24 a is split into three signals S 1 ′, S 1 ″, and S 1 ′″ that are delivered to the data-processing cores 24 b, 24 c, and 24 d via ridge waveguides 32 b 1 , 32 c 1 , and 32 d 1 , respectively. The modulated signal I x2 obtained from the core 24 b is split into three signals S 2 ′, S 2 ″, and S 2 ′″ that are delivered to the data-processing cores 24 a, 24 c, and 24 d via ridge waveguides 32 a 2 , 32 c 2 , and 32 d 2 , respectively. The modulated signal I x3 obtained from the core 24 c is split into three signals S 3 ′, S 3 ″, and S 3 ′″ that are delivered to the data-processing cores 24 a, 24 b, and 24 d via ridge waveguides 32 a 3 , 32 b 3 , and 32 d 3 , respectively. The modulated signal I x4 obtained from the core 24 d is split into three signals S 4 ′, S 4 ″, and S 4 ′″ that are delivered to the data-processing cores 24 a, 24 b, and 24 c via ridge waveguides 32 a 4 , 32 b 4 , and 32 c 4 , respectively ( FIGS. 2 and 4 ). Each core has three independent optical signal receivers each of which receives signals from one of three remaining cores. In other words, the data-processing core 24 a receives the respective copy signals to receivers R ax2 , R ax3 , and R ax4 ; the data-processing core 24 b receives the respective copy signals to receivers R bx1 , R bx3 , and R bx4 ; the data-processing core 24 c receives the respective copy signals to receivers R cx1 , R cx2 , and R cx4 ; and the data-processing core 24 d receives the respective copy signals to receivers R dx1 , R dx2 , and R dx4 .

The invention is efficient in that it allows replacing the electrical interconnections for core communication with optical interconnections by employing holographic microchips that perform the aforementioned interconnection in a single functional layer structure. This makes it possible to exclude communication-line cross and thus to significantly reduce crosstalks. It is understood that this architecture is scalable up to a dozen of processing cores or even more. Furthermore, in this case it becomes more efficient to have a hierarchy of interconnections, instead of the flat each-to-each configuration. All of the discussed patterns can be also realized with a single holographic microchip.

Although the invention has been described with reference to specific examples, it is understood that the invention is not limited by the given examples and any changes and modifications are possible without departure from the scope of the claims given below. For example, the number and mutual position of the data-processing cores on the chip may be different from those shown in the drawings, and the cores can be used in an amount less than four or greater than four. The modulators/transceivers may be formed directly in the pattern of the data-processing core or beyond the limits of the data-processing core and linked thereto by electrical interconnects.