Method for producing a two-chip assembly and corresponding two-chip assembly

1. Field of the Invention

The present invention relates to a method for producing a two-chip assembly, and a corresponding two-chip assembly.

2. Description of the Related

Although any micromechanical or microelectronic components are also usable, the present invention and the problem underlying it are explained on the basis of micromechanical sensor devices.

These days, micromechanical sensor devices for consumer applications are packaged predominantly in QFN (Quad Flat No Leads)-, LGA (Land Grid Array)- or BGA (Ball Grid Array)-packages. In so doing, space is needed on the side for the formation of wire bonds. In the case of single chips, Wafer Level Packages (WLP), also known as Wafer-Level Chip-Size Packages (WL-CSP), are beginning to win favor.

The U.S. Pat. Nos. 7,838,975 and 7,446,405 describe Wafer-Level Chip-Size Packages.

The present invention permits a robust production of a two-chip assembly as a chip-size package, because the back of the wafer is thinned and the vias are applied from the back side only after the cohesive one-sided mold package has been produced. Wafer breakage and reduced yield are able to be avoided by the procedure of the present invention.

FIGS. 1 a to 1 g show schematic cross-sectional views for explaining a method for producing a two-chip assembly in the form of a micromechanical sensor device according to an example embodiment of the present invention.

In the figures, identical reference symbols denote identical or functionally equivalent elements.

In FIG. 1 a ), reference numeral 1 denotes a silicon wafer having a front side VS and a back side RS. A plurality of first chips 1 a , 1 b , 1 c , which are ASIC chips, is provided in silicon wafer 1 . On front side VS, first chips 1 a , 1 b , 1 c have pairs of first electrical connection areas M 1 , M 2 and M 3 , M 4 and M 5 , M 6 , respectively.

Reference numeral 10 denotes an alignment device, e.g., alignment marks or pattern, applied on front side VS of wafer 1 .

Continuing with reference to FIG. 1 b ), a corresponding plurality of second chips 2 a , 2 b , 2 c is mounted on front side VS of wafer 1 using customary processes, so that every first chip 1 a , 1 b , 1 c is joined in each instance to a second chip 2 a , 2 b , 2 c and forms a corresponding two-chip pair. During mounting, the pairs of first electrical connection areas M 1 , M 2 and M 3 , M 4 and M 5 , M 6 are connected to corresponding pairs of second connection areas 21 , 22 and 23 , 24 and 25 , 26 , respectively, of second chips 2 a , 2 b , 2 c.

In the present specific embodiment, second chips 2 a , 2 b , 2 c , which in the present case are micromechanical sensor chips, are mounted using flip-chip technology, front side VS′ of second chips 2 a , 2 b , 2 c pointing toward front side VS of wafer 1 , and back side RS′ of second chips 2 a , 2 b , 2 c facing away from it.

It is equally possible to bond chips 2 a , 2 b , 2 c adhesively onto front side VS of wafer 1 and to contact them using wire bond connections.

Continuing with reference to FIG. 1 c ), a cohesive, one-sided mold package MG is subsequently formed on front side VS of wafer 1 in such a way that second chips 2 a , 2 b , 2 c are packaged. This is accomplished in a customary injection molding process such as transfer molding or compression molding, or in a customary casting process. The molding stabilizes wafer 1 sufficiently for the following process steps. Preferably, during the molding-over process, the wafer edge is used for holding down in the tool, and thus is kept free of molding compound. Alignment device 10 is not molded over, since it is needed in the following process steps.

Continuing with reference to FIG. 1 d ), wafer 1 is then thinned by a grinding process starting from back side RS, in doing which, wafer 1 is backthinned from first thickness d 1 to second thickness d 2 , typical values for d 1 being between 600 μm and 800 μm, and for d 2 , being between 50 and 150 μm.

In the following process step, which is illustrated in FIG. 1 e ), vias D 1 , D 2 , D 3 , D 4 , D 5 , D 6 to first electrical connection areas M 1 , M 2 , M 3 , M 4 , M 5 , M 6 are formed starting from back side RS, in doing which, first connection areas M 1 to M 6 are used as stop surfaces. The vias are formed using customary lithographic etching technology.

In order to align vias D 1 to D 6 with the corresponding target structures on front side VS, alignment device 10 may be used, or alternatively or additionally, the front side may be viewed in reflection with infrared. In order for alignment device 10 to be visible in this step, mold package MG does not extend to alignment device 10 .

Continuing with reference to FIG. 1 f ), after forming vias D 1 to D 6 , third electrical connection areas U 1 to U 6 are formed on the back side and may also be provided with a wiring around (not shown); at the end, solder bumps 11 , 12 , 13 , 14 , 15 , 16 are provided on third electrical connection areas U 1 to U 6 . After that, the two-chip pairs, having chips 1 a , 2 a and 1 b , 2 b and 1 c , 2 c , respectively, are separated into corresponding two-chip assemblies.

FIG. 1 g ) shows the final product in the form of a two-chip assembly 3 a having chips 1 a , 2 a.