Level shift circuit

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2011-163450, filed on Jul. 26, 2011; the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to level shift circuits.

In some semiconductor devices, in order to optimize the characteristics of an internal circuit, the level of an external power supply voltage is shifted and then supplied to the internal circuit. At that time, when there is a large difference between the delay time of the rising edge of an output voltage and the delay time of the falling edge of the output voltage, the deviation of the duty ratio of the output voltage increases, which results in a large reduction in operation margin.

FIG. 1 is a block diagram illustrating the schematic structure of a level shift circuit according to a first embodiment;

FIG. 2 is a circuit diagram illustrating the schematic structure of a level shift circuit according to a second embodiment;

FIG. 3 is a timing chart illustrating the voltage waveform of each unit in the level shift circuit shown in FIG. 2 ;

FIG. 4 is a circuit diagram illustrating the delay of each node when an input voltage INPUT to an inverter M 11 falls in the level shift circuit shown in FIG. 2 ;

FIG. 5 is a circuit diagram illustrating the delay of each node when the input voltage INPUT to the inverter M 11 rises in the level shift circuit shown in FIG. 2 ;

FIG. 6 is a circuit diagram illustrating the schematic structure of a level shift circuit according to a third embodiment;

FIG. 7 is a timing chart illustrating the voltage waveform of each unit in the level shift circuit shown in FIG. 6 ;

FIG. 8 is a circuit diagram illustrating the schematic structure of a level shift circuit according to a fourth embodiment;

FIG. 9 is a timing chart illustrating the voltage waveform of each unit in the level shift circuit shown in FIG. 8 ;

FIG. 10 is a circuit diagram illustrating the schematic structure of a level shift circuit according to a fifth embodiment;

FIG. 11 is a circuit diagram illustrating the schematic structure of a level shift circuit according to a sixth embodiment;

FIG. 12 is a circuit diagram illustrating the schematic structure of a level shift circuit according to a seventh embodiment;

FIG. 13 is a circuit diagram illustrating the delay of each node when an input voltage INPUT to an inverter M 11 falls in a level shift circuit according to an eighth embodiment;

FIG. 14 is a circuit diagram illustrating the delay of each node when the input voltage INPUT to the inverter M 11 rises in the level shift circuit shown in FIG. 13 ;

FIG. 15 is a block diagram illustrating the schematic structure of a semiconductor device according to a ninth embodiment to which the level shift circuit is applied;

FIG. 16A is a block diagram illustrating the schematic structure of a semiconductor memory device according to a tenth embodiment to which the level shift circuit is applied;

FIG. 16B is a perspective view illustrating the schematic structure of a NAND memory 3 - 1 shown in FIG. 16A ;

FIG. 16C is a perspective view illustrating the schematic structure of a semiconductor chip CP 1 of the NAND memory 3 - 1 shown in FIG. 16B ;

FIG. 17 is a perspective view illustrating an example of the schematic structure of the NAND memory 3 - 1 shown in FIG. 16A ; and

FIG. 18 is a timing chart illustrating the operation of a semiconductor memory device according to an eleventh embodiment to which the level shift circuit is applied in the toggle mode.

In general, according to an embodiment, a level shift circuit includes a plurality of level shift units which are connected to each other and in which the delay time of the rising edge of an output voltage is different from the delay time of the falling edge of the output voltage. The delay time of the rising edge of the output voltage from the previous level shift unit is compensated by the delay time of the falling edge of the output voltage from the next level shift unit, and the delay time of the falling edge of the output voltage from the previous level shift unit is compensated by the delay time of the rising edge of the output voltage from the next level shift unit.

Exemplary embodiments of the level shift circuit will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.

First Embodiment

FIG. 1 is a block diagram illustrating the schematic structure of a level shift circuit according to a first embodiment.

In FIG. 1 , the level shift circuit includes level shift units F 1 and F 2 , and the level shift unit F 2 is connected to the rear stage of the level shift unit F 1 . An inverter M 1 is connected to the rear stage of the level shift unit F 2 .

The level shift unit F 1 can shift the level of an output voltage between a first power supply potential VSS and a second power supply potential VCCQ 1 . The level shift unit F 2 can shift the level of the output voltage between the first power supply potential VSS and a third power supply potential VCCQ 2 . The inverter M 1 can invert the output voltage between the first power supply potential VSS and the third power supply potential VCCQ 2 .

The first power supply potential VSS, the second power supply potential VCCQ 1 , and the third power supply potential VCCQ 2 may satisfy the relationship VSS<VCCQ 1 ≦VCCQ 2 and the second power supply potential VCCQ 1 may be equal to the third power supply potential VCCQ 2 . In addition, the first power supply potential VSS may be a ground potential.

In each of the level shift units F 1 and F 2 , the delay time of the rising edge of the output voltage is different from the delay time of the falling edge of the output voltage.

The delay time of the rising edge of the output voltage means a delay time from the rise of the input voltage to the rise of the output voltage, and the delay time of the falling edge of the output voltage means a delay time from the fall of the input voltage to the fall of the output voltage.

The delay time of the rising edge of the output voltage is not limited to the time from a 100 percent rise in the level of the input voltage from the bottom to the top to a 100 percent rise in the level of the output voltage from the bottom to the top, but it may be arbitrarily defined. For example, the delay time of the rising edge of the output voltage may be the time from a 50 percent rise in the level of the input voltage from the bottom to a 50 percent rise in the level of the output voltage from the bottom.

The delay time of the falling edge of the output voltage is not limited to the time from a 100 percent fall in the level of the input voltage from the top to the bottom to a 100 percent fall in the level of the output voltage from the top, but it may be arbitrarily defined. For example, the delay time of the falling edge of the output voltage may be the time from a 50 percent fall in the level of the input voltage from the top to a 50 percent fall in the level of the output voltage from the top.

The level shift circuit can compensate the delay time of the rising edge of the output voltage from the previous level shift unit F 1 with the delay time of the falling edge of the output voltage from the next level shift unit F 2 and compensate the delay time of the falling edge of the output voltage from the previous level shift unit F 1 with the delay time of the rising edge of the output voltage from the next level shift unit F 2 .

When an input voltage V 1 with an amplitude VDD is input to the level shift unit F 1 , the level of the input voltage V 1 shifts to an output voltage V 2 with an amplitude VCCQ 1 and the output voltage V 2 is then input to the level shift unit F 2 . The voltage VDD may be less than the voltage VCCQ 1 .

In the level shift unit F 2 , the level of the output voltage V 2 with the amplitude VCCQ 1 shifts to an output voltage V 3 with an amplitude VCCQ 2 and the output voltage V 3 is input to the inverter M 1 . Then, the inverter M 1 inverts the output voltage V 3 from the level shift unit F 2 and an output voltage V 4 is output from the inverter M 1 .

It is assumed that, in the level shift unit F 1 , the delay time of the falling edge ED 2 of the output voltage V 2 is more than that of the rising edge EU 2 and, in the level shift unit F 2 , the delay time of the falling edge ED 3 of the output voltage V 3 is more than that of the rising edge EU 3 .

At that time, it is assumed that, in the level shift unit F 1 , the falling edge ED 2 of the output voltage V 2 is generated according to the rising edge EU 1 of the input voltage V 1 and the rising edge EU 2 of the output voltage V 2 is generated according to the falling edge ED 1 of the input voltage V 1 . In this case, the amount of delay of the falling edge ED 2 relative to the rising edge EU 1 is less than the amount of delay of the rising edge EU 2 relative to the falling edge ED 1 .

It is assumed that, in the level shift unit F 2 , the rising edge EU 3 of the output voltage V 3 is generated according to the falling edge ED 2 of the input voltage V 2 , and the falling edge ED 3 of the output voltage V 3 is generated according to the rising edge EU 2 of the input voltage V 2 . In this way, the amount of delay of the falling edge ED 3 relative to the rising edge EU 2 is less than that of the rising edge EU 3 relative to the falling edge ED 2 .

As a result, the amount of delay of the rising edge EU 2 relative to the falling edge ED 1 which is more than that of the falling edge ED 2 relative to the rising edge EU 1 can be compensated by the amount of delay of the rising edge EU 3 relative to the falling edge ED 2 which is less than that of the falling edge ED 3 relative to the rising edge EU 2 .

Therefore, assuming that the falling edge ED 4 of the output voltage V 4 is generated according to the rising edge EU 3 of the output voltage V 3 and the rising edge EU 4 of the output voltage V 4 is generated according to the falling edge ED 3 of the output voltage V 3 , the inverter M 1 can make the amount of delay of the falling edge ED 4 relative to the rising edge EU 1 close to the amount of delay of the rising edge EU 4 relative to the falling edge ED 1 .

In the above-described embodiment, two level shift units are connected to each other. However, the even-numbered level shift units may be connected to each other.

Second Embodiment

FIG. 2 is a circuit diagram illustrating the schematic structure of a level shift circuit according to a second embodiment.

In FIG. 2 , the level shift circuit includes level shift units F 11 and F 12 , and the level shift unit F 12 is connected to the rear stage of the level shift unit F 11 . An inverter M 12 is connected to the front stage of the level shift units F 11 and F 12 , an inverter M 11 is connected to the front stage of the inverter M 12 , and an inverter M 13 is connected to the rear stage of the level shift unit F 12 .

The level shift unit F 11 can shift the level of an output voltage between a first power supply potential VSS and a second power supply potential VCCQ 1 . The level shift unit F 12 can shift the level of an output voltage between the first power supply potential VSS and a third power supply potential VCCQ 2 . The inverters M 11 and M 12 can invert the output voltage between the first power supply potential VSS and a fourth power supply potential VDD. The inverter M 13 can invert the output voltage between the first power supply potential VSS and the third power supply potential VCCQ 2 .

In each of the level shift units F 11 and F 12 , the delay time of the rising edge of the output voltage is different from the delay time of the falling edge of the output voltage. The level shift unit F 11 can perform a level shift operation on the basis of input voltages IN and INn. The input voltage IN is an inverted voltage of the input voltage INn. The input voltages IN and INn can be used as differential input voltages. The level shift unit F 12 can perform a level shift operation using the input voltage IN to the level shift unit F 11 and the output voltage I 2 from the level shift unit F 11 as differential input voltages.

The inverter M 11 includes a P-channel field effect transistor P 1 and an N-channel field effect transistor N 1 . The inverter M 12 includes a P-channel field effect transistor P 2 and an N-channel field effect transistor N 2 . The inverter M 13 includes a P-channel field effect transistor P 3 and an N-channel field effect transistor N 3 .

The level shift unit F 11 includes P-channel field effect transistors P 11 to P 14 and N-channel field effect transistors N 11 and N 12 . The level shift unit F 12 includes P-channel field effect transistors P 15 to P 18 and N-channel field effect transistors N 15 and N 16 .

The source of the P-channel field effect transistor P 1 is connected to the fourth power supply potential VDD. The drain of the P-channel field effect transistor P 1 is connected to the drain of the N-channel field effect transistor N 1 . The source of the N-channel field effect transistor N 1 is connected to the first power supply potential VSS. The gate of the P-channel field effect transistor P 1 is connected to the gate of the N-channel field effect transistor N 1 .

The source of the P-channel field effect transistor P 2 is connected to the fourth power supply potential VDD. The drain of the P-channel field effect transistor P 2 is connected to the drain of the N-channel field effect transistor N 2 . The source of the N-channel field effect transistor N 2 is connected to the first power supply potential VSS. The gate of the P-channel field effect transistor P 2 and the gate of the N-channel field effect transistor N 2 are connected to the drain of the P-channel field effect transistor P 1 .

The sources of the P-channel field effect transistors P 11 and P 12 are connected to the second power supply potential VCCQ 1 . The drain of the P-channel field effect transistor P 11 is connected to the source of the P-channel field effect transistor P 13 . The drain of the P-channel field effect transistor P 13 is connected to the drain of the N-channel field effect transistor N 11 . The drain of the P-channel field effect transistor P 12 is connected to the source of the P-channel field effect transistor P 14 . The drain of the P-channel field effect transistor P 14 is connected to the drain of the N-channel field effect transistor N 12 . The sources of the N-channel field effect transistors N 11 and N 12 are connected to the first power supply potential VSS.

The gate of the P-channel field effect transistor P 11 and the gate of the N-channel field effect transistor N 11 are connected to the drain of the P-channel field effect transistor P 2 . The gate of the P-channel field effect transistor P 12 and the gate of the N-channel field effect transistor N 12 are connected to the drain of the P-channel field effect transistor P 1 . The gate of the P-channel field effect transistor P 13 is connected to the drain of the P-channel field effect transistor P 14 . The gate of the P-channel field effect transistor P 14 is connected to the drain of the P-channel field effect transistor P 13 .

The sources of the P-channel field effect transistors P 15 and P 16 are connected to the third power supply potential VCCQ 2 . The drain of the P-channel field effect transistor P 15 is connected to the source of the P-channel field effect transistor P 17 . The drain of the P-channel field effect transistor P 17 is connected to the drain of the N-channel field effect transistor N 15 . The drain of the P-channel field effect transistor P 16 is connected to the source of the P-channel field effect transistor P 18 . The drain of the P-channel field effect transistor P 18 is connected to the drain of the N-channel field effect transistor N 16 . The sources of the N-channel field effect transistors N 15 and N 16 are connected to the first power supply potential VSS.

The gate of the P-channel field effect transistor P 15 and the gate of the N-channel field effect transistor N 15 are connected to the drain of the P-channel field effect transistor P 13 . The gate of the P-channel field effect transistor P 16 and the gate of the N-channel field effect transistor N 16 are connected to the drain of the P-channel field effect transistor P 2 . The gate of the P-channel field effect transistor P 17 is connected to the drain of the P-channel field effect transistor P 18 . The gate of the P-channel field effect transistor P 18 is connected to the drain of the P-channel field effect transistor P 17 .

The source of the P-channel field effect transistor P 3 is connected to the third power supply potential VCCQ 2 . The drain of the P-channel field effect transistor P 3 is connected to the drain of the N-channel field effect transistor N 3 . The source of the N-channel field effect transistor N 3 is connected to the first power supply potential VSS. The gate of the P-channel field effect transistor P 3 and the gate of the N-channel field effect transistor N 3 are connected to the drain of the P-channel field effect transistor P 17 .

FIG. 3 is a timing chart illustrating the voltage waveform of each unit in the level shift circuit shown in FIG. 2 .

In FIG. 3 , when an input voltage INPUT is input to the inverter M 11 , the inverter M 11 inverts the input voltage INPUT to generate the input voltage INn and outputs the input voltage INn to the inverter M 12 and the level shift unit F 11 .

Then, when the input voltage INn is input to the inverter M 12 , the inverter M 12 inverts the input voltage INn to generate the input voltage IN and outputs the input voltage IN to the level shift unit F 11 . The amplitudes of the input voltages INPUT, INn, and IN are maintained at VDD.

Then, the level shift unit F 11 performs a level shift operation using the input voltages INn and IN as the differential input voltages to generate an output voltage 12 with an amplitude VCCQ 1 . The output voltage I 2 is input to the level shift unit F 12 .

Then, the level shift unit F 12 performs a level shift operation using the input voltage IN to the level shift unit F 11 and the output voltage I 2 from the level shift unit F 11 as the differential input voltages to generate an output voltage b 2 with an amplitude VCCQ 2 . The output voltage b 2 is input to the inverter M 13 .

Then, the inverter M 13 inverts the output voltage b 2 from the level shift unit F 12 and outputs an output voltage OUTn.

In the level shift unit F 11 , when the input voltage INn is at an “L” level and the input voltage IN is at an “H” level, the P-channel field effect transistors P 12 and P 14 and the N-channel field effect transistor N 11 are turned on and the P-channel field effect transistors P 11 and P 13 and the N-channel field effect transistor N 12 are turned off. Therefore, the output voltage I 2 from the level shift unit F 11 is reduced to the first power supply potential VSS through the N-channel field effect transistor N 11 and changes to an “L” level.

In the level shift unit F 11 , when the input voltage INn is at an “H” level and the input voltage IN is at an “L” level, the P-channel field effect transistors P 12 and P 14 and the N-channel field effect transistor N 11 are turned off and the P-channel field effect transistors P 11 and P 13 and the N-channel field effect transistor N 12 are turned on. Therefore, the output voltage I 2 from the level shift unit F 11 is raised to the second power supply potential VCCQ 1 through the P-channel field effect transistors P 11 and P 13 and changes to an “H” level. The delay time of the rising edge EU 11 of the output voltage I 2 is more than the delay time of the falling edge ED 11 .

In the level shift unit F 12 , when the input voltage IN is at the “L” level and the output voltage I 2 is at the “H” level, the P-channel field effect transistors P 16 and P 18 and the N-channel field effect transistor N 15 are turned on and the P-channel field effect transistors P 15 and P 17 and the N-channel field effect transistor N 16 are turned off. Therefore, the output voltage b 2 from the level shift unit F 12 is reduced to the first power supply potential VSS through the N-channel field effect transistor N 15 and changes to an “L” level.

In the level shift unit F 12 , when the input voltage IN is at the “H” level and the output voltage I 2 is at the “L” level, the P-channel field effect transistors P 16 and P 18 and the N-channel field effect transistor N 15 are turned off and the P-channel field effect transistors P 15 and P 17 and the N-channel field effect transistor N 16 are turned on. Therefore, the output voltage b 2 from the level shift unit F 12 is raised to the third power supply potential VCCQ 2 through the P-channel field effect transistors P 15 and P 17 and changes to an “H”. The delay time of the rising edge EU 12 of the output voltage b 2 is more than the delay time of the falling edge ED 12 .

Therefore, the delay time of the falling edge ED 11 of the output voltage I 2 from the previous level shift unit F 11 can be compensated by the delay time of the rising edge EU 12 of the output voltage b 2 from the next level shift unit F 12 , and the delay time of the rising edge EU 11 of the output voltage I 2 from the previous level shift unit F 11 can be compensated by the delay time of the falling edge ED 12 of the output voltage b 2 from the next level shift unit F 12 . As a result, it is possible to reduce the deviation of the duty ratio of the output voltage OUTn to the input voltage INPUT, as compared to the deviation of the duty ratio of the output voltage I 2 to the input voltage INPUT. Therefore, it is possible to prevent a reduction in operation margin.

FIG. 4 is a circuit diagram illustrating the delay of each node when the input voltage INPUT to the inverter M 11 falls in the level shift circuit shown in FIG. 2 . In the example shown in FIG. 4 , the delay time corresponding to one transistor is 1 and the delay time of each node is shown together with the level.

In FIG. 4 , when the input voltage INPUT is at an “L” level and the delay time is 1, the input voltage INn is delayed by a value corresponding to one transistor of the inverter M 11 and rises. Therefore, the input voltage INn is at an “H” level and the delay time is 2. When the input voltage INn is at the “H” level, the drain potential of the P-channel field effect transistor P 14 is delayed by a value corresponding to one transistor of the level shift unit F 11 and falls. Therefore, the drain potential of the P-channel field effect transistor P 14 is at an “L” level and the delay time is 3. The P-channel field effect transistor P 13 is turned on.

When the input voltage INn is at the “H” level, the input voltage IN is delayed by a value corresponding to one transistor of the inverter M 12 and falls. Therefore, the input voltage IN is at an “L” level and the delay time is 3. When the input voltage IN is at the “L” level, the drain potential of the P-channel field effect transistor P 11 is delayed by a value corresponding one transistor of the level shift unit F 11 and rises. Therefore, the drain potential of the P-channel field effect transistor P 11 is at an “H” level and the delay time is 4. When the P-channel field effect transistor P 13 is turned on and the drain potential of the P-channel field effect transistor P 11 is at the “H” level, the output voltage I 2 is delayed by a value corresponding to one transistor of the level shift unit F 11 and rises. Therefore, the output voltage I 2 is at an “H” level and the delay time is 5.

When the output voltage I 2 is at the “H” level, the output voltage b 2 is delayed by a value corresponding to one transistor of the level shift unit F 12 and falls. Therefore, the output voltage b 2 is at an “L” level and the delay time is 6. When the output voltage b 2 is at the “L” level, the output voltage OUTn is delayed by a value corresponding to one transistor of the inverter M 13 and rises. Therefore, the output voltage OUTn is at an “H” level and the delay time is 7.

FIG. 5 is a circuit diagram illustrating the delay of each node when the input voltage INPUT of the inverter M 11 rises in the level shift circuit shown in FIG. 2 . In the example shown in FIG. 5 , the delay time corresponding to one transistor is 1 and the delay time of each node is shown together with the level.

In FIG. 5 , when the input voltage INPUT is at an “H” level and the delay time is 1, the input voltage INn is delayed by a value corresponding to one transistor of the inverter M 11 and falls. Therefore, the input voltage INn is at an “L” and the delay time is 2. When the input voltage INn is at the “L” level, the drain potential of the P-channel field effect transistor P 12 is delayed by a value corresponding to one transistor of the level shift unit F 11 and rises. Therefore, the drain potential of the P-channel field effect transistor P 12 is at an “H” level and the delay time is 3.

When the input voltage INn is at the “L” level, the input voltage IN is delayed by a value corresponding to one transistor of the inverter M 12 and rises. Therefore, the input voltage IN is at an “H” level and the delay time is 3. When the input voltage IN is at the “H” level, the output voltage I 2 is delayed by a value corresponding to one transistor of the level shift unit F 11 and falls. Therefore, the output voltage I 2 is at an “L” level and the delay time is 4. When the drain potential of the P-channel field effect transistor P 12 is at an “H” level and the output voltage I 2 is at an “L” level, the drain potential of the P-channel field effect transistor P 14 is delayed by a value corresponding to one transistor of the level shift unit F 11 and rises. Therefore, the drain potential of the P-channel field effect transistor P 14 is at the “H” level and the delay time is 5.

When the input voltage IN is at the “H” level, the drain potential of the P-channel field effect transistor P 18 is delayed by a value corresponding to one transistor of the level shift unit F 12 and falls. Therefore, the drain potential of the P-channel field effect transistor P 18 is at an “L” level and the delay time is 4. The P-channel field effect transistor P 17 is turned on.

When the output voltage I 2 is at the “L” level, the drain potential of the P-channel field effect transistor P 15 is delayed by a value corresponding to one transistor of the level shift unit F 12 and rises. Therefore, the drain potential of the P-channel field effect transistor P 15 is at an “H” level and the delay time is 5. When the P-channel field effect transistor P 17 is turned on and the drain potential of the P-channel field effect transistor P 15 is at the “H”, the output voltage b 2 is delayed by a value corresponding to one transistor of the level shift unit F 12 and rises. Therefore, the output voltage b 2 is at an “H” level and the delay time is 6. When the output voltage b 2 is at the “H” level, the output voltage OUTn is delayed by a value corresponding to one transistor of the inverter M 13 and falls. Therefore, the output voltage OUTn is at an “L” level and the delay time is 7.

When the input voltage IN is input to the gate of the N-channel field effect transistor N 16 , the gate voltage of the P-channel field effect transistor P 17 can fall before the source potential of the P-channel field effect transistor P 17 rises. Therefore, before the source potential of the P-channel field effect transistor P 17 rises, the P-channel field effect transistor P 17 can be turned on. The number of stages of the delay of the transistor for the time from the rise of the input voltage INPUT to the rise of the output voltage b 2 can be equal to the number of stages of the delay of the transistor for the time from the fall of the input voltage INPUT to the fall of the output voltage b 2 .

Third Embodiment

FIG. 6 is a circuit diagram illustrating the schematic structure of a level shift circuit according to a third embodiment.

In FIG. 6 , the level shift circuit further includes capacitive elements C 1 and C 2 , as compared to the level shift circuit shown in FIG. 2 . The capacitive elements C 1 and C 2 are connected to the output side of a level shift unit F 1 . The capacitive element C 1 includes a P-channel field effect transistor P 21 and the capacitive element C 2 includes an N-channel field effect transistor N 21 .

The source and drain of the P-channel field effect transistor P 21 are connected to a second power supply potential VCCQ 1 . The gate of the P-channel field effect transistor P 21 is connected to the drain of a P-channel field effect transistor P 13 . The source and drain of the N-channel field effect transistor N 21 are connected to a first power supply potential VSS. The gate of the N-channel field effect transistor N 21 is connected to the drain of the P-channel field effect transistor P 13 .

The capacitive elements C 1 and C 2 can form capacitance using the channels of the P-channel field effect transistor P 21 and the N-channel field effect transistor N 21 . At that time, in the capacitive element C 1 , at the beginning of the rise of an output voltage I 2 , a channel is formed in the P-channel field effect transistor P 21 and the P-channel field effect transistor P 21 can function as capacitance. In the capacitive element C 2 , at the end of the rise of the output voltage I 2 , a channel is formed in the N-channel field effect transistor N 21 and the N-channel field effect transistor N 21 can function as capacitance.

In the embodiment illustrated in FIG. 6 , the source and drain of the P-channel field effect transistor P 21 are connected to the second power supply potential VCCQ 1 and the source and drain of the N-channel field effect transistor N 21 are connected to the first power supply potential VSS. However, the potential of the source and drain of the P-channel field effect transistor P 21 may be controlled by the output of the CMOS circuit and the potential of the source and drain of the N-channel field effect transistor N 21 may be controlled by an output with a polarity opposite to that of the output of the CMOS circuit. The input of the CMOS circuit can be set by a register value or ROM fuse data. In addition, a plurality of P-channel field effect transistors P 21 and a plurality of N-channel field effect transistors N 21 may be provided. The potentials of the sources and drains of the P-channel field effect transistors P 21 and the potentials of the sources and drains of the N-channel field effect transistors N 21 may be individually controlled. In this way, it is possible to switch the levels of the potentials of the sources and drains of the P-channel field effect transistors P 21 and the levels of the potentials of the sources and drains of the N-channel field effect transistors N 21 . For example, it is possible to adjust capacitance for each IO without changing a mask.

FIG. 7 is a timing chart illustrating the voltage waveform of each unit in the level shift circuit shown in FIG. 6 .

In FIG. 7 , the amount of delay of the rising edge EU 11 of the output voltage I 2 is more than that of the falling edge ED 11 of the output voltage I 2 due to the capacitive elements C 1 and C 2 . Therefore, when the capacitive elements C 1 and C 2 are connected to the output side of the level shift unit F 11 , the rising edge of the output voltage I 2 is changed from EU 11 to EU 11 ′.

When the rising edge of the output voltage I 2 is changed from EU 11 to EU 11 ′, the falling edge of the output voltage b 2 is changed from ED 12 to ED 12 ′ and the rising edge of the output voltage OUTn is changed from EU 13 to EU 13 ′. On the other hand, the amount of delay of the falling edge ED 11 of the output voltage I 2 due to the capacitive elements C 1 and C 2 is small. Therefore, there is little change in the timing of the rising edge EU 12 of the output voltage b 2 and there is little change in the timing of the falling edge ED 13 of the output voltage OUTn.

Therefore, when the capacitive elements C 1 and C 2 are connected to the output side of the level shift unit F 11 , it is possible to change the duty ratio of the output voltage OUTn and reduce the deviation of the duty ratio due to the level shift circuit.

In the above-described embodiment, a method in which the capacitive elements C 1 and C 2 are connected to the output side of the level shift unit F 11 has been described. However, only one of the capacitive elements C 1 and C 2 may be connected.

In the above-described embodiment, a method in which the source and drain of the P-channel field effect transistor P 21 are fixed to the second power supply potential VCCQ 1 has been described. However, the source and drain of the P-channel field effect transistor P 21 may be switched between the first power supply potential VSS and the second power supply potential VCCQ 1 . At that time, when the source and drain of the P-channel field effect transistor P 21 are switched to the first power supply potential VSS, no channel is formed in the P-channel field effect transistor P 21 and the P-channel field effect transistor P 21 does not function as capacitance. Therefore, it is possible to change the capacitance of the output side of the level shift unit F 11 and adjust the amount of delay due to the capacitive element C 1 .

In the above-described embodiment, a method in which the source and drain of the N-channel field effect transistor N 21 are fixed to the first power supply potential VSS has been described above. However, the source and drain of the N-channel field effect transistor N 21 may be switched between the first power supply potential VSS and the second power supply potential VCCQ 1 . At that time, when the source and drain of the N-channel field effect transistor N 21 are switched to the second power supply potential VCCQ 1 , no channel is formed in the N-channel field effect transistor N 21 and the N-channel field effect transistor N 21 does not function as capacitance. Therefore, it is possible to change the capacitance of the output side of the level shift unit F 11 and adjust the amount of delay due to the capacitive element C 2 .

In order to accurately change the capacitance of the output side of the level shift unit F 11 , a plurality of sets of the capacitive elements C 1 and C 2 may be connected in parallel to each other and power supply to the capacitive elements C 1 and C 2 may be switched.

In the above-described embodiment, a method in which the P-channel field effect transistor P 21 and the N-channel field effect transistor N 21 are used as the capacitive elements C 1 and C 2 has been described. However, a capacitor in which a dielectric body is interposed between metal electrodes may be used.

Fourth Embodiment

FIG. 8 is a circuit diagram illustrating the schematic structure of a level shift circuit according to a fourth embodiment.

In FIG. 8 , the level shift circuit further includes capacitive elements C 3 and C 4 , as compared to the level shift circuit shown in FIG. 2 . The capacitive elements C 3 and C 4 are connected to the output side of a level shift unit F 12 . The capacitive element C 3 includes a P-channel field effect transistor P 22 and the capacitive element C 4 includes an N-channel field effect transistor N 22 .

The source and drain of the P-channel field effect transistor P 22 are connected to a third power supply potential VCCQ 2 . The gate of the P-channel field effect transistor P 22 is connected to the drain of a P-channel field effect transistor P 17 . The source and drain of the N-channel field effect transistor N 22 are connected to a first power supply potential VSS. The gate of the N-channel field effect transistor N 22 is connected to the drain of the P-channel field effect transistor P 17 .

The capacitive elements C 3 and C 4 can form capacitance using the channels of the P-channel field effect transistor P 22 and the N-channel field effect transistor N 22 . At that time, in the capacitive element C 3 , at the beginning of the rise of the output voltage b 2 , a channel is formed in the P-channel field effect transistor P 22 and the P-channel field effect transistor P 22 can function as capacitance. In the capacitive element C 4 , at the end of the rise of the output voltage b 2 , a channel is formed in the N-channel field effect transistor N 22 and the N-channel field effect transistor N 22 can function as capacitance.

In the embodiment illustrated in FIG. 8 , the source and drain of the P-channel field effect transistor P 22 are connected to the third power supply potential VCCQ 2 and the source and drain of the N-channel field effect transistor N 22 are connected to the first power supply potential VSS. However, the potential of the source and drain of the P-channel field effect transistor P 22 may be controlled by the output of the CMOS circuit and the potential of the source and drain of the N-channel field effect transistor N 22 may be controlled by an output with a polarity opposite to that of the output of the CMOS circuit. The input of the CMOS circuit can be set by a register value or ROM fuse data. In addition, a plurality of P-channel field effect transistors P 22 and a plurality of N-channel field effect transistors N 22 may be provided. The potentials of the sources and drains of the P-channel field effect transistors P 22 and the potentials of the sources and drains of the N-channel field effect transistors N 22 may be individually controlled. In this way, it is possible to switch the levels of the potentials of the sources and drains of the P-channel field effect transistors P 22 and the levels of the potentials of the sources and drains of the N-channel field effect transistors N 22 . For example, it is possible to adjust capacitance for each IO without changing a mask.

FIG. 9 is a timing chart illustrating the voltage waveform of each unit in the level shift circuit shown in FIG. 8 .

In FIG. 9 , the amount of delay of the rising edge EU 12 of an output voltage b 2 is more than that of the falling edge ED 12 of the output voltage b 2 due to the capacitive elements C 3 and C 4 . Therefore, when the capacitive elements C 3 and C 4 are connected to the output side of the level shift unit F 12 , the falling edge of the output voltage b 2 is changed from ED 12 to ED 12 ′.

When the rising edge of the output voltage b 2 is changed from EU 12 to EU 12 ′, the falling edge of an output voltage OUTn is changed from ED 13 to ED 13 ′. On the other hand, the amount of delay of the falling edge ED 12 of the output voltage b 2 due to the capacitive elements C 3 and C 4 is small. Therefore, there is little change in the timing of the falling edge ED 12 of the output voltage b 2 and there is little change in the rising edge EU 13 of the output voltage OUTn.

Therefore, when the capacitive elements C 3 and C 4 are connected to the output side of the level shift unit F 12 , it is possible to change the duty ratio of the output voltage OUTn and reduce the deviation of the duty ratio due to the level shift circuit.

In the above-described embodiment, a method in which the capacitive elements C 3 and C 4 are connected to the output side of the level shift unit F 12 has been described. However, only one of the capacitive elements C 3 and C 4 may be connected.

In the above-described embodiment, a method in which the source and drain of the P-channel field effect transistor P 22 are fixed to the third power supply potential VCCQ 2 has been described. However, the source and drain of the P-channel field effect transistor P 22 may be switched between the first power supply potential VSS and the third power supply potential VCCQ 2 . At that time, when the source and drain of the P-channel field effect transistor P 22 are switched to the first power supply potential VSS, no channel is formed in the P-channel field effect transistor P 22 and the P-channel field effect transistor P 22 does not function as capacitance. Therefore, it is possible to change the capacitance of the output side of the level shift unit F 12 and adjust the amount of delay due to the capacitive element C 3 .

In the above-described embodiment, a method in which the source and drain of the N-channel field effect transistor N 22 are fixed to the first power supply potential VSS has been described above. However, the source and drain of the N-channel field effect transistor N 22 may be switched between the first power supply potential VSS and the third power supply potential VCCQ 2 . At that time, when the source and drain of the N-channel field effect transistor N 22 are switched to the third power supply potential VCCQ 2 , no channel is formed in the N-channel field effect transistor N 22 and the N-channel field effect transistor N 22 does not function as capacitance. Therefore, it is possible to change the capacitance of the output side of the level shift unit F 12 and adjust the amount of delay due to the capacitive element C 4 .

In order to accurately change the capacitance of the output side of the level shift unit F 12 , a plurality of sets of the capacitive elements C 3 and C 4 may be connected in parallel to each other and power supply to the capacitive elements C 3 and C 4 may be switched.

In the above-described embodiment, a method in which the P-channel field effect transistor P 22 and the N-channel field effect transistor N 22 are used as the capacitive elements C 3 and C 4 has been described. However, a capacitor in which a dielectric body is interposed between metal electrodes may be used.

Fifth Embodiment

FIG. 10 is a circuit diagram illustrating the schematic structure of a level shift circuit according to a fifth embodiment.

In FIG. 10 , the level shift circuit includes level shift units F 21 and F 22 . The level shift unit F 22 is connected to the rear stage of the level shift unit F 21 . An inverter M 12 is connected to the front stage of the level shift units F 21 and F 22 . An inverter M 11 is connected to the front stage of the inverter M 12 . An inverter M 13 is connected to the rear stage of the level shift unit F 22 .

The level shift unit F 21 further includes P-channel field effect transistors P 31 to P 34 , as compared to the level shift unit F 11 shown in FIG. 2 . The level shift unit F 22 further includes P-channel field effect transistors P 35 to P 38 , as compared to the level shift unit F 12 shown in FIG. 2 .

The sources of the P-channel field effect transistors P 31 and P 33 are connected to a second power supply potential VCCQ 1 . The drain of the P-channel field effect transistor P 31 is connected to the source of the P-channel field effect transistor P 32 . The drain of the P-channel field effect transistor P 32 is connected to the drain of an N-channel field effect transistor N 11 . The drain of the P-channel field effect transistor P 33 is connected to the source of the P-channel field effect transistor P 34 . The drain of the P-channel field effect transistor P 34 is connected to the drain of an N-channel field effect transistor N 12 .

The gate of the P-channel field effect transistor P 32 is connected to the gate of a P-channel field effect transistor P 13 . The gate of the P-channel field effect transistor P 34 is connected to the gate of a P-channel field effect transistor P 14 .

The sources of the P-channel field effect transistors P 35 and P 37 are connected to a third power supply potential VCCQ 2 . The drain of the P-channel field effect transistor P 35 is connected to the source of the P-channel field effect transistor P 36 . The drain of the P-channel field effect transistor P 36 is connected to the drain of an N-channel field effect transistor N 15 . The drain of the P-channel field effect transistor P 37 is connected to the source of the P-channel field effect transistor P 38 . The drain of the P-channel field effect transistor P 38 is connected to the drain of an N-channel field effect transistor N 16 .

The gate of the P-channel field effect transistor P 36 is connected to the gate of a P-channel field effect transistor P 17 . The gate of the P-channel field effect transistor P 38 is connected to the gate of a P-channel field effect transistor P 18 .

The P-channel field effect transistors P 11 and P 13 form a pull-up element PU 1 . The P-channel field effect transistors P 12 and P 14 form a pull-up element PU 2 . The P-channel field effect transistors P 31 and P 32 form a pull-up element PU 3 . The P-channel field effect transistors P 33 and P 34 form a pull-up element PU 4 . The N-channel field effect transistor N 11 forms a pull-down element PD 1 and the N-channel field effect transistor N 12 forms a pull-down element PD 2 .

The pull-up element PU 1 and the pull-down element PD 1 are connected in series to each other and the pull-up element PU 2 and the pull-down element PD 2 are connected in series to each other. The pull-up elements PU 1 and PU 3 are connected in parallel to each other and the pull-up elements PU 2 and PU 4 are connected in parallel to each other. The pull-up elements PU 1 to PU 4 can pull up an output voltage I 2 to the second power supply potential VCCQ 1 . The pull-down elements PD 1 and PD 2 can pull down the output voltage I 2 to the first power supply potential VSS.

The P-channel field effect transistors P 15 and P 17 form a pull-up element PU 5 . The P-channel field effect transistors P 16 and P 18 form a pull-up element PU 6 . The P-channel field effect transistors P 35 and P 36 form a pull-up element PU 7 . The P-channel field effect transistors P 37 and P 38 form a pull-up element PU 8 . The N-channel field effect transistor N 15 forms a pull-down element PD 5 and the N-channel field effect transistor N 16 forms a pull-down element PD 6 .

The pull-up element PU 5 and the pull-down element PD 5 are connected in series to each other and the pull-up element PU 6 and the pull-down element PD 6 are connected in series to each other. The pull-up elements PU 5 and PU 7 are connected in parallel to each other and the pull-up elements PU 6 and PU 8 are connected in parallel to each other. The pull-up elements PU 5 to PU 8 can pull up an output voltage b 2 to the third power supply potential VCCQ 2 . The pull-down elements PD 5 and PD 6 can pull down the output voltage b 2 to the first power supply potential VSS.

A switching signal HVCCQ is input to the gates of the P-channel field effect transistors P 31 , P 33 , P 35 , and P 37 . When the second power supply potential VCCQ 1 and the third power supply potential VCCQ 2 are low, the switching signal HVCCQ can have an “L” level. When the second power supply potential VCCQ 1 and the third power supply potential VCCQ 2 are high, the switching signal HVCCQ can have an “H” level.

When the switching signal HVCCQ is at the “L” level, the P-channel field effect transistors P 31 , P 33 , P 35 , and P 37 are turned on. Then, the pull-up elements PU 3 , PU 4 , PU 7 , and PU 8 are driven and the pull-up capability of the level shift units F 21 and F 22 is increased. On the other hand, when the switching signal HVCCQ is at the “H” level, the P-channel field effect transistors P 31 , P 33 , P 35 , and P 37 are turned off. Then, the driving of the pull-up elements PU 3 , PU 4 , PU 7 , and PU 8 is stopped and the pull-up capability of the level shift units F 21 and F 22 is reduced.

In this way, even when the second power supply potential VCCQ 1 and the third power supply potential VCCQ 2 are changed, it is possible to prevent a change in the delay time of the rising edges of the output voltages I 2 and b 2 and reduce the deviation of the duty ratio of the output voltage OUTn.

In order to reduce the deviation of the duty ratio of the output voltage OUTn, the capacitive elements C 1 and C 2 shown in FIG. 6 may be connected to the output side of the level shift unit F 21 and the capacitive elements C 3 and C 4 shown in FIG. 8 may be connected to the output side of the level shift unit F 22 .

Sixth Embodiment

FIG. 11 is a circuit diagram illustrating the schematic structure of a level shift circuit according to a sixth embodiment.

In FIG. 11 , the level shift circuit further includes a power-off element W 1 , as compared to the level shift circuit shown in FIG. 10 . The power-off element W 1 includes a P-channel field effect transistor P 41 . The sources of the P-channel field effect transistors P 11 , P 12 , P 15 , P 16 , P 31 , P 33 , P 35 , and P 37 are connected to a common terminal COM. The drain of a P-channel field effect transistor P 41 is connected to the common terminal COM. The source of the P-channel field effect transistor P 41 is connected to a fifth power supply potential VCCQ. A power-down signal PWN is input to the gate of the P-channel field effect transistor P 41 .

When the power-down of an external power supply is detected, the power-down signal PWN rises and the P-channel field effect transistor P 41 is turned off. In addition, a fourth power supply potential VDD is generated from the external power supply and the fifth power supply potential VCCQ is generated from an internal power supply. Therefore, the level shift units F 21 and F 22 can be disconnected from the fifth power supply potential VCCQ and it is possible to prevent a shoot-through current from flowing to the level shift circuit when power-down occurs in the external power supply.

Seventh Embodiment

FIG. 12 is a circuit diagram illustrating the schematic structure of a level shift circuit according to a seventh embodiment.

In FIG. 12 , the level shift circuit includes level shift units F 31 and F 32 and the level shift unit F 32 is connected to the rear stage of the level shift unit F 31 . An inverter M 12 is connected to the front stage of the level shift units F 31 and F 32 . An inverter M 11 is connected to the front stage of the inverter M 12 . An inverter M 13 is connected to the rear stage of the level shift unit F 32 .

The level shift unit F 31 can shift the level of an output voltage between a first power supply potential VSS and a second power supply potential VCCQ 1 . The level shift unit F 32 can shift the level of the output voltage between the first power supply potential VSS and a third power supply potential VCCQ 2 .

In each of the level shift units F 31 and F 32 , the delay time of the rising edge of the output voltage is different from that of the falling edge of the output voltage. The level shift unit F 31 can perform a level shift operation on the basis of input voltages IN and INn. The level shift unit F 32 can perform a level shift operation using the input voltage IN to the level shift unit F 31 and the output voltage I 2 from the level shift unit F 31 as differential input voltages.

The level shift unit F 31 includes P-channel field effect transistors P 51 and P 52 and N-channel field effect transistors N 51 and N 52 . The level shift unit F 32 includes P-channel field effect transistors P 53 and P 54 and N-channel field effect transistors N 53 and N 54 .

The sources of the P-channel field effect transistors P 51 and P 52 are connected to the second power supply potential VCCQ 1 . The drain of the P-channel field effect transistor P 51 is connected to the drain of the N-channel field effect transistor N 51 . The drain of the P-channel field effect transistor P 52 is connected to the drain of the N-channel field effect transistor N 52 . The sources of the N-channel field effect transistors N 51 and N 52 are connected to the first power supply potential VSS.

The gate of the N-channel field effect transistor N 51 is connected to the drain of the P-channel field effect transistor P 2 . The gate of the N-channel field effect transistor N 52 is connected to the drain of the P-channel field effect transistor P 1 . The gate of the P-channel field effect transistor P 51 is connected to the drain of the P-channel field effect transistor P 52 . The gate of the P-channel field effect transistor P 52 is connected to the drain of the P-channel field effect transistor P 51 .

The sources of the P-channel field effect transistors P 53 and P 54 are connected to the third power supply potential VCCQ 2 . The drain of the P-channel field effect transistor P 53 is connected to the drain of the N-channel field effect transistor N 53 . The drain of the P-channel field effect transistor P 54 is connected to the drain of the N-channel field effect transistor N 54 and the sources of the N-channel field effect transistors N 53 and N 54 are connected to the first power supply potential VSS.

The gate of the N-channel field effect transistor N 53 is connected to the drain of the P-channel field effect transistor P 51 and the gate of the N-channel field effect transistor N 54 is connected to the drain of the P-channel field effect transistor P 2 . The gate of the P-channel field effect transistor P 53 is connected to the drain of the P-channel field effect transistor P 54 and the gate of the P-channel field effect transistor P 54 is connected to the drain of the P-channel field effect transistor P 53 .

When an input voltage INPUT is input to the inverter M 11 , the inverter M 11 inverts the input voltage INPUT to generate an input voltage INn and outputs the input voltage INn to the inverter M 12 and the level shift unit F 31 .

When the input voltage INn is input to the inverter M 12 , the inverter M 12 inverts the input voltage INn to generate an input voltage IN and outputs the input voltage IN to the level shift unit F 31 .

The level shift unit F 31 performs a level shift operation using the input voltages INn and IN as differential input voltages to generate an output voltage 12 with an amplitude VCCQ 1 , and the output voltage I 2 is input to the level shift unit F 32 .

The level shift unit F 32 performs a level shift operation using the input voltage IN to the level shift unit F 31 and the output voltage I 2 from the level shift unit F 31 as differential input voltages to generate an output voltage b 2 with an amplitude VCCQ 2 , and the output voltage b 2 is input to the inverter M 13 .

The inverter M 13 inverts the output voltage b 2 from the level shift unit F 32 and an output voltage OUTn is output from the inverter M 13 .

In this way, the delay time of the falling edge of the output voltage I 2 from the previous level shift unit F 31 can be compensated by the delay time of the rising edge of the output voltage b 2 from the next level shift unit F 32 , and the delay time of the rising edge of the output voltage 12 from the previous level shift unit F 31 can be compensated by the delay time of the falling edge of the output voltage b 2 from the next level shift unit F 32 . As a result, it is possible to reduce the deviation of the duty ratio of the output voltage OUTn to the input voltage INPUT, as compared to the deviation of the duty ratio of the output voltage I 2 to the input voltage INPUT and prevent a reduction in operation margin.

Eighth Embodiment

FIG. 13 is a circuit diagram illustrating the delay of each node when an input voltage INPUT to an inverter M 11 falls in a level shift circuit according to an eighth embodiment. In the example shown in FIG. 13 , the delay time corresponding to one transistor is 1 and the delay time of each node is shown together with the level.

In FIG. 13 , the level shift circuit includes level shift units F 11 ′ and F 12 ′, instead of the level shift units F 11 and F 12 shown in FIG. 2 . The level shift units F 11 ′ and F 12 ′ can shift the level of an output voltage between a first power supply potential VSS and a fifth power supply potential VCCQ.

In each of the level shift units F 11 ′ and F 12 ′, the delay time of the rising edge of the output voltage is different from that of the falling edge of the output voltage. The level shift unit F 11 ′ can perform a level shift operation on the basis of input voltages IN and INn. The level shift unit F 12 ′ can perform a level shift operation using output voltages I 2 and I 2 n from the level shift unit F 11 ′ as differential input voltages.

In FIG. 2 , the sources of the P-channel field effect transistors P 11 and P 12 of the level shift unit F 11 are connected to the second power supply potential VCCQ 1 . However, in FIG. 13 , the sources of the P-channel field effect transistors P 11 and P 12 of the level shift unit F 11 ′ are connected to the fifth power supply potential VCCQ. The structure of the level shift unit F 11 ′ shown in FIG. 13 is similar to that of the level shift unit F 11 shown in FIG. 2 except for the above.

In FIG. 2 , the sources of the P-channel field effect transistors P 15 and P 16 of the level shift unit F 12 are connected to the third power supply potential VCCQ 2 . However, in FIG. 13 , the sources of the P-channel field effect transistors P 15 and P 16 of the level shift unit F 12 ′ are connected to the fifth power supply potential VCCQ. In FIG. 2 , the gate of the P-channel field effect transistor P 16 and the gate of the N-channel field effect transistor N 16 in the level shift unit F 12 are connected to the drain of the P-channel field effect transistor P 2 . However, in FIG. 13 , the gate of the P-channel field effect transistor P 16 and the gate of the N-channel field effect transistor N 16 in the level shift unit F 12 ′ are connected to the drain of the P-channel field effect transistor P 14 . The structure of the level shift unit F 12 ′ shown in FIG. 13 is similar to that of the level shift unit F 12 shown in FIG. 2 except for the above.

When an input voltage INPUT is at an “L” level and the delay time is 1, the input voltage INn is delayed by a value corresponding to one transistor of the inverter M 11 and rises. Therefore, the input voltage INn is at an “H” level and the delay time is 2. When the input voltage INn is at the “H” level, the drain potential of the P-channel field effect transistor P 14 is delayed by a value corresponding to one transistor of the level shift unit F 11 ′ and falls. Therefore, the drain potential of the P-channel field effect transistor P 14 is at an “L” level and the delay time is 3. The P-channel field effect transistor P 13 is turned on.

When the input voltage INn is at the “H” level, the input voltage IN is delayed by a value corresponding to one transistor of the inverter M 12 and falls. Therefore, the input voltage IN is at an “L” level and the delay time is 3. When the input voltage IN is at the “L” level, the drain potential of the P-channel field effect transistor P 11 is delayed by a value corresponding to one transistor of the level shift unit F 11 ′ and rises. Therefore, the drain potential of the P-channel field effect transistor P 11 is at an “H” level and the delay time is 4. When the P-channel field effect transistor P 13 is turned on and the drain potential of the P-channel field effect transistor P 11 is at the “H” level, the output voltage I 2 is delayed by a value corresponding to one transistor of the level shift unit F 11 ′ and rises. Therefore, the output voltage 12 is at an “H” level and the delay time is 5.

When the output voltage I 2 is at the “H” level, the output voltage b 2 is delayed by a value corresponding to one transistor of the level shift unit F 12 ′ and falls. Therefore, the output voltage b 2 is at an “L” level and the delay time is 6. When the output voltage b 2 is at the “L” level, the output voltage OUTn is delayed by a value corresponding to one transistor of the inverter M 13 and rises. Therefore, the output voltage OUTn is at an “H” level and the delay time is 7.

That is, in this case, the P-channel field effect transistor P 15 of the level shift unit F 12 ′ is turned off and the N-channel field effect transistor N 15 thereof is turned on, thereby determining the level of the output voltage b 2 . Therefore, the states of the P-channel field effect transistor P 16 and the N-channel field effect transistor N 16 of the level shift unit F 12 ′ are not related to the determination of the level of the output voltage. In the level shift circuit shown in FIG. 13 , even when the connection destinations of the gate of the P-channel field effect transistor P 16 and the gate of the N-channel field effect transistor N 16 are different from those in the level shift circuit shown in FIG. 2 , the same operation as that of the level shift circuit shown in FIG. 2 is performed.

FIG. 14 is a circuit diagram illustrating the delay of each node when the input voltage INPUT to the inverter M 11 rises in the level shift circuit shown in FIG. 13 . In the example shown in FIG. 14 , the delay time corresponding to one transistor is 1 and the delay time of each node is shown together with the level.

In FIG. 14 , when the input voltage INPUT is at an “H” level and the delay time is 1, the input voltage INn is delayed by a value corresponding to one transistor of the inverter M 11 and falls. Therefore, the input voltage INn is at an “L” level and the delay time is 2. When the input voltage INn is at the “L” level, the drain potential of the P-channel field effect transistor P 12 is delayed by a value corresponding to one transistor of the level shift unit F 11 ′ and rises. Therefore, the drain potential of the P-channel field effect transistor P 12 is at an “H” level and the delay time is 3.

When the input voltage INn is at the “L” level, the input voltage IN is delayed by a value corresponding to one transistor of the inverter M 12 and rises. Therefore, the input voltage IN is at an “H” level and the delay time is 3. When the input voltage IN is at the “H” level, the output voltage I 2 is delayed by a value corresponding to one transistor of the level shift unit F 11 ′ and falls. Therefore, the output voltage I 2 is at an “L” level and the delay time is 4. When the drain potential of the P-channel field effect transistor P 12 is at the “H” level and the output voltage I 2 is at the “L” level, the drain potential of the P-channel field effect transistor P 14 is delayed by a value corresponding to one transistor of the level shift unit F 11 ′ and rises. Therefore, the drain potential of the P-channel field effect transistor P 14 is at an “H” level and the delay time is 5.

When the output voltage I 2 is at the “L” level, the drain potential of the P-channel field effect transistor P 15 is delayed by a value corresponding to one transistor of the level shift unit F 12 ′ and rises. Therefore, the drain potential of the P-channel field effect transistor P 15 is at an “H” level and the delay time is 5.

When the drain potential of the P-channel field effect transistor P 14 is at the “H” level, the drain potential of the P-channel field effect transistor P 18 is delayed by a value corresponding to one transistor of the level shift unit F 12 ′ and falls. Therefore, the drain potential of the P-channel field effect transistor P 18 is at an “L” level and the delay time is 6. The P-channel field effect transistor P 17 is turned on.

When the drain potential of the P-channel field effect transistor P 15 is at the “H” level and the P-channel field effect transistor P 17 is turned on, the output voltage b 2 is delayed by a value corresponding to one transistor of the level shift unit F 12 ′ and rises. Therefore, the output voltage b 2 is at an “H” level and the delay time is 7. When the output voltage b 2 is at the “H” level, the output voltage OUTn is delayed by a value corresponding to one transistor of the inverter M 13 and falls. Therefore, the output voltage OUTn is at an “L” level and the delay time is 8.

Therefore, in the level shift circuit, the time from the rise of the input voltage INPUT to the fall of the output voltage OUTn is delayed by a delay time corresponding to one transistor, as compared to the time from the fall of the input voltage INPUT to the rise of the output voltage OUTn.

The level shift units F 11 ′ and F 12 ′ with the same amount of level shift are connected in series to each other to compensate the delay time of the falling edge of the output voltage I 2 from the previous level shift unit F 11 ′ with the delay time of the rising edge of the output voltage b 2 from the next level shift unit F 12 ′ and compensate the delay time of the rising edge of the output voltage I 2 from the previous level shift unit F 11 ′ with the delay time of the falling edge of the output voltage b 2 from the next level shift unit F 12 ′. Therefore, even when the delay times of the rising edges of the output voltages I 2 and b 2 are different from the delay times of the falling edges of the output voltages I 2 and b 2 in each of the level shift units F 11 ′ and F 12 ′, it is possible to reduce the deviation of the duty ratio of the output voltage OUTn to the input voltage INPUT and prevent a reduction in operation margin.

Ninth Embodiment

FIG. 15 is a block diagram illustrating the schematic structure of a semiconductor device according to a ninth embodiment to which a level shift circuit is applied.

In FIG. 15 , an input buffer 22 , an internal circuit 23 , and an output buffer 24 are formed in a semiconductor chip 21 . The internal circuit 23 may be a logic circuit, memory, a processor, or an ASIC. The input buffer 22 is connected to the front stage of the internal circuit 23 and the output buffer 24 is connected to the rear stage of the internal circuit 23 .

The input buffer 22 includes inverters M 21 and M 22 and a level shift circuit FS 1 and the output buffer 24 includes inverters M 23 and M 24 and a level shift circuit FS 2 . The level shift circuits FS 1 and FS 2 may have any one of the structures shown in FIGS. 1 , 2 , 6 , and 8 and FIGS. 10 to 13 .

The inverter M 21 is connected to the front stage of the level shift circuit FS 1 . The inverter M 22 is connected to the rear stage of the level shift circuit FS 1 . A pad electrode PDI is connected to the input of the inverter M 21 . The internal circuit 23 is connected to the input of the inverter M 22 . The inverter M 23 is connected to the front stage of the level shift circuit FS 2 . The inverter M 24 is connected to the rear stage of the level shift circuit FS 2 . The internal circuit 23 is connected to the input of the inverter M 23 . A pad electrode PDO is connected to the output of the inverter M 24 .

When an input voltage with an amplitude VCCQ is input to the pad electrode PDI, the inverter M 21 inverts the input voltage and the inverted input voltage is input to the level shift circuit FS 1 . Then, in the level shift circuit FS 1 , a level shift from the input voltage with the amplitude VCCQ to an output voltage with an amplitude VDD is performed and the output voltage is inverted by the inverter M 22 and is then input to the internal circuit 23 .

When the output voltage with the amplitude VDD is output from the internal circuit 23 , the inverter M 23 inverts the output voltage and the inverted output voltage is input to the level shift circuit FS 2 . Then, in the level shift circuit FS 2 , a level shift from the output voltage with the amplitude VDD to an output voltage with an amplitude VCCQ is performed and the output voltage is inverted by the inverter M 24 and is then output through the pad electrode PDO.

When VCCQ>VDD is satisfied, the internal circuit 23 can operate at the internal voltage lower than the external power supply voltage. On the other hand, when VCCQ<VDD is satisfied, the internal circuit 23 can be operated at the internal voltage higher than the external power supply voltage and it is possible to increase the operation speed.

Since the level shift circuits FS 1 and FS 2 have any one of the structures shown in FIGS. 1 , 2 , 6 , and 8 and FIGS. 10 to 13 , it is possible to reduce the deviation of the duty ratio of the output voltage and prevent a reduction in the operation margin of the internal circuit 23 .

Tenth Embodiment

FIG. 16A is a block diagram illustrating the schematic structure of a semiconductor memory device to which a level shift circuit according to a tenth embodiment is applied. FIG. 16B is a perspective view illustrating the schematic structure of a NAND memory 3 - 1 shown in 16 A. FIG. 16C is a perspective view illustrating the schematic structure of a semiconductor chip CP 1 of the NAND memory 3 - 1 shown in FIG. 16B .

In FIGS. 16A to 16C , the semiconductor memory device includes n (n is an integer equal to or greater than 2) NAND memories 3 - 1 to 3 - n and a controller 1 that controls the driving of the NAND memories 3 - 1 to 3 - n . Examples of the control of the driving of the NAND memories 3 - 1 to 3 - n may include the control of the reading and writing of the NAND memories 3 - 1 to 3 - n , block selection, error correction, and wear leveling.

The NAND memories 3 - 1 to 3 - n are connected in parallel to the controller 1 through a channel 2 . For example, the NAND memory 3 - 1 includes m (m is an integer equal to or greater than 2) semiconductor chips CP 1 to CPm and each of the semiconductor chips CP 1 to CPm includes a NAND flash memory 13 and pad electrodes PD 1 to PDm connected to the NAND flash memory 13 . The NAND flash memory 13 may include, for example, a unit cell array, a decoder, a sense amplifier, a charge pump circuit, and a page buffer.

Each of the semiconductor chips CP 1 to CPm includes an input buffer 11 , an output buffer 12 , and a programmable ROM 14 . The input buffer 11 can transmit control signals, such as written data or an address, transmitted from the controller 1 to the NAND flash memory 13 . The output buffer 12 can transmit data read from, for example, the NAND flash memory 13 to the controller 1 .

The input buffer 22 shown in FIG. 15 may be used as the input buffer 11 . The input buffer 24 shown in FIG. 15 may be used as the output buffer 12 . In this case, the power supply voltage of the NAND flash memory 13 may be set to VDD and the power supply voltage of the controller 1 may be set to VCCQ.

The programmable ROM 14 stores various parameters related to the operations of the input buffer 11 , the output buffer 12 , and the NAND flash memory 13 . For example, when the level shift circuits of the input buffer 11 and the output buffer 12 have the structure shown in FIG. 6 , parameters for switching the source and drain of the P-channel field effect transistor P 21 between the first power supply potential VSS and the second power supply potential VCCQ 1 may be stored, and parameters for switching the source and drain of the N-channel field effect transistor N 21 between the first power supply potential VSS and the second power supply potential VCCQ 1 may be stored.

The m semiconductor chips CP 1 to CPm are mounted on one semiconductor package PK 1 and an external terminal TM of the semiconductor package PK 1 is shared by the pad electrodes PD 1 to PDm of the m semiconductor chips CP 1 to CPm. As a method of mounting the semiconductor chips CP 1 to CPm on the semiconductor package PK 1 , the following methods may be used: a method of laminating the semiconductor chips CP 1 to CPm; and a method of arranging the semiconductor chips CP 1 to CPm on the same plane. In addition, the semiconductor chips CP 1 to CPm may be mounted face down or face up. As a method of sharing one external terminal TM among the m pad electrodes PD 1 to PDm, the m pad electrodes PD 1 to PDm and the one external terminal TM may be connected to each other by bonding wires BW. Alternatively, the semiconductor chips CP 1 to CPm may be mounted by flip chip technology, and the pad electrodes PD 1 to PDm and the external terminal TM may be connected to each other through bump electrodes form on the pad electrodes PD 1 to PDm. Alternatively, through electrodes may be formed in the semiconductor chips CP 1 to CPm and the pad electrodes PD 1 to PDm and the external terminal TM may be connected to each other through the through electrodes. This holds for the NAND memories 3 - 2 to 3 - n other than the NAND memory 3 - 1 . In addition, the semiconductor memory device may be used as a storage device, such as a memory card or an SSD.

FIG. 17 is a perspective view illustrating an example of the schematic structure of the NAND memory 3 - 1 shown in FIG. 16A . In the example shown in FIG. 17 , m is 4.

In FIG. 17 , the pad electrodes PD 1 to PD 4 are formed in the semiconductor chips CP 1 to CP 4 , respectively. The pad electrodes PD 1 to PD 4 may be used as, for example, address terminals, reading/writing terminals, chip selection terminals, or data terminals. External terminals TM 1 to TM 17 are formed in the semiconductor package PK 1 . When four semiconductor chips CP 1 to CP 4 are laminated and mounted on the semiconductor package PK 1 , the semiconductor chips CP 1 to CP 4 may be laminated so as to deviate from each other such that the pad electrodes PD 1 to PD 4 are exposed. Then, for example, the pad electrodes PD 1 to PD 4 may be connected to the common external terminal TM 1 by the bonding wires BW. In this way, the pad electrodes PD 1 to PD 4 of the four semiconductor chips CP 1 to CP 4 can share one external terminal TM 1 .

Eleventh Embodiment

FIG. 18 is a timing chart illustrating the operation of a semiconductor memory device according to an eleventh embodiment to which a level shift circuit is applied in the toggle mode.

In FIG. 18 , the controller 1 shown in FIG. 16 outputs a chip enable signal CE_n, a command latch enable signal CLE, an address latch enable signal ALE, a clock signal CLK, a read/write signal W/R_n, a data strobe signal DQS, and data DQ[ 7 : 0 ].

The data strobe signal DQS indicates the time when the data DQ[ 7 : 0 ] is acquired and the timing of the data strobe signal DQS and the data DQ[ 7 : 0 ] is set on the basis of the clock signal CLK. In the controller shown in FIG. 16 , a command and an address are output as the data DQ[ 7 : 0 ], the data DQ[ 7 : 0 ] when the command latch enable signal CLE is activated is considered as the command, and the data DQ[ 7 : 0 ] when the address latch enable signal ALE is activated is considered as the address.

In the toggle mode, when the command latch enable signal CLE and the address latch enable signal ALE are inactivated, the data DQ[ 7 : 0 ] is acquired at both the rising edge and the falling edge of the data strobe signal DQS.

In FIG. 18 , tCH is a CE_n hold time, tWHR is a command, an address, or a data input cycle to a data output cycle, tCALS is a W/R_n, CLE, and ALE setup time, tHP is a half-clock period, tDQSD is W/R_n low to DQS/DQ driven by device, tDQSCK is an access window of DQS from CLK, tDQSHZ is W/Rn high to DQS/DQ tri-state by device, tAC is an access window of DQ[ 7 : 0 ] from CLK, tDVW is an output data valid window, tDQSQ is DQS-DQ skew, DQS to last DQ valid, per access, and tQH is DQ-DQS hold, DQS to first DQ to go non-valid, per access.

The controller 1 shown in FIG. 16 sets the amplitudes of the chip enable signal CE_n, the command latch enable signal CLE, the address latch enable signal ALE, the clock signal CLK, the read/write signal W/R_n, and the data strobe signal DQS and data DQ[ 7 : 0 ] to VCCQ.

The level shift circuit of the input buffer 11 shifts the level of the signal from the controller 1 to an amplitude VDD and the level-shifted signal is input to the NAND flash memory 13 . At that time, the NAND flash memory 13 shown in FIG. 16 sets the amplitudes of the chip enable signal CE_n, the command latch enable signal CLE, the address latch enable signal ALE, the clock signal CLK, the read/write signal W/R_n, the data strobe signal DQS, and the data DQ[ 7 : 0 ] to VDD. The level shift circuit of the output buffer 12 shifts the level of the signal from the NAND flash memory 13 to an amplitude VCCQ and the level-shifted signal is input to the controller 1 .

Since the level shift circuits of the input buffer 11 and the output buffer 12 have any one of the structures shown in FIGS. 1 , 2 , 6 , and 8 and FIGS. 10 to 13 , it is possible to reduce the deviation of the duty ratio of the output voltage. Therefore, it is possible to reduce the deviation of tDVW during a level shift operation and prevent a reduction in operation margin.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.