Methods of making jogged layout routings double patterning compliant

1. Field of the Invention

Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of making jogged routing layouts that are compliant with double patterning techniques and resulting semiconductor devices that contain such jogged routing layouts.

2. Description of the Related Art

Photolithography is one of the basic processes used in manufacturing integrated circuit products. At a very high level, photolithography involves: (1) forming a layer of light or radiation-sensitive material, such as photoresist, above a layer of material or a substrate; (2) selectively exposing the radiation-sensitive material to a light generated by a light source (such as a DUV or EUV source) to transfer a pattern defined by a mask or reticle (interchangeable terms as used herein) to the radiation-sensitive material; and (3) developing the exposed layer of radiation-sensitive material to define a patterned mask layer. Various process operations, such as etching or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned mask layer.

Of course, the ultimate goal in integrated circuit fabrication is to faithfully reproduce the original circuit design on the integrated circuit product. Historically, the feature sizes and pitches (spacing between features) employed in integrated circuit products were such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced to the point where existing photolithography tools, e.g., 193 nm wavelength photolithography tools, cannot form a single patterned mask layer with all of the features of the overall target pattern. Accordingly, device designers have resorted to techniques that involve performing multiple exposures to define a single target pattern in a layer of material. One such technique is generally referred to as double patterning. In general, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, less-dense patterns. The simplified, less-dense patterns are then printed separately on a wafer utilizing two separate masks (where one of the masks is utilized to image one of the less-dense patterns, and the other mask is utilized to image the other less-dense pattern). Further, in some cases, the second pattern is printed in between the lines of the first pattern such that the imaged wafer has, for example, a feature pitch which is half that found on either of the two less-dense masks. This technique effectively lowers the complexity of the photolithography process, improving the achievable resolution and enabling the printing of far smaller features than would otherwise be possible using existing photolithography tools.

FIG. 1 depicts one illustrative double patterning process. An initial overall target pattern 10 that is comprised of nine illustrative trench features 12 is depicted in FIG. 1 . Each of the features 12 has the same critical dimension 13 . The space between the features 12 in the initial overall target pattern 10 is such that the initial overall target pattern 10 cannot be printed using a single mask with available photolithography tools. Thus, in this illustrative example, the initial overall target pattern 10 is decomposed into a first sub-target pattern 10 A (comprised of features 1 , 3 , 5 , 7 and 9 ), and a second sub-target pattern 10 B (comprised of the features 2 , 4 , 6 and 8 ). The sub-target patterns 10 A, 10 B are referred to as “sub-target patterns” because each of them contain less than all of the features in the initial overall target pattern 10 . The features that are incorporated in the sub-target patterns 10 A, 10 B are selected and spaced such that the patterns 10 A, 10 B may be readily formed in a single masking layer using available photolithography tools. Ultimately, when the mask design process is completed, data corresponding to the sub-target patterns 10 A, 10 B (modified as necessary during the design process) will be provided to a mask manufacturer that will produce tangible masks (not shown) corresponding to the patterns 10 A, 10 B to be used in a photolithography tool to manufacture integrated circuit products.

FIGS. 2A-2B depict various illustrative circuit layout patterns that may be employed when designing integrated circuit devices. FIG. 2A depicts an illustrative circuit layout pattern 14 comprised of a plurality of rectangular line-type features 18 , e.g., trenches, and a crossover or jogged feature 16 . The crossover or jogged feature 16 is a composite pattern that is comprised of line-type features 16 A, 16 B that are connected together by a crossover portion 16 J. All of the features depicted in FIG. 2A , including the crossover portion 16 J, have the same critical dimension 15 . The pattern 14 includes five illustrative routing tracks (A-E). The distance between adjacent routing tracks may be referred to as the “pitch” of features in the pattern 14 . The crossover feature 16 depicted in FIG. 2A is sometimes referred to as an “even-jog” type feature because the crossover portion 16 J spans an even number of pitch distances, e.g., a fist “pitch” between the tracks B and C and a “second pitch” between tracks C and D in the depicted example. A crossover type feature that spanned 6 such pitch distances (not shown) would also be referred to as an even-jog type feature. In contrast, the features 12 depicted in the pattern 10 in FIG. 1 do not have any such crossover or jogged features.

FIG. 2B depicts an illustrative circuit layout pattern 17 comprised of a plurality of rectangular line-type features 19 , e.g., trenches, and a crossover or jogged feature 21 . The pattern 15 also includes five illustrative routing tracks (A-E). The crossover feature 21 is a composite pattern that is comprised of line-type features 21 A, 21 B that are connected together by a crossover portion 21 J. All of the features depicted in FIG. 2B , including the crossover portion 21 J, have the same critical dimension 21 X. The crossover feature 21 is sometimes referred to as an “odd-jog” type feature because the crossover portion 21 J spans a distance equal to one pitch, e.g., the distance between the tracks B and C in the depicted example.

To use double patterning techniques, an overall target pattern must be what is referred to as double patterning compliant. In general, this means that an overall target pattern can be decomposed into two separate patterns that each may be printed in a single layer using existing photolithography tools. An overall target pattern may have many regions or areas that cannot be printed because the features in those regions are spaced too close to one another for existing photolithography tools to be able to print such closely spaced features as individual features. To the extent an overall target pattern has an even number of such regions, such a pattern is sometimes referred to as an “even cycle” pattern, while an overall target pattern that has an odd number of such regions is sometimes referred to as an “odd cycle” pattern. Even cycle patterns can be formed using double patterning techniques, while odd cycle patterns cannot be formed using double patterning techniques.

In general, the use of patterns that have odd jog crossover or jogged features, such as the feature 21 depicted in FIG. 2B , is discouraged when trying to develop circuit layouts that are intended to be double patterning compliant for fear that the inclusion of such odd-jog crossover features will lead to odd-cycle routing layouts. However, the general restriction against using such odd-jog features for double patterning compliant circuit layouts degrade routing efficiency and may lead to the consumption of additional chip area as circuit layouts are increased in size as a result of the non-use of such odd-jog features.

FIGS. 3A-3C depict additional overall target patterns that are discussed as it relates to various issues associated with double patterning techniques. FIG. 3A depicts an illustrative circuit layout pattern 20 comprised of a plurality of rectangular line-type features 20 F, e.g., trenches, and a crossover or jogged feature 22 . The pattern 20 includes five illustrative routing tracks (A-E). The crossover feature 22 is a composite pattern that is comprised of line-type features 22 A, 22 B that are connected together by a crossover portion 22 J. All of the features depicted in FIG. 2A , including the crossover portion 22 J, have the same critical dimension 23 . The crossover feature 22 J depicted in FIG. 3A is an odd-jog type feature because the crossover portion 16 J spans a distance equal to one pitch, e.g., between the tracks B and C in the depicted example. In one illustrative example, as depicted in FIG. 3A , the overall target pattern 20 may be decomposed into two sub-target patterns 20 A, 20 B. In this example, the crossover feature 22 is divided into two sub-features 22 - 1 (in pattern 20 A) and 22 - 2 (in pattern 20 B). The two sub-features 22 - 1 , 22 - 2 are sized such that when these patterns are formed on a product, there will be an area or overlap 25 —or a so-called “stich”—that will be printed twice, once when the mask corresponding to the pattern 20 A is used and a second time when the mask corresponding to the pattern 20 B is used. In this example, even though crossover or jogged feature 22 is an odd-jog feature, the pattern 20 may be formed using double patterning techniques because there is no structure near or opposite the ends 22 E 1 and 22 E 2 of the sub-features 22 - 1 , 22 - 2 , respectively.

FIG. 3B depicts an illustrative circuit layout pattern 30 comprised of a plurality of rectangular line-type features 30 F, e.g., trenches, and a crossover or jogged feature 32 . The pattern 30 includes five illustrative routing tracks (A-E). The crossover feature 32 is a composite pattern that is comprised of line-type features 32 A, 32 B that are connected together by a crossover portion 32 J. All of the features depicted in FIG. 3B , including the crossover portion 32 J, have the same critical dimension 33 . The crossover feature 32 depicted in FIG. 3B is sometimes referred to as an odd-jog type feature because the crossover portion 32 J spans a distance equal to three pitches, e.g., between the tracks B and E in the depicted example. In one illustrative example, as depicted in FIG. 3B , the overall target pattern 30 may be decomposed into two sub-target patterns 30 A, 30 B. In this example, the crossover feature 32 is divided into two sub-features 32 - 1 (in pattern 30 A) and 32 - 2 (in pattern 30 B). The two sub-features 32 - 1 , 32 - 2 are sized such that, when these patterns are formed on a product, there will be an area or overlap 35 —or a so-called “stich”—that will be printed twice, once when the mask corresponding to the pattern 30 A is used and a second time when the mask corresponding to the pattern 30 B is used. In this example, even though crossover or jogged feature 32 is an “odd-jog” feature, the pattern 30 may be formed using double patterning techniques because there is no structure near or opposite the ends 32 E 1 , and 32 E 2 of the sub-features 32 - 1 , 32 - 2 , respectively.

FIG. 3C depicts an illustrative circuit layout pattern 40 comprised of a plurality of rectangular line-type features 40 F, e.g., trenches, and a crossover or jogged feature 42 . The pattern 40 also includes five illustrative routing tracks (A-E). The crossover feature 42 is a composite pattern that is comprised of line-type features 42 A, 42 B that are connected together by a crossover portion 42 J. All of the features depicted in FIG. 3C , including the crossover portion 42 J, have the same critical dimension 43 . The crossover feature 42 depicted in FIG. 3C is sometimes referred to as an odd-jog type feature because the crossover portion 42 J spans a distance equal to one pitch, e.g., between the tracks B and C in the depicted example. In this example, the overall target pattern 40 may be initially decomposed into two sub-target patterns 40 A, 40 B. In this example, the crossover feature 42 is divided into two sub-features 42 - 1 (in pattern 40 A) and 42 - 2 (in pattern 40 B). However, in this example, the overall pattern 40 cannot be formed using double patterning techniques because there is structure near or opposite the ends 42 E 1 and 42 E 2 of the sub-features 42 - 1 , 42 - 2 , in the areas indicated by the dashed lines 48 A, 48 B. That is, the spacing 45 , 47 between the ends 42 E 1 , 42 E 2 , respectively, and the nearby structure 44 , 46 , respectively, violates minimum spacing design rules and, accordingly, the patterns 40 A, 40 B cannot be reliably formed using photolithography tools that will be used manufacturing such a pattern. Additionally, when printing certain features, the surrounding structures can and do have an impact on how accurately a feature may be formed. For example, it is known that, when trying to form a pattern like that depicted in FIG. 3C , where, for example, the end 42 E 1 is positioned adjacent the line 44 , there will be greater variation in printing the feature 42 - 1 in the situation where there was an open space opposite the end 42 E 1 . Accordingly, the overall pattern 40 depicted in FIG. 3C cannot be formed using double patterning techniques. The overall target pattern must be redesigned and/or re-routed, which results in extra time and expense and perhaps the consumption of additional area on a semiconductor chip.

The present disclosure is directed to various methods of making jogged routing layouts that are compliant with double patterning techniques which may solve or at least reduce one or more of the problems identified above.

The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

Generally, the present disclosure is directed to various methods of making jogged routing layouts that are compliant with double patterning techniques and resulting semiconductor devices that contain such jogged routing layouts. In one embodiment, a method is disclosed herein that is directed to the design and manufacture of reticles that may be employed in semiconductor manufacturing. Such a method involves creating an overall target pattern comprised of a plurality of features that includes at least one odd-jogged feature, wherein the odd-jogged feature has a crossover region that connects first and second line portions. In this example, the crossover region has a first dimension in a first direction (the Y-direction) that is greater than a second dimension (i.e., critical dimension) of each of the first and second line portions in a second direction (the X-direction that is transverse to the Y-direction). The method further includes the steps of decomposing the overall target pattern into a first sub-target pattern and a second sub-target pattern, wherein the first sub-target pattern comprises one of the line portions and a first portion of the crossover region and wherein the second sub-target pattern comprises the other of the line portions and a second portion of the crossover region, generating a first set of mask data corresponding to the first sub-target pattern, and generating a second set of mask data corresponding to the second sub-target pattern. In some embodiments, the method further includes the steps of sending the first and second sets of mask data to a mask manufacturer to fabricate a first mask that corresponds to the first sub-target pattern and to fabricate a second mask that corresponds to the second sub-target pattern.

In further more detailed embodiments, the various methods disclosed herein include determining a value for the first dimension of the crossover region at a point where a minimum spacing between features in the first sub-target pattern is equal to or larger than a minimum resolution capability of single patterning technology. The various methods disclosed herein may also include determining a value for an overlay distance between the jogged portions of the first and second sub-patterns at a point where a minimum spacing between the features in the first sub-target pattern is equal to or larger than a minimum resolution capability of single patterning technology.

In another example, one illustrative method disclosed herein involves transferring an overall target pattern to a layer of material, wherein the overall target pattern includes an odd-jogged feature and wherein the overall target pattern is comprised of first and second sub-target patterns. Such a method may involve performing a first etching process through a first mask layer having the first sub-target pattern defined therein to transfer the first sub-target pattern to the layer of material, wherein the first sub-target pattern is comprised of one of the first and second line portions and a first portion of the crossover region of the odd-jogged feature, and performing a second etching process through a second mask layer having the second sub-target pattern defined therein to transfer the second sub-target pattern to the layer of material, wherein the second sub-target pattern comprises the other of the first and second line portions and a second portion of the crossover region of the odd-jogged feature. In a further example, the layer of material having the first and second sub-target patterns defined therein may then be used to transfer the overall target pattern to an underlying layer of material or to a semiconducting substrate.

The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

FIG. 1 is a simplistic depiction of an illustrative prior art double patterning process;

FIGS. 2A-2B depict various illustrative prior art circuit layouts involving jogged features;

FIGS. 3A-3C depict illustrative prior art routing layouts;

FIGS. 4A-4C depict various illustrative embodiments of various method disclosed herein of making jogged routing layouts that are compliant with double patterning techniques; and

FIG. 5 schematically depicts an illustrative system disclosed herein for exposing a plurality of substrates using reticles designed as disclosed herein and for practicing various methods disclosed herein.

While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.

The present disclosure is directed to various methods of making jogged routing layouts that are compliant with double patterning techniques and resulting semiconductor devices that contain such jogged routing layouts. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the methods and devices disclosed herein may be employed in the fabrication of a variety of devices, such as logic devices, memory devices, ASICs, etc. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.

Certain aspects of the present subject matter will now be described with reference to FIGS. 4A-4C . FIG. 4A depicts an illustrative circuit layout pattern 60 comprised of a plurality of rectangular line-type features 60 F, e.g., trenches, lines, etc., and a crossover or jogged feature 62 . The pattern 60 includes five illustrative routing tracks (A-E). The crossover feature 62 is a composite pattern that is comprised of line-type features 62 A, 62 B that are connected together by a crossover region 62 J. All of the features 60 F depicted in FIG. 4A , except the crossover region 62 J, have the same critical dimension 63 in a direction that is transverse to the long axis of the line-type features 60 F (the long axis of the line-type features corresponds with orientation of the routing tracks A-E—hereinafter the “Y-direction” as indicated in FIG. 4A ). The crossover region 62 J depicted in FIG. 4A is sometimes referred to as an odd-jog type feature because the crossover region 62 J spans a distance equal to one pitch, e.g., the distance between the tracks B and C in the depicted example.

Unlike the crossover or jogged portions 22 J, 32 J and 42 J shown in the prior art patterns depicted in FIGS. 3A , 3 B and 3 C, respectively, the crossover region 62 J shown in FIG. 4A has a dimension 62 D in the Y-direction that is greater than the critical dimension of the line portions 62 A, 62 B in a direction that is transverse to the Y-direction (hereinafter the “X-direction” as indicated in FIG. 4A ). Stated simply, in the depicted example, the dimension 62 D is greater than the critical dimension 63 of the line portions 62 A, 62 B of the jogged feature 62 .

In one illustrative example, as depicted in FIG. 4A , the overall target pattern 60 may be decomposed into first and second sub-target patterns 60 A, 60 B, respectively. In this example, the crossover region 62 J is divided into first and second portions 62 J 1 (in pattern 60 A) and 62 J 2 (in pattern 60 B), respectively. FIG. 4B is an enlarged view of the jogged feature 62 .

As reflected in these drawings, the first portion 62 - 1 is comprised of the line-type feature 62 B and a first portion 62 J 1 of the crossover region 62 J. In the depicted example, both the first and second portions 62 J 1 , 62 J 2 of the crossover portion 62 J have the same dimension 62 D in the Y-direction as does the original jogged portion 62 J. By increasing the dimension of the jogged portion 62 J, the relationship between the edge 62 E 1 and the edge 64 E of the feature 64 behaves more like edge-to edge when printed. The edge 62 E 1 of the first portion 62 - 1 is spaced apart from the edge 64 E of the nearest feature 64 in the first sub-target pattern 60 A by a distance 65 that is greater than the minimum spacing allowed for the overall target pattern 60 . The edge 62 E 2 of the second portion 62 - 2 is spaced apart from the edge 66 E of the nearest feature 66 in the second sub-target pattern 60 B by a distance 67 that is greater than the minimum spacing allowed for the overall target pattern 60 . The first and second portions 62 J 1 , 62 J 2 , are sized such that, when these patterns 60 A, 60 B are formed on a product, there will be an area or overlap “D” (see FIG. 4B ) between the edges 62 E 1 and 62 E 2 .

As indicated above, in the depicted example, both the first and second portions 62 J 1 , 62 J 2 of the crossover portion 62 J have the same dimension 62 D in the Y-direction as does the original jogged portion 62 J. However, such a configuration is not required in all applications. In some applications, the Y-direction dimension of both of the portions 62 J 1 , 62 J 2 may be less than the overall Y-direction dimension 62 D of the jogged portion 62 .

Determining the appropriate Y-direction distance 62 D of the jogged portion 62 J of the jogged feature 62 will vary depending on the particular application and a variety of factors. FIG. 4C is a graph that depicts at least some of the factors that may be considered in setting the Y-direction dimension 62 D—or “H”—of the jogged portion 62 J. In FIG. 4C , H is plotted on the horizontal axis, the line “T” represents the smallest space that can be produced using whatever single patterning technology or technique is employed, e.g., DUV lithography, the line “D” represents the overlap of the portions 62 J 1 , 62 J 2 (see FIG. 4B ), and the line “S” represents the spacing ( 65 , 67 shown in FIG. 4A ) between various features in the first and second sub-target patterns 60 A, 60 B. The minimum value of H is where S is approximately equal to T. Of course, if desired, the Y-dimension 62 D of the jogged portion 62 J may be selected to be greater than the aforementioned minimum value of H if plot space allows or if there are other reasons for doing so. Stated another way, a minimum value of H is determined at a point where the minimum spacing between the features in the first sub-target pattern is approximately equal to or larger than the minimum resolution capability of single patterning technology. Similarly, the amount or magnitude of the overlap D between the jogged portions of the first and second is a value that is determined at a point where a minimum spacing between the features in the first sub-target pattern is approximately equal to or larger than a minimum resolution capability of single patterning technology. Meanwhile, the amount of the overlap D must be sufficient to guarantee the connectivity between the first ( 62 J 1 ) and second ( 62 J 2 ) portion of the jogged portion. The data set forth in FIG. 4C can be generated through lithography modeling or real silicon experiments.

Based on current day technology, the following are numerical examples of the various dimensions described above, for one particular example. In one example, T=64 nm (the minimum spacing or pitch), S=60 nm (the dimensions 65 , 67 are the same) and the overlap D=32 nm. In this illustrative example, the minimum value of H is about 70 nm. Of course this is but one numerical example and the various inventions disclosed herein should not be considered to be limited to such an example. Moreover, FIG. 4C is not intended to depict this particular example. Thus, using the methods disclosed herein, even though crossover or jogged feature 62 is an “odd-jog” feature bounded on the left by the line 64 and the right by the line 66 (see FIG. 4A ), the pattern 60 may be formed using double patterning techniques by using masks corresponding to the sub-target patterns 60 A, 60 B.

As noted previously, the methods disclosed herein may be employed to form masks or reticles (the terms are used interchangeably herein) to be used in the manufacture of integrated circuit products. Such masks or reticles generally comprise patterns corresponding to the circuit components that are part of an integrated circuit product. The patterns used to create such masks or reticles are generated utilizing computer-aided design (CAD) programs, wherein this process is sometimes referred to as electronic design automation. Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes.

In addition to the methods described above, other techniques may also be employed to produce more accurate masks. For example, well-known software-based optical proximity correction (OPC) techniques may be performed of the first sub-target pattern 60 A and the second sub-target pattern 60 B in an effort to generate a more accurate mask that can reliably and repeatedly produce the desired pattern on the target material or structure. There are several OPC correction methods that have been employed within the industry, and they may be roughly classified into rule-based approaches and simulation-based approaches. Both of these techniques may be employed with the methods disclosed herein. Additionally, the masks designed as described herein may also include multiple SRAFs, in an effort to produce a more effective and accurate mask.

FIG. 5 schematically depicts an illustrative system 200 comprised of an illustrative photolithography tool 210 (having a light source 211 ), reticles 60 A-M 1 and 60 B-M 2 that correspond to the sub-target patterns 60 A, 60 B, respectively, an illustrative substrate or wafer 214 and the hard mask layer 116 formed above the wafer 214 . The reticles 60 A-M 1 and 60 B-M 2 are depicted as being positioned side by side in the illustrative photolithography tool 200 , but those skilled in the art will recognize that the reticles 60 A-M 1 and 60 B-M 2 will be used in a sequential fashion in a double patterning process and they may be used in any order. At least portions of the data to be used in manufacturing the reticles 60 A-M 1 and 60 B-M 2 may be generated based on data corresponding to the first sub-target pattern 60 A and the second sub-target pattern 60 B, respectively, as described above. The data may then be provided to a reticle manufacturer to manufacture the reticles 60 A-M 1 and 60 B-M 2 . The reticles 60 A-M 1 and 60 B-M 2 may then be employed in the photolithography tool 210 (which may be of any desired configuration and employ any desired wavelength or form of radiation) in a sequence of traditional photolithography operations, whereby the overall target pattern 60 , defined by the combination of the features in both of the reticles 60 A-M 1 and 60 B-M 2 , may be transferred to a layer of material, such as the illustrative patterned hard mask layer 116 A depicted in FIG. 5 . Thereafter, the patterned hard mask layer 116 A may be used in fabricating or defining various portions or regions of an integrated circuit product that will be formed in and above the substrate 214 . The reticles 60 A-M 1 and 60 B-M 2 may be used to form patterned layers of material above subsequently processed wafers as processing continues. Of course, as noted above, the methods disclosed herein may be employed to transfer the overall target pattern 60 to a material layer or a substrate without the need for the hard mask layer 116 A depicted in FIG. 5 .

In one embodiment, a method is disclosed herein that is directed to the design and manufacture of reticles that may be employed in semiconductor manufacturing. In one example, the method involves creating an overall target pattern 60 comprised of a plurality of features 60 F that includes at least one odd-jogged feature 62 , wherein the odd-jogged feature 62 has a crossover region 62 J that connects first and second line portions 62 A, 62 B. In this example, the crossover region 62 J has a first dimension 62 D in a first direction (the Y-direction that is parallel to a long-axis of one the first and second line portions 62 A, 62 B) that is greater than a second dimension 63 of each of the first and second line portions 62 A, 62 B in a second direction (the X-direction that is transverse to Y-direction. The method further includes the steps of decomposing the overall target pattern 60 into a first sub-target pattern 60 A and a second sub-target pattern 60 B, wherein the first sub-target pattern 60 A comprises one of the line portions 60 A, 60 B and a first portion 62 J 1 of the crossover region 62 J and wherein the second sub-target pattern 60 B comprises the other of the line portions 60 A, 60 B, and a second portion 62 J 2 of the crossover region 62 J, generating a first set of mask data corresponding to the first sub-target pattern 60 A, and generating a second set of mask data corresponding to the second sub-target pattern 60 B. In some embodiments, the method further includes the steps of sending the first and second sets of mask data to a mask manufacturer to fabricate a first mask 60 A-M 1 that corresponds to the first sub-target pattern 60 A and to fabricate a second mask 60 B-M 2 that corresponds to the second sub-target pattern 60 B.

In another example, one illustrative method disclosed herein involves transferring an overall target pattern 60 comprised of first and second sub-target patterns 60 A, 60 B to a layer of material. Such a method may involve performing a first etching process through a first mask layer having the first sub-target pattern 60 A defined therein to transfer the first sub-target pattern 60 A to the layer of material, wherein the first sub-target pattern 60 A is comprised of one of the first and second line portions 62 A, 62 B and a first portion 62 J 1 of the crossover region 62 J of the odd-jogged feature 62 , and performing a second etching process through a second mask layer having the second sub-target pattern 60 B defined therein to transfer the second sub-target pattern 60 B to the layer of material, wherein the second sub-target pattern 60 B comprises the other of the first and second line portions 62 A, 62 B and a second portion 62 J 2 of the crossover region 62 J of the odd-jogged feature 62 . In a further example, the layer of material having the first and second sub-target patterns 60 A, 60 B defined therein may then be used to transfer the overall target pattern to an underlying layer of material or to a semiconducting substrate.

The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.