DC-DC converter switching transistor current measurement technique

This application is a divisional of U.S. application Ser. No. 11/173,760, filed Jun. 30, 2005 now U.S. Pat. No. 8,134,548, which is incorporated herein by reference in its entirety.

DC-DC converters typically craft a DC voltage by full wave rectifying and filtering one or more time varying signals. Because of the switching undertaken in the full wave rectification process, significant amounts of current are frequently “switched” back-and-forth at rapid pace by large transistors. It is often helpful to measure the current through these transistors to, for instance, determine whether or not the DC-DC converter is being loaded, monitor any ripple currents resulting from rectification, etc.

Two “straight-forward” techniques are readily known in the art for measuring current: 1) shunt inductance; and, 2) series resistance. Shunt inductance induces a current measurement signal in an inductor by coupling magnetic fields that are produced by the current signal being measured through the inductor. Unfortunately, shunt inductance is not practical for rapidly changing currents because the bandwidth of an inductor is limited (i.e., the inductor will increasingly attenuate the current measurement signal as its frequency increases).

The series resistance technique, which is shown in FIG. 1 , does not typically suffer from limited bandwidth issues because a pure resistance does not change its resistive properties as a function of signal frequency. Unfortunately, however, the series resistance technique is also not practical for large currents (such as those drawn by a DC-DC converter's switching transistors) because a large current being driven through a resistance will tend to dissipate large amounts of power (through the relationship P=I 2 R) which may result in overheating; or, if the power “problem” is handled by using a very small series resistance, inaccuracy results because the signal V=I*R may become too small to measure.

FIGURES

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

FIG. 1 shows resistance couples in series with a DC-DC converter switching transistor;

FIG. 2 shows an embodiment of a current measurement circuit coupled to a DC-DC converter switching transistor;

FIG. 3 shows an equivalent circuit for the circuit of FIG. 2 ;

FIG. 4 shows another circuit that measures DC-DC converter switching transistor current using a similar M 1 through M 4 structure as shown in FIG. 2 ;

FIG. 5 shows an extension of the circuit of FIG. 4 capable of providing an indication of the output current from the pair of switching transistors Q 1 and Q 2 ;

FIG. 6 shows a computing system whose processor(s) include a DC-DC converter.

FIG. 2 shows a circuit directed to measuring the I DS current of transistor Q 1 without the use of a series resistance through which the I DS current flows. Here, transistor Q 1 may be a large switching transistor whose drain-to-source current (I DS ) is rapidly changing with large amplitude. A pair of transistors M 1 , M 2 having their conductive channels coupled in series (where, the conductive channel of a transistor is understood to be the channel between its drain and source nodes). The drain of M 1 is coupled to the drain of the switching transistor's conductive channel. The source of M 2 is coupled to the source of the switching transistor's conductive channel (through the ground node). A node between the M 1 and M 2 transistors is coupled to an input of an amplifier (the source node of M 5 ). A second pair of transistors M 3 and M 4 have their conductive channels coupled in parallel (their drains are tied together and their source nodes are tied to ground) and a node between the second pair of transistors M 3 , M 4 is coupled to a reference input of the amplifier (the source node of M 6 ).

According to the theory of operation of the circuitry of FIG. 2 , a current flow of approximately kI DS will flow through transistor M 1 , where k<1 (e.g., in many applications k is expected to be within a range of 0.0001 to 0.01 inclusive). The kI DS current flow through transistor M 1 influences an output signal Io which can be used as an indicator of the current I DS through transistor Q 1 . In a typical implementation transistors M 1 and M 2 , as well as M 3 and M 4 are scaled down versions of transistor Q 1 (e.g., being designed with identical doping profiles and gate lengths but with different gate widths). Since a large transistor Q 1 is often implemented as a parallel connection of many identical small transistors (legs), the smaller transistors M 1 , M 2 , M 3 , and M 4 can be implemented using just a few of the same small transistors.

The proportionality factor can be approximately computed from the transistors' widths as 1/k=W Q1 *(1/W M1 +1/W M2 ). In some applications a value of k>1 may be desirable. The M 1 and M 2 structure essentially enables fast and accurate measurement of the I DS current without actually imposing a series resistance through the I DS current path. To ensure proper operation, M 1 and M 3 may be matched and M 2 and M 4 may be matched respectively. To improve the accuracy at larger drain-to-source voltages V DS in Q 1 , especially, when Q 1 is operating in saturation, M 1 may be chosen to be smaller than M 2 . To enhance the output signal Io, M 1 may be chosen to be larger than M 2 .

Transistors M 5 , M 6 , M 7 and M 8 form a common gate amplifier having: 1) a reference leg M 6 , M 7 whose current, I BIAS , flows into the resistive network formed by transistors M 3 and M 4 ; and, 2) a measurement leg M 5 , M 8 whose current I x flows into the resistive network formed by transistors M 1 and M 2 .

The principle of operation of the entire circuit is that voltage changes in proportion to kI DS at the source of transistor M 5 causes the gate-to-source voltage of transistor M 5 to differ with respect to that of transistor M 6 such that an output current Io is created having a component that varies in proportion to kI DS . The current I BIAS may be injected using various techniques, such as, e.g., using a reference current circuit or a resistor connected to the gates of M 6 and M 7 .

The principle of operation of the circuit of FIG. 2 is more easily viewed with the equivalent circuit of FIG. 3 . Comparing FIGS. 2 and 3 , note that: 1) transistor M 1 has been replaced by a variable resistance R 1 and a voltage source V DS causing a current of kI DS ; 2) transistor M 2 has been replaced by resistance R 2 ; 3 ) transistor M 3 has been replaced by variable resistance R 3 ; and, 4) transistor M 4 has been replaced by resistance R 4 .

Transistors M 2 and M 4 are designed to be in the linear mode over the range of operation for the circuit. Therefore, M 2 and M 4 will behave like resistors (i.e., approximately a linear relationship between its drain-to-source voltage and its drain-to-source current). Moreover, like M 2 and M 4 , transistors M 1 and M 3 are also ideally designed to remain in linear mode of operation, when transistor Q 1 is in linear mode, and to be in saturation mode when Q 1 is in saturation mode. In order to help effect this behavior, the gates of transistors M 2 and M 4 are tied to a fixed voltage (V CC ) and the gates of transistors M 1 and M 3 are tied to the gate of transistor Q 1 .

With transistors M 5 and M 6 in saturation mode, and with transistors M 7 and M 8 forming a current mirror, it can be shown that the output current Io for the circuit of FIG. 3 can be approximated as:

Io≈kI DS ( R 1/( R 1//R2 +R 5))+(( R 1//R2)−( R 3//R4))/( R 1//R2 +R 5)) I BIAS   Eqn. 1

where I DS is the current being measured (i.e., the drain-to-source current of transistor Q 1 ), k is a proportionality constant between the drain-to-source currents of transistors Q 1 and M 1 , and R 5 is the common-gate input resistance of transistor M 5 . Moreover,

R 3//R4=( R 3 R 4)/( R 3 +R 4)  Eqn. 2a

R 1//R2=( R 1 R 2)/( R 1 +R 2)  Eqn. 2b

which corresponds to the effective resistances of resistors R 3 and R 4 in parallel and R 1 and R 2 in parallel, respectively. Since R 1 =R 3 and R 2 =R 4 , I BIAS does not add to the output signal Io. The value of R 5 depends on the transconductance parameter 13 of M 5 and on the bias current I BIAS :

R 5=1/sqrt(2β M5 ( I BIAS −Io ))  Eqn. 3

In a typical design R 5 may be large compared to R 1 //R 2 , e.g., ten times larger, to reduce the power consumption of the common-gate amplifier. In other designs R 5 may be comparable to or even smaller than R 1 //R 2 in order to improve linearity. To ensure proper operation the bias current should be larger than the maximum output current: I BIAS >Io. For negative currents Io<0 the bias current may be reduced to a very small value, e.g., by operating M 5 and M 6 at or slightly above threshold. The presence of M 3 also provides for good suppression of noise from the gate node of transistor Q 1 since the noise injected through the gate capacitances of M 1 and M 3 approximately cancels out. Note that although the reference voltage of FIGS. 2 and 3 correspond to a ground node, another fixed voltage could be used (such as a supply node) provided appropriate offset were applied to V CC .

Other Circuits

FIG. 4 provides another circuit design that uses the M 1 through M 4 structure as a device for measuring I DS , but uses a different common-gate amplifier, formed by M 5 through M 11 , to generate the output signal Io. This amplifier is essentially equivalent to a combination of two replicas of the amplifier M 5 through M 8 in FIG. 2 and provides improved range and linearity at a reduced bias current.

When the current I DS of Q 1 is small, i.e., the output signal is approximately −I BIAS <Io<+I BIAS , both parts of the amplifier, M 5 through M 8 and M 9 through M 11 respectively contribute to the output signal Io. When current is large and positive, i.e., Io>+I BIAS , M 9 through M 11 will increase their contribution to Io due to the nonlinearity of the circuit, whereas M 5 through M 8 will reduce and eventually cease their contribution to the output signal.

Furthermore, when the current is large and negative, i.e., Io<−I BIAS , M 9 through M 11 will reduce their contribution to Io and M 5 through M 8 will take over. Thus, the non-linearities of both halves of the amplifier compensate each other, resulting in improved linearity and range at a smaller bias current. The method for properly choosing the bias current I BIAS and the sizes of M 5 through M 11 usually involves simple calculations and circuit simulations, which anyone skilled in the art can easily carry out.

FIG. 5 shows a circuit that measures the current through both of switching transistors Q 1 and Q 2 . M 13 through M 16 are the PMOS equivalent of M 1 through M 4 respectively, and, M 7 , M 8 , M 11 , M 12 are coupled so that they become the PMOS equivalent of M 5 , M 6 , M 10 and M 9 respectively. Arrangement in this manner allows for an output Io that varies with I DS — Q2 -I DS — Q1 .

Possible Applications of Current Measurement Circuits

It is envisioned that embodiments of the current measurement approaches described herein can be used in “on-chip” DC-DC converters. A DC-DC converter is a device that converts a first fixed voltage into a second fixed voltage. Here, for example, transistor Q 1 (and transistors Q 1 and Q 2 in FIG. 4 ) can be a large switching transistor in an “on-chip” DC-DC converter (and transistors Q 1 and Q 2 can be large switching transistors in an “on-chip” DC-DC converter).

The current measurement circuit can be used for various functions such as, to name a few: 1) soft-switching, i.e., to monitor the currents through switching transistors in order to determine the proper time for turn-off; 2) monitoring the ripple current in DC-DC converters; 3) “safe turn off” in “on-chip” DC-DC converters (e.g., turning off the DC-DC converter when the inductor currents flowing through the switching transistors are small enough to prevent voltage overshoot); and, 4) monitoring the load current, e.g., in “on-chip” DC-DC converters used to a CPU (central processing unit) or part of a CPU.

FIG. 6 shows an embodiment of a computing system. The exemplary computing system of FIG. 6 includes: 1) one or more processors 601 having an “on-chip” DC-DC converter 610 ; 2) a memory control hub (MCH) 602 ; 3) a system memory 603 (of which different types exist such as DDR RAM, EDO RAM, etc); 4) a cache 604 ; 5) an I/O control hub (ICH) 605 ; 6) a graphics processor 606 ; 6) a display/screen 607 (of which different types exist such as Cathode Ray Tube (CRT), Thin Film Transistor (TFT), Liquid Crystal Display (LCD), DPL, etc.; 8) one or more I/O devices 608 .

The one or more processors 601 execute instructions in order to perform whatever software routines the computing system implements. The instructions frequently involve some sort of operation performed upon data. Both data and instructions are stored in system memory 603 and cache 604 . Cache 604 is typically designed to have shorter latency times than system memory 603 . For example, cache 604 might be integrated onto the same silicon chip(s) as the processor(s) and/or constructed with faster SRAM cells whilst system memory 603 might be constructed with slower DRAM cells.

By tending to store more frequently used instructions and data in the cache 604 as opposed to the system memory 603 , the overall performance efficiency of the computing system improves. System memory 603 is deliberately made available to other components within the computing system. For example, the data received from various interfaces to the computing system (e.g., keyboard and mouse, printer port, LAN port, modem port, etc.) or retrieved from an internal storage element of the computing system (e.g., hard disk drive) are often temporarily queued into system memory 603 prior to their being operated upon by the one or more processor(s) 601 in the implementation of a software program.

Similarly, data that a software program determines should be sent from the computing system to an outside entity through one of the computing system interfaces, or stored into an internal storage element, is often temporarily queued in system memory 603 prior to its being transmitted or stored. The ICH 605 is responsible for ensuring that such data is properly passed between the system memory 603 and its appropriate corresponding computing system interface (and internal storage device if the computing system is so designed). The MCH 602 is responsible for managing the various contending requests for system memory 603 access amongst the processor(s) 601 , interfaces and internal storage elements that may proximately arise in time with respect to one another.

One or more I/O devices 608 are also implemented in a typical computing system. I/O devices generally are responsible for transferring data to and/or from the computing system (e.g., a networking adapter); or, for large scale non-volatile storage within the computing system (e.g., hard disk drive). ICH 605 has bi-directional point-to-point links between itself and the observed I/O devices 608 .

In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.