Power module and the method of packaging the same

This application claims the benefit of U.S. Provisional Application No. 61/437,495, filed on Jan. 28, 2011, the contents of which are incorporated herein by reference.

1. Field of the Invention

The invention relates to a power module, and in particular, relates to a method of packaging the power module.

2. Description of the Related Art

Power converters have been widely utilized in commercialized power management category. For example, DC/DC conversion, or providing constant current flow. FIG. 1A shows a diagram of a traditional power converter 100 . The power converter 100 comprises a pulse width modulating controller (PWM controller), NMOSFETs Q 1 and Q 2 , an inductor L 1 , and a capacitor C 1 . The PWM controller controls ON/OFF state of the NMOSFETs Q 1 and Q 2 by providing a first control signal Hdry to a gate of the NMOSFET Q 1 and providing a second control signal Ldry to a gate of the NMOSFET Q 2 , wherein the first control signal Hdry is a periodical signal, and the second control signal Ldry is complemetary to the first control signal Hdrv. When the first control signal Hdry is HIGH and the second control signal Ldry is LOW, the NMOSFET Q 1 is ON and the NMOSFET Q 2 is OFF, and the inductor L 1 and the capacitor C 1 are charged through the NMOSFET Q 1 by an input voltage VDD. When the first control signal Hdry is LOW and the second control signal Ldry is HIGH, the NMOSFET Q 1 is OFF and the NMOSFET Q 2 is ON, and the inductor L 1 and the capacitor C 1 are discharged through the NMOSFET Q 2 toward a reference voltage level GND, The power converter 100 thus provides a constant voltage output Vload to a load Rload.

With advancement of VLSI fabrication technology, cost, footprint and design flexibility of power modules have become crucial. Modulized packaging of power modules have gained a significant advantage over traditional packaging. For example, as shown in FIG. 1B , a power converter 200 integrates a PWM controller, and NMOSFETs Q 1 and Q 2 into a multi-chip module (MCM) 20 . FIG. 1C shows another power converter 300 , which integrates NMOSFETs Q 1 and Q 2 into an independent package structure 30 . However, the power modules mentioned above are inconvenient when being incorporated with different PWM controllers and still have room for improvement.

Some exemplary embodiments of the invention show a power module, which comprises a substrate; a inductor formed on the substrate, wherein the inductor comprises a conductive path layer with a particular pattern; a connection layer formed on the substrate, wherein the connection layer is electrically connected to a first terminal of the inductor; and a first transistor, electrically coupled on the substrate through the connection layer.

Other exemplary embodiments of the invention show a method of packaging a power module, which comprises providing a substrate; forming a connection layer and a conductive path layer on the first side of the substrate, wherein the conductive path layer comprises a particular pattern to work as an inductor, and the connection layer is electrically connected to a first terminal of the conductive path layer; and mounting at least one transistor electrically through the conductive path layer on the substrate.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1A is a circuit diagram of a traditional power converter 100 ;

FIG. 1B is a circuit diagram of a power module 20 and corresponding power converter 200 ;

FIG. 1C is a circuit diagram of a power module 30 and corresponding power converter 300 ;

FIG. 2 is a circuit diagram of a power module 40 and corresponding power converter 400 ;

FIG. 3A-8A are top views showing the process steps of fabricating a power module 40 .

FIG. 3B-8B are cross sectional views showing the process steps of fabricating a power module 40 .

FIG. 2 shows a circuit diagram of power module 40 according to an embodiment of the invention and a corresponding power converter 400 using the power module 40 . The power converter 400 comprises a power module 40 , which integrates a first transistor Q 1 , a second transistor Q 2 , and an inductor L 1 into a package; a PWM controller controlling ON/OFF states of the first transistor Q 1 and the second transistor Q 2 by sending a first control signal Hdry and a second control signal Ldry to gates of the transistors Q 1 and Q 2 , respectively; and a capacitor C 1 .

When the first control signal Hdry switches the first transistor to ON, the second control signal Ldry switches the first transistor to OFF. Thus, the inductor L 1 and the capacitor C 1 are charged via the first transistor Q 1 by an input voltage VDD. When the first control signal Hdry switches the first transistor to OFF, the second control signal Ldry switches the first transistor to ON. Thus, the inductor L 1 and the capacitor C 1 then discharge via the first transistor Q 1 to a reference voltage level GND. Therefore the power converter 400 provides a constant output voltage Vload to a load Rload.

According to some embodiments of the invention, the second transistor Q 2 in the power module 40 can be replaced by a switch device or a diode (not shown). The power module 40 described above is a buck converter, however it is not intended to limit the scope of the invention. The power module in the invention can be any power module comprising an inductor and at least a transistor, such as a boost converter, a buck-boost converter, a cuk converter or a single-ended primary industry converter (SEPIC), etc.

The following is an embodiment of packaging a power module 40 of the invention. It is for exemplary purposes and is not intended to limit the scope of the invention. Those skilled in the art can make any modification or substitution to carry out the same result and/or achieve the same advantages of the embodiments introduced herein using the examples, applications and principles disclosed in the invention.

FIG. 3A to 8A show the top views of the power module 40 during fabrication steps in an embodiment of the invention. FIG. 3B to 8B show the cross sectional views of the power module 40 during fabrication steps corresponding to FIG. 3A to 8A . Some of the exemplary drawings above are adjusted or modified for easy understanding. Moreover, parts and/or devices not shown in the figures are well-known by those who skilled in the art.

Refer to FIGS. 3A and 3B , wherein FIG. 3B is the corresponding cross-sectional view of FIG. 3A . Firstly, a substrate 41 is provided. Only a portion of the substrate 41 is shown in FIGS. 3A and 3B . In an embodiment, multiple following procedures can be performed simultaneously on the substrate 41 to form a plurality of power modules 40 . In an embodiment, the material of the substrate 41 is glass. However, the material of the substrate 41 can also be other insulators such as quartz or plastic.

After, form a conductor layer on the substrate 41 and define a pattern on it using lithography. An etching process is performed on the conductive layer to further form a patterned first connection layer 42 and a conductive path layer 43 . The first connection layer 42 provides connections between external circuits and devices within the power module 40 . The first connection layer 42 comprises first to fifth portions, 42 - 1 to 42 - 5 . For easy understanding, reference numerals of the first connection layer 42 will not be shown in later drawings. The conductive path layer 43 shown in FIG. 3A has a particular shape, for example, it can be a rectangular, polygonal, or circular spiral shape. The conductive path layer 43 can also be a transmission line shape or a meander shape. The conductive path layer 43 works to form an inductor L 1 and comprises a first terminal 43 A and a second terminal 43 B. The materials of the first connection layer 42 and the conductive path layer 43 can be metals such as Al and Cu, conductive ceramics, conductive macromolecular materials, or combinations thereof. The first connection layer 42 and the conductive path layer 43 can be formed of the same material or different materials. The first connection layer 42 and the conductive path layer 43 can be formed on the substrate 41 simultaneously or sequentially.

Inductors usually occupy a significant amount of footprint in traditional power converter. However with the advancement of VLSI fabrication technology, transistors with faster switching rates are available, therefore inductors with smaller footprints and lower inductance can be incorporated to form a compact power module 400 . In a preferred embodiment, the inductance of the inductor L 1 is about 30 nH. However, the actual inductance value and size of the inductor depends on the switching speed of corresponding transistors.

Refer to FIGS. 4A and 4B , wherein FIG. 4B is the side view along a cross section AA′ of FIG. 4A . A protection layer on the first connection layer 42 and the conductive path layer 43 is formed, and a lithography process is performed to define a pattern, and a patterned first protection layer 44 is formed (shown in FIG. 4B ). The first protection layer 44 has a plurality of windows W 1 , exposing the third portion 42 - 3 of the first connection layer 42 , and the first portion 43 A of the conductive path layer 43 . Materials of the first protection layer 44 can be solder mask, Benzocyclobutene (BCB), Polyimide, or combinations thereof. After, a metal layer is formed, and a pattern is defined using a lithography process. Then an etching step is performed to form a second connection layer 45 . The second connection layer 45 is electrically connected to the third portion 42 - 3 of the first connection layer 42 and the first portion 43 A of the conductive path layer 43 via the windows W 1 .

Refer to FIGS. 5A and 5B , wherein FIG. 5B is the side view along the cross section AA′ of FIG. 5A . A second protection layer 46 is formed on the second connection layer 45 and the first protection layer 44 , and a lithography process is performed to define a particular pattern. After, an etching process is performed to form a plurality of windows W 2 on the second protection layer 46 and the first protection layer 44 (shown in FIG. 5B ), exposing the first to fifth portions 42 - 1 to 42 - 5 of the first connection layer 42 . After, transistors comprising a first transistor Q 1 and a second transistor Q 2 are electrically mounted on the substrate 41 via the first to fifth portions 42 - 1 to 42 - 5 of the first connection layer 42 . In an embodiment of the invention, the first transistor Q 1 and the second transistor Q 2 are power NMOSFETs.

FIG. 5B shows the first transistor Q 1 electrically connected to the first connection layer 42 through the window W 2 , wherein the gate G 1 of the first transistor Q 1 is electrically connected to the second portion 42 - 2 of the first connection layer 42 , and the source S 1 of the first transistor Q 1 is electrically connected to the third portion 42 - 3 of the first connection layer 42 , and the drain D 1 of the first transistor Q 1 is electrically connected to the first portion 42 - 1 of the first connection layer 42 .

The second transistor Q 2 is electrically connected to the first connection layer 42 through the window W 2 , wherein the drain D 2 of the second transistor Q 2 is electrically connected to the third portion 42 - 3 of the first connection layer 42 , the gate G 2 of the second transistor Q 2 is electrically connected to the fourth portion 42 - 4 of the first connection layer 42 , and the source S 2 of the first transistor Q 2 is electrically connected to the fifth portion 42 - 5 of the first connection layer 42 .

In a preferred embodiment, the first transistor Q 1 and the second transistor Q 2 are discrete package units formed by chip-scale packaging, with through-substrate vias formed at the bottom side of the package units for external connections. Terminals of the first transistor Q 1 and the second transistor Q 2 electrically connect to the first to the fifth portions 42 - 1 to 42 - 5 of the first connection layer 42 through the windows W 2 and through-substrate vias by solder bumps or copper pillars. In other embodiments, the second transistor Q 2 can be replaced by a diode or a switching device.

Refer to FIGS. 6A and 6B , wherein FIG. 6B is the side view along the cross section AA′ of FIG. 6A . After mounting of the transistors Q 1 and Q 2 , a carrier substrate 47 is attached on the first side of the substrate 41 , which is on the same side where the transistors Q 1 and Q 2 are mounted (shown as FIG. 6B ), and the carrier substrate 47 is temporarily fixed on the substrate 41 by gluing, in order to hold the substrate 41 in later processes. In some embodiments of the invention, the materials of the carrier substrate 47 can be glass or plastic, and the materials of glue can be polymers such as acrylic or epoxy resin. After, a plurality of openings comprising opening O 1 to opening O 5 are defined on the second side of the substrate 41 along a predetermined scribe lines SL. The opening O 1 to the opening O 5 can be formed using laser patterning or etching processes. Openings can be rectangular or circular shaped, and their locations are shown in FIG. 6A . For simplicity, the carrier substrate 47 is not shown in FIG. 6A .

As shown in FIG. 6B , openings O 2 and O 3 have leaning sidewalls, and the second portion 42 - 2 of the connection layer 42 and second terminal 43 B of the conductive path layer 43 are exposed at the bottom of the openings O 2 and O 3 . The openings O 1 , O 4 and O 5 have leaned sidewalls, and the first portion 42 - 1 , the fourth portion 42 - 4 and the fifth portion 72 - 5 of the connection layer 42 are exposed at the bottom of the openings O 1 , O 4 and O 5 .

Refer to FIGS. 7A and 7B , wherein FIG. 7B is the side view along the AA′ cross section of FIG. 7A . A conductive layer is formed on the second side of the substrate 41 . After defining its pattern using the lithography process and etching step, a plurality of conductive contacts T 1 to T 5 are formed on the openings O 1 to O 5 on the second side of the substrate 41 , respectively. In some embodiments of the invention, the conductive contacts T 1 to T 5 can be formed by sputtering, electroplating or PECVD. Materials of the conductive contacts T 1 to T 5 can be metal, such as Copper, Aluminum, Nickel etc., or combinations thereof.

As shown in FIG. 7B , each of the conductive contacts T 2 and T 3 has a terminal extending along the sidewalls of the openings O 2 and O 3 to the bottom of the openings O 2 and O 3 respectively and is electrically connected to the second portion 42 - 2 of the connection layer 42 and the second terminal 43 B of the conductive path layer 43 respectively. Each of the conductive contacts T 2 and T 3 has another terminal extending on the second side of the substrate 41 . Same as above, each of the conductive contacts T 1 , T 4 and T 5 has a terminal extending along the sidewalls of the openings O 1 , O 4 and O 5 to the bottom of the openings O 1 , O 4 and O 5 respectively and is electrically connected to the first portion 42 - 1 of the connection layer 42 , the fourth portion 42 - 4 of the connection layer 42 , and the fifth portion 42 - 5 of the connection layer 42 , respectively. Each of the conductive contacts T 1 , T 4 and T 5 has another terminal extending on the second side of the substrate 41 .

A solder mask (not shown) is formed covering the conductive contacts T 1 to T 5 , preventing the conductive contacts T 1 to T 5 from being contaminated or damaged. The solder mask has a plurality of windows for forming solder bumps (not shown) as pins of the power module 40 for external connections. After, the substrate 41 is sliced along the scribe lines SL to separate it into at least a die 41 ′, and the carrier substrate 47 is removed hereafter. Finally, an encapsulation 48 (as shown in FIG. 8B ) is formed on the first side of the die 41 ′ to cover the transistors Q 1 and Q 2 . A discrete packaged power module 40 is shown in FIG. 8A . FIG. 8B is the side view along the AA′ cross section of FIG. 8A .

Embodiments of power module process steps disclosed above are not intended to limit the scope of the invention. The process steps can be interchanged, altered or modified. For example, in another embodiment, after formation of the second protection layer 46 , the carrier substrate 47 is fixed on the substrate 41 , and then the conductive contacts T 1 to T 5 are formed. After, solder mask and solder bumps are formed, and then the substrate 41 is sliced into at least a die 41 ′, and the carrier substrate 47 is removed from die 41 ′. Finally, the transistor devices Q 1 and Q 2 are mounted on the die 41 ′, and the encapsulation 48 is formed.

In the embodiments above, the conductive contact T 1 in the power module 40 is for receiving a DC power supply, the conductive contact T 2 in the power module 40 is for receiving a first control signal controlling ON/OFF states of the first transistor Q 1 ; the conductive contact T 3 in the power module 40 is for electrically connecting the second terminal 43 B of the conductive path layer 43 to a capacitor and a load; the conductive contact T 4 in the power module 40 is for receiving a second control signal controlling ON/OFF states of the second transistor Q 2 which is complementary to the first control signal, and the conductive contact T 5 in the power module 40 is coupled to a reference voltage level.

In the invention, an inductor and a connection layer in the power module are directly formed by deposition or electroplating, which significantly lowers the cost and simplifies fabrication. Integrating chip-scale packaged transistors and inductor further improves footprint and saves the problem of matching transistors with inductors for designers. Furthermore, a wide variety of PWM controllers can be incorporated as long as their driving signal frequencies are on par with the switching speed of transistors in the power module to promote power management design efficiency.