Technology of memory repair after stacking of three-dimensional integrated circuit

This application claims the priority benefit of Taiwan application serial no. 100132840, filed on Sep. 13, 2011. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

1. Field of the Invention

The disclosure relates to a three-dimensional integrated circuit (3-D IC), and more particularly, to a 3-D IC and a method capable of repairing a memory chip after the chip is stacked with a controller chip.

2. Description of Related Art

A 3-D IC stacks and connects chips vertically by using the through-silicon via (TSV) technology. A TSV is an electrical conductor which passes completely through the silicon substrate of a chip. By introducing the vertical interconnect, a system design allows accessing the front side of the chip from the backside or vice versa. The length of the TSV is about equal to the thickness of the chip, and is usually shorter than 100 μm. Hence, a long wire between two components on a system on chip (SoC) may be eliminated by placing the two components on two separate chips and routing their connection through the TSV, so the propagation delay can be reduced significantly. In addition, the density of the TSVs may be higher than 100/mm 2 , and therefore, the TSVs may provide a high bandwidth in the 3-D IC.

At present, a spare memory (having multiple spare memory cells that are added into a memory array typically in a form of redundant row or redundant column) is usually built in a memory chip, so as to replace a damaged memory cell if there exists one.

However, even a well tested and repaired memory chip may be damaged again during the process of TSV forming, wafer thinning, and chip stacking of the 3-D IC. At this time, the spare memory may not be used up, but the chip stacking should be announced as a failure, because it is impossible to record any newly added failure address after chip stacking. Using a conventional method of programming by laser excision, for example, the front side of a chip after stacking may be covered by an upper- or lower-layer chip, and unable to have a fuse be blown. Obviously, as it fails to repair the memory chip by replacing the damaged memory cell with a spare after chip stacking, the enhancement of manufacturing yield of the 3-D IC becomes one of the major tasks at present.

Accordingly, an exemplary embodiment provides a 3-D IC, which at least includes a controller chip and a memory chip. The controller chip includes a control circuit, and the memory chip includes an address translation circuit with an external activation/enablement function. After the controller chip and the memory chip are stacked, the controller chip, in response to the setting of the control circuit and a preset condition associated with the address translation circuit in the memory chip, controls the address translation circuit through at least one vertical interconnect, so as to activate/enable at least one spare (i.e. unused redundant row or redundant column) in the memory chip to repair at least one damaged memory cell in the memory chip after stacking.

Another exemplary embodiment provides a method for memory repair after chip stacking of a 3-D IC, which includes: designing a control circuit in a controller chip, and designing an address translation circuit with an external activation/enabling function in a memory chip; activating the external activation/enablement function for unused spares in the memory chip before stacking; and after the controller chip and the memory chip are stacked, enabling the controller chip to, in response to the setting of the control circuit, control the address translation circuit in the memory chip through at least one TSV, so as to activate/enable at least one redundant row and/or one redundant column in the memory chip to repair at least one damaged memory cell in the memory chip.

Furthermore, another exemplary embodiment provides a method for memory repair after chip stacking of a 3-D IC, which includes: activating/enabling at least one spare in a stacked memory chip through a stacked controller chip to replace at least one damaged memory cell in the stacked memory chip.

It should be noted that the above descriptions and the following embodiments are merely exemplary for illustration, which are not intended to limit the scope of the disclosure.

Several exemplary embodiments accompanied with figures are described below to further clarify the disclosure in detail.

The accompanying drawings are included to provide further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments and, together with the descriptions, serve to explain the principles of the disclosure.

FIG. 1 is a schematic view of a 3-D IC, consisting of a controller chip Die_ 1 and a memory chip Die_ 0 , according to an exemplary embodiment.

FIG. 2 is an operational view of an address translation circuit of a memory chip Die_ 0 according to an exemplary embodiment.

FIG. 3 to FIG. 5 are schematic views of an address translation circuit of a memory chip Die_ 0 according to another exemplary embodiment.

FIG. 6 is a flow chart of a method for memory repair after chip stacking of a 3-D IC according to an exemplary embodiment.

The exemplary embodiments of the disclosure are illustrated in detail below with reference to the accompanying drawings. In addition, components/members of the same reference numerals are used to represent the same or similar parts in the accompanying drawings and implementations wherever it is possible.

It should be noted that, at present, the process to manufacture a memory chip before stacking becomes mature as time passes by. The number of damaged memory cells that need to be repaired (namely, bit failures) is decreasing, and the number of spares that are unused is increasing. In such a situation, the disclosure provides a technique of memory repair after chip stacking, to activate/enable a spare in a memory chip from another stacked chip. In this manner, an inconvenient access to an internal fuse circuit after chip stacking is solved. At the same time, flexible usage of the spare memory is provided, and the yield of the 3-D IC is improved.

Accordingly, FIG. 1 is a schematic view of a 3-D IC 10 according to an exemplary embodiment. Referring to FIG. 1 , the 3-D IC 10 includes at least a controller chip Die_ 1 and a memory chip Die_ 0 , where a redundant row R_row[0] and a redundant column R_col[0] are equipped in the memory chip Die_ 0 , but the disclosure is not limited thereto. The controller chip Die_ 1 may include a control circuit formed by two sub-control units CB 0 and CB 1 , corresponding to the two redundant components. The memory chip Die_ 0 may include an address translation circuit with an external activation/enablement function.

In the exemplary embodiment, after the controller chip Die_ 1 and the memory chip Die_ 0 are stacked, the controller chip Die_ 1 may, in response to the setting of the control circuit and a preset condition associated with the address translation circuit capable of external activation/enablement (which will be described later), control the address translation circuit of the memory chip Die_ 0 through vertical interconnects (for example, TSVs V 0 and V 1 ) to activate/enable either redundant row R_row[0] or redundant column R_col[0] in the memory chip Die_ 0 , so as to repair a damaged memory cell DMC selected by a column col[0] and a row row[0] in the memory chip Die_ 0 .

More clearly, the address translation circuit of the memory chip Die_ 0 may include P-type transistors P 1 and P 2 , N-type transistors N 1 and N 2 , fuse sets FS 1 and FS 2 (each consisting of multiple fuses and multiple N-type transistors as selectors), and an address translation circuit external activating/enabling unit formed by P-type transistors P 3 to P 5 , N-type transistors N 3 to N 9 , inverter INV, and fuse Fx. FIG. 1 shows only main circuit components of the fuse sets. Other circuit design may exist. For example, in the disclosure, N-type transistors N 1 and N 2 are respectively inserted between the fuse sets (FS 1 and FS 2 ) and ground, so as to form a tail switch controlled by a signal SW. A circuit design technique to mitigate short-circuit current may add, between fuse set FS 1 and N-type transistor N 1 , an extra N-type transistor with drain connected to fuse set FS 1 , source connected to N-type transistor N 1 , and gate connected to the (precharge) control signal Pre. The same manner is equally applicable between fuse set FS 2 and N-type transistor N 2 .

In this embodiment, the gate of P-type transistor P 1 is coupled to (or receives) a first precharge control signal Pre, and the source of P-type transistor P 1 is coupled to a power supply V DD . The gate of N-type transistor N 1 is coupled to (or receives) a switch control signal SW, and the source of N-type transistor N 1 is coupled to the ground. Fuse set FS 1 , corresponding to redundant row R_row[0], is coupled between drains of P-type transistor P 1 and N-type transistor N 1 . First ends of the fuses in fuse set FS 1 are coupled together to the drain of P-type transistor P 1 , gates of the N-type transistors in fuse set FS 1 are coupled to decoded signals of an input row address [A 0 , A 0 B, A 1 , A 1 B], drains of the N-type transistors in fuse set FS 1 are respectively coupled to second ends of the fuses in fuse set FS 1 , and sources of the N-type transistors in fuse set FS 1 are coupled together to the drain of N-type transistor N 1 . Decoded row address signals A 0 and A 0 B are complementary, while decoded row address signals A 1 and A 1 B are complementary.

The gate of P-type transistor P 2 is coupled to (or receives) the precharge control signal Pre, and the source of P-type transistor P 2 is coupled to the power supply V DD . The gate of N-type transistor N 2 is coupled to (or receives) the switch control signal SW, and the source of N-type transistor N 2 is coupled to the ground. Fuse set FS 2 , corresponding to redundant column R_col[0], is coupled between drains of P-type transistor P 2 and N-type transistor N 2 . First ends of the fuses in fuse set FS 2 are coupled together to the drain of P-type transistor P 2 , gates of the N-type transistors in fuse set FS 2 are coupled to decoded signals of an input column address [A 2 , A 2 B, A 3 , A 3 B], drains of the N-type transistors in fuse set FS 2 are respectively coupled to second ends of the fuses in fuse set FS 2 , and sources of N-type transistors in fuse set FS 2 are coupled together to the drain of N-type transistor N 2 . Decoded column address signals A 2 and A 2 B are complementary, while decoded column address signals A 3 and A 3 B are complementary.

The address translation circuit external activating/enabling unit, formed by P-type transistors P 3 to P 5 , N-type transistors N 3 to N 9 , inverter INV, and fuse Fx, may be coupled to the control circuit in the controller chip Die_ 1 through TSVs V 0 and V 1 . In response to the setting of the control circuit in the controller chip Die_ 1 and the preset condition, it determines whether to activate/enable redundant row R_row[0] and redundant column R_col[0] or not, and provides a switch control signal SW accordingly. The gate of N-type transistor N 3 is coupled to the gate of P-type transistor P 1 , and the drain of N-type transistor N 3 is coupled to the drain of P-type transistor P 1 .

The gate of N-type transistor N 4 is coupled to sub-control unit CB 0 of the control circuit in the controller chip Die_ 1 through TSV V 0 , the drain of N-type transistor N 4 is coupled to the source of N-type transistor N 3 , and the source of N-type transistor N 4 is coupled to the ground. The gate of N-type transistor N 5 is coupled to the gate of P-type transistor P 2 , and the drain of N-type transistor N 5 is coupled to the drain of P-type transistor P 2 . The gate of N-type transistor N 6 is coupled to sub-control unit CB 1 of the control circuit in the controller chip Die_ 1 through TSV V 1 , the drain of N-type transistor N 6 is coupled to the source of N-type transistor N 5 , and the source of N-type transistor N 6 is coupled to the ground.

The source of P-type transistor P 3 is coupled to the power supply V DD , and the gate of P-type transistor P 3 is coupled to the gate of P-type transistor P 4 . The gate of P-type transistor P 4 is coupled to a precharge control signal Pre 2 , the source of P-type transistor P 4 is coupled to the power supply V DD , and the drain of P-type transistor P 4 is coupled to the gate of N-type transistor N 4 . The gate of P-type transistor P 5 is coupled to the precharge control signal Pre 2 , the source of P-type transistor P 5 is coupled to the power supply V DD , and the drain of P-type transistor P 5 is coupled to the gate of N-type transistor N 6 .

The gate of N-type transistor N 7 is coupled to the gate of P-type transistor P 4 , and the drain of N-type transistor N 7 is coupled to the drain of P-type transistor P 3 . The gate of N-type transistor N 8 is coupled to the switch control signal SW, and the drain of N-type transistor N 8 is coupled to the drain of P-type transistor P 4 . The gate of N-type transistor N 9 is coupled to the switch control signal SW, and the drain of N-type transistor N 9 is coupled to the drain of P-type transistor P 5 . The input of inverter NV is coupled to the drains of P-type transistor P 3 and N-type transistor N 7 together, and the output of inverter NV is the switch control signal SW. A first end of fuse Fx is coupled to the sources of N-type transistors N 7 to N 9 together, and a second end of fuse Fx is coupled to the ground. In this exemplary embodiment, the foregoing preset condition may indicate that, when fuse Fx is blown before the memory chip Die_ 0 is stacked, the corresponding redundant row R_row[0] and redundant column R_col[0] have not been used, and hence, both can be used to replace at least one newly damaged memory cell after chip stacking.

On the other hand, sub-control unit CB 0 of the control circuit in the controller chip Die_ 1 , corresponding to redundant row R_row[0], includes P-type transistor P 6 , N-type transistors N 10 and XN 0 , fuse F T1 , and transmission gate TG 1 . The gate of P-type transistor P 6 is coupled to a precharge control signal xPre, and the source of P-type transistor P 6 is coupled to the power supply V DD . The gate of N-type transistor N 10 is coupled to the gate of P-type transistor P 6 , and the drain of N-type transistor N 10 is coupled to the drain of P-type transistor P 6 . A first end of fuse F T1 is coupled to the source of N-type transistor N 10 , and a second end of fuse F in is coupled to the ground. The input terminal of transmission gate TG 1 is coupled to the drain of P-type transistor P 6 , with two complementary control signals being respectively en 0 and en 0 B. The gate of N-type transistor XN 0 is coupled to the output terminal of transmission gate TG 1 , the drain of N-type transistor XN 0 is coupled to the gate of N-type transistor N 4 through TSV V 0 , and the source of N-type transistor XN 0 is coupled to the ground.

Sub-control unit CB 1 of the control circuit in the controller chip Die_ 1 , corresponding to redundant column R_col[0], includes P-type transistor P 7 , N-type transistors N 11 and XN 1 , fuse F T2 , and transmission gate TG 2 . The gate of P-type transistor P 7 is coupled to the precharge control signal xPre, and the source of P-type transistor P 7 is coupled to the power supply V DD . The gate of N-type transistor N 11 is coupled to the gate of P-type transistor P 7 , and the drain of N-type transistor N 11 is coupled to the drain of P-type transistor P 7 . A first end of the fuse F T2 is coupled to the source of N-type transistor N 11 , and a second end of fuse F T2 is coupled to the ground. The input terminal of transmission gate TG 2 is coupled to the drain of P-type transistor P 7 , with two complementary control signals being respectively en 1 and en 1 B. The gate of N-type transistor XN 1 is coupled to the output terminal of transmission gate TG 2 , the drain of N-type transistor XN 1 is coupled to the gate of N-type transistor N 6 through TSV V 1 , and the source of N-type transistor XN 1 is coupled to the ground. In this exemplary embodiment, the foregoing setting of the control circuit is associated with whether fuses F T1 and F T2 are blown or not. It is noted that the fuses used in the controller chip Die_ 1 are not necessarily the same as those in the memory chip Die_ 0 .

More clearly, FIG. 2 is an operational view (timing diagram) of the address translation circuit on the memory chip Die_ 0 , according to an exemplary embodiment. Referring to FIG. 1 and FIG. 2 in combination, when the activating/enabling fuse Fx is blown, the switch control signal SW is low, and N-type transistors N 1 and N 2 are turned off, so that the discharge paths of fuse sets FS 1 and FS 2 are cut off. When the precharge control signal Pre transitions from low to high, TSVs V 0 and V 1 remain high, N-type transistors N 3 to N 6 are turned on, and nodes ND 0 and ND 1 are pulled down to ground, indicating that both redundant row R_row[0] and redundant column R_col[0] are deactivated.

When fuse F T1 is blown, in response to the control of the precharge control signal xPre and complementary enabling signals en 0 /en 0 B and en 1 /en 1 B, TSVs V 0 and V 1 stay respectively low and high. Therefore, N-type transistor N 4 is turned off and N-type transistor N 6 is turned on, node ND 0 remains at V DD , and node ND 1 is pulled down to ground. Apparently, once fuse F T1 is blown, the controller chip Die_ 1 is able to activate/enable redundant row R_row[0] to replace row row[0] which contains the damaged memory cell DMC in the memory chip Die_ 0 .

When fuse F T2 is blown, in response to the control of the precharge control signal xPre and complementary enabling signals en 0 /en 0 B and en 1 /en 1 B, TSVs V 0 and V 1 stay respectively high and low. Therefore, N-type transistor N 4 is turned on and N-type transistor N 6 is turned off, node ND 0 is pulled down to ground, and node ND 1 remains at V DD . Apparently, once fuse F T2 is blown, the controller chip Die_ 1 is able to activate/enable redundant column R_col[0] to replace column col[0] which contains the damaged memory cell DMC in the memory chip Die_ 0 .

It can be concluded that so long as the memory chip Die_ 0 has fuse Fx be blown before it is stacked with the controller chip Die_ 1 , redundant row R_row[0] or redundant column R_col[0] in the memory chip Die_ 0 may still be activated/enabled by blowing out fuse F T1 or F T2 in the controller chip Die_ 1 to repair the damaged memory cell DMC in the memory chip Die_ 0 , even after the memory chip Die_ 0 and the controller chip Die_ 1 are stacked.

Based on the content disclosed/taught in the above exemplary embodiment, those of ordinary skill in the art may obtain implementations of the address translation circuit for multiple redundant rows and columns built in the memory chip Die_ 0 and the corresponding control circuit in the controller chip Die_ 1 by analogy, and details thereof are not described herein again.

On the other hand, redundant row R_row[0] and redundant column R_col[0] in the memory chip Die_ 0 of the foregoing exemplary embodiment share the address translation circuit external activating/enabling unit; however, the disclosure is not limited thereto. More clearly, FIG. 3 is a schematic view of an address translation circuit in a memory chip Die_ 0 according to another exemplary embodiment of the disclosure. Referring to FIG. 1 and FIG. 3 in juxtaposition, an observable difference between the two address translation circuits lies in that redundant row R_row[0] and redundant column R_col[0] of the memory chip Die_ 0 in FIG. 3 do not share a common address translation circuit external activating/enabling unit as those in FIG. 1 . In other words, redundant row R_row[0] and redundant column R_col[0] each have their own address translation circuit external activating/enabling unit in the memory chip Die_ 0 of FIG. 3 .

Similarly, the address translation circuit external activating/enabling unit, corresponding to redundant row R_row[0] in the memory chip Die_ 0 , may be coupled to a control circuit in the controller chip Die_ 1 through TSV V 0 , and in response to the setting of the control circuit in the controller chip Die_ 1 (i.e., whether fuse F T1 is blown or not) and a preset condition (i.e., fuse F x0 is blown), used to activate/enable redundant row R_row[0] in the memory chip Die_ 0 and to provide a control signal SW 0 accordingly.

In addition, the address translation circuit external activating/enabling unit, corresponding to redundant column R_col[0] in the memory chip Die_ 0 , may be coupled to a control circuit in the controller chip Die_ 1 through TSV V 1 , and in response to setting of the control circuit in the controller chip Die_ 1 (i.e., whether fuse F T2 is blown or not) and a preset condition (i.e., fuse F x1 is blown), used to activate/enable redundant column R_col[0] in the memory chip Die_ 0 and to provide a control signal SW 1 accordingly.

Apparently, the address translation circuit, associated with redundant row R_row[0] and redundant column R_col[0] in the memory chip Die_ 0 shown in FIG. 3 , is applicable to a case when a part of damaged memory cells are already repaired before the memory chip Die_ 0 and the controller chip Die_ 1 are stacked. It is assumed that redundant column R_col[0] is already used to repair another damaged memory cell in the memory chip Die_ 0 discovered before stacking, so that although fuse F x1 in the address translation circuit external activating/enabling unit, corresponding to redundant column R_col[0], cannot be blown, fuse F x0 in the address translation circuit external activating/enabling unit, corresponding to redundant row R_row[0], still can be blown.

In this manner, redundant row R_row[0] in the memory chip Die_ 0 is activated/enabled by blowing fuse F T1 in the controller chip Die_ 1 to repair the damaged memory cell DMC in the memory chip Die_ 0 discovered after stacking, without affecting the already used redundant column R_col[0].

In addition, FIG. 4 is a schematic view of an address translation circuit of a memory chip Die_ 0 , according to another exemplary embodiment of the disclosure. Referring to FIG. 4 , two redundant rows R_row[0] and R_row[1] and two redundant columns R_col[0] and R_col[1] are built in the memory chip Die_ 0 shown in FIG. 4 , and therefore, the size of the address translation circuit shown in FIG. 4 doubles that of the address translation circuit shown in FIG. 1 . An address translation circuit external activating/enabling unit, corresponding to redundant rows R_row[0] and R_row[1], may be coupled to a control circuit in the controller chip Die_ 1 through TSVs V 0 and V 2 , and in response to the setting of the control circuit in the controller chip Die_ 1 and a preset condition (i.e., fuse F x0 is blown), determines to activate/enable redundant row R_row[0] and/or R_row[1], and provides a switch control signal SW 0 accordingly.

Similarly, an address translation circuit external activating/enabling unit, corresponding to redundant columns R_col[0] and R_col[1], may be coupled to the control circuit in the controller chip Die_ 1 through TSVs V 1 and V 3 , and in response to the setting of the control circuit in the controller chip Die_ 1 and a preset condition (i.e., fuse F x1 is blown), determines to activate/enable redundant column R_col[0] and/or R_col[1], and provides a switch control signal SW 1 accordingly.

Further, FIG. 5 is a schematic view of an address translation circuit of a memory chip Die_ 0 , according to another exemplary embodiment. Referring to FIG. 5 , two redundant rows R_row[0] and R_row[1] and two redundant columns R_col[0] and R_col[1] are built in the memory chip Die_ 0 shown in FIG. 5 . Compared with that shown in FIG. 4 , an address translation circuit, corresponding to redundant rows R_row[0] and R_row[1] and redundant columns R_col[0] and R_col[1], share a common address translation circuit external activating/enabling unit with fuse F x . As a result, the four redundant components can only be used as a whole before stacking or after stacking, determined by a condition whether fuse F x is blown or not.

Based on the content disclosed/taught in the foregoing exemplary embodiments, FIG. 6 is a flow chart of a method capable of repairing a memory chip after the chip is stacked with a controller chip in a 3-D IC, according to an exemplary embodiment. Referring to FIG. 6 , the method for memory repair after chip stacking in a 3-D IC according to this exemplary embodiment includes the following steps.

A control circuit is designed in a controller chip, and an address translation circuit with an external activation/enablement function is designed in a memory chip (Step S 601 ).

The external activation/enablement function is activated for at least one unused redundant row and/or one redundant column before the memory chip is stacked (Step S 602 ).

After the controller chip and the memory chip are stacked, the controller chip is able to, in response to the setting of the control circuit and a preset condition associated with the address translation circuit capable of external activation/enablement, control the address translation circuit in the memory chip through at least one TSV, so as to activate/enable at least one redundant row and/or one redundant column in the memory chip to repair at least one damaged memory cell in the memory chip (Step S 603 ).

It should be noted that, in the foregoing exemplary embodiments, although the controller chip is used to control the address translation circuit in the memory chip through the TSV, the disclosure is not limited thereto. More clearly, in other exemplary embodiments, the controller chip may also control the address translation circuit in the memory chip through three-dimensional interconnects, such as a micro bump and a redistribution layer (RDL), whose usage is entirely based on actual design requirements.

In conclusion, the disclosure provides a technique of memory repair after chip stacking, which uses another stacked chip to enable/activate spares in a memory chip, so as to repair a damaged memory cell in the memory chip. In this manner, a problem of inconvenient access to an internal fuse circuit after chip stacking is solved. At the same time, flexible usage of the spare memory is provided, and the yield of the 3-D IC is improved.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.