Analyzing EM performance during IC manufacturing

The present invention relates to a measurement structure in a standard cell for controlling and monitoring process parameters for electro-migration (EM) performance during manufacturing of an integrated circuit (IC).

Electro-migration (EM) refers to mass transport due to the momentum exchange between conducting electrons and diffusing metal atoms in metallic interconnects. As integrated circuits become progressively more complex, the individual components must become increasingly more reliable if the reliability of the whole device is to be acceptable. However, due to continuing miniaturization of very large scale integrated (VLSI) circuits, thin film metallic conductors or interconnects are subject to increasingly high current densities. Under these conditions, EM can lead to an electrical failure of a product within a relatively short time, therefore reducing the product lifetime to an unacceptable level. More and more integrated circuit systems, especially for those circuits used in medical, military, and space applications, need an assurance of system reliability for their critical missions. Therefore, it is of great importance and critical need to evaluate EM during the manufacturing process to assure overall chip reliability.

EM reliability tests during integrated circuit (IC) manufacturing attempt to project future EM failures, i.e., the tests calculate “EM projections”. Unfortunately, reliability of the tests is limited due to the approach used in conventional testing. For example, such tests are performed at extremely high temperatures (e.g., 300-400 degrees Celsius) in order to accelerate failure times of a very limited sample size (e.g., less than 100 samples per condition) at module level. Drawbacks of this approach include:

1) High temperatures could cause some competing degradation effects such as stress migration and low-k film material degradation;

2) Module (i.e., package) level test is costly as it requires, e.g., extra shipping, wafer dicing, cleaning, chiplet picking, wire bonding, baking, etc.; module level testing is also time consuming and prone to other damages, e.g., ESD, cracking, edge seal damages, etc.;

3) Modeling chip level EM from line level is not easy and needs a careful mathematical transformation (chip level EM is not Lognormal distributed); and

4) Confidence bounds of projection based on limited sample size are typically poor and multi-modal sub-group distributions cannot be easily separated from a limited sample size.

In a first aspect, the present invention provides a testing structure for monitoring electro-migration (EM) performance, comprising: an EM resistor having four point resistive measurement, wherein a first terminal and a second terminal provide current input and a third terminal and a fourth terminal provides a voltage measurement; and a first transistor coupled to the first terminal of the EM resistor as a secondary side of a current mirror for supplying a test current; wherein the voltage measurement is obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to measure a voltage across the third and fourth terminals.

In a second aspect, the invention provides a system for monitoring electro-migration (EM) performance, comprising: an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first terminal and a second terminal provides current input and a third terminal and a fourth terminal provides a voltage measurement, the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to measure a voltage across the third and fourth terminals; and a first transistor coupled to the first terminal of the EM resistor as a secondary side of a current mirror for supplying a test current; a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure.

In a third aspect, the invention provides a method for determining electro-migration (EM) reliability, comprising: providing a plurality of testing structures in an integrated circuit (IC), wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first terminal and a second terminal provides current input and a third terminal and a fourth terminal provides a voltage measurement, the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to measure a voltage across the third and fourth terminals; and a first transistor coupled to the first terminal of the EM resistor as a secondary side of a current mirror for supplying a test current; selectively activating the selection switch for each of the plurality of testing structures; and outputting the voltage measurement for each selected testing structure.

These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings.

FIG. 1 depicts a layout view of four point resistors in accordance with an embodiment of the present invention.

FIG. 2 depicts an EM testing structure in accordance with an embodiment of the present invention.

FIG. 3 depicts a testing array in accordance with an embodiment of the present invention.

FIG. 4 depicts an externally controlled testing system in accordance with an embodiment of the present invention.

FIG. 5 depicts an alternative EM testing structure in accordance with an embodiment of the present invention.

FIG. 6 depicts an alternative testing array in accordance with an embodiment of the present invention.

FIG. 7 depicts a flow diagram showing a methodology in accordance with an embodiment of the present invention.

The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like reference numbering represents like elements.

The following embodiments include testing structures and methods for providing a reliable and highly accurate EM projection for an integrated circuit. The described solution utilizes a layout 10 of four point resistors 12 (also commonly referred to as “4-terminal resistors”), as shown in FIG. 1 . Each resistor 12 includes an associated independent circuit to form an EM testing structure (cell) 14 shown in FIG. 2 for detecting resistance failures. In an illustrative embodiment, one million or so such structures 14 may be utilized and packaged in a relatively small area, e.g., 1 mm 2 . Based on the occurrence of one or more failures during testing, an EM projection can be determined. For instance, a failure at time T F during testing can be transformed into a projected EM failure at time P F .

In the illustrative testing structure 14 shown in FIG. 2 , resistor Ri includes terminals T 1 and T 2 that are used for current input and terminals T 3 and T 4 that are used for voltage measurement. A measurement switch comprising P 2 i and P 3 i is coupled to terminals T 3 and T 4 . P 1 i is a PFET (P-type field effect transistor) of the secondary side of a current mirror which provides the test current to resistor Ri. P 2 i and P 3 i are the switching PFETs and drains O 1 i and O 2 i of P 2 i and P 3 i , respectively, are connected to two common voltage terminals, which can be used to measure the voltage cross the terminal T 3 and terminal T 4 of Ri. The gates of P 2 i and P 3 i are connected to the selection terminal, Si, and the sources are connected to terminals T 3 and T 4 , respectively.

When the voltage on Si is at logic low, both P 2 i and P 3 i are turned on so the voltage across terminals T 3 and T 4 of Ri are connected to the output voltage terminals 16 of the system. Such voltages can be measured by either off chip or on-chip measurement units (not shown). Note that while testing structure 14 is shown implemented with PFETs, it is understood that the circuit could be implemented with any type or combination of transistors capable of performing the actions described herein, including PFETs, NFETs or bipolar transistors.

FIG. 3 depicts an illustrative testing array 18 that comprises a plurality of testing structures 100 (i.e., 100 _ 1 , 100 _ 2 . . . 100 _i). The terminal Vdd of each testing structure 100 is connected to pad 1 . P 0 is a PFET which forms the primary side of the current mirror for each testing structure 100 ; the secondary side being provided, e.g., by P 1 i shown in FIG. 1 . The gate and drain of P 0 are connected to pad 2 and terminals C 1 , C 2 , . . . Ci of each testing structure 100 . Pad 2 is further connected to a current source so that the current mirror mirrors the current of the current source to each testing structure 100 with a mirror ratio.

The terminal of 0V of each testing structure 100 is connected to pad 3 . The terminal O 1 (i.e., O 11 , O 12 . . . O 1 i) of each testing structure 100 is connected to pad 4 , Vout 1 . The terminal of O 2 (i.e., O 21 , O 22 . . . O 2 i) of each testing structure 100 is connected to pad 5 , Vout 2 . Each terminal S (S 1 , S 2 . . . Si) is coupled to a decoder 200 . The rest of the pads, i.e., pad 6 to pad 25 are utilized as the inputs of decoder, i.e., b 0 to b 19 .

When a predetermined input code is applied to pads b 0 to b 19 of the decoder, one of the decoder outputs S is set at logic low. The output voltage of the corresponding testing structure 100 on the resistor under test is connected to pad 4 of Vout 1 and pad 5 of Vout 2 . Because this embodiment utilizes a 20 bit input into the decoder 200 , up to 1,048,576 testing structures 100 may be implemented to test the corresponding IC.

FIG. 4 depicts an illustrative on-chip array-based scanning system 20 for controlling the testing array 18 of FIG. 3 . In this embodiment, testing array 18 is provided in which V 1 is a voltage supply and I 1 is a current source that provides the current to the current mirror. A microcontroller (MC) 22 is provided that includes two analog to digital converters (adc 1 and adc 2 ), and 20 input/output ports (I/O 0 , I/O 1 , . . . I/O 19 ). A communication port, e.g., a USB, connects the microcontroller 22 to a computer (CP) 24 , such as a personal computer.

FIG. 5 depicts an alternative embodiment of a testing structure 26 capable of testing for both resistance and leakage failures. In addition to PFETs P 1 i , P 2 i and P 3 i shown in FIG. 2 , testing structure 26 includes two additional PFETs (P 4 i , P 5 i ) and an inverter INVi, which causes P 1 i to not always be on. When ENi is at logic high, P 5 i is turned on, P 4 i is turned off, P 1 i is connected to the primary side of the current mirror. Also, since P 1 i provides the current to the resistor Ri under test when Si is at logic low. P 2 i and P 3 i are turned on as well for the normal stress test. A stress test generally refers to operating a device under higher than usual voltage, current and/or temperature conditions to accelerate failure.

When ENi is at logic low, P 5 i is turned off, P 4 i is turned on, and P 1 i is disconnected from the primary side of the current mirror. However Si is at logic low, so the leakage between two neighbor resistors (not shown) can be recorded. Note that testing structure 26 could be readily implemented using any type or combination of transistors capable of performing the actions described herein, including PFETs, NFETs or bipolar transistors.

In the associated testing array 28 shown in FIG. 6 , the decoder 400 has control signals for EN (i.e., EN 1 , EN 2 . . . ENi) which can be turned to at logic high or logic low independently. When the leakage between neighboring resistors Rx and R(x+1) are tested, En(x−1) and Enx are at logic low, and En(x+1) is at logic high. Pad 25 (b 19 ) of decoder 400 can be use for the mode selection. When b 19 is at logic low, “resistor” mode is selected, and all ENs are at logic high. When b 19 is at logic high, “leakage mode” is selected.

FIG. 7 depicts an illustrative methodology for performing EM testing. At S 1 , obtain baseline voltage measurements for each testing structure. At S 2 , convert the baseline measurements from analog to digital and store the digital data. At S 3 , obtain time dependent voltage measurements for each testing structure under high temperature and constant current stress. At S 4 , covert the time-dependent measurements from analog to digital and store the data. Next, compare the time-dependent measurements for each testing structure with associated baseline measurements at S 5 , and if the values are different by more than a predetermined threshold, mark the testing structure as failed and do no further testing on the failed structure at S 6 . Continue testing as dictated by an implemented reliability plan.

Note that at wafer level testing with a multi-probe setup, only the first or second failure from one chip is needed for an accurate chip level EM projection to be obtained quickly. With two times Juse (Juse=two times the design manual's defined maximum allowable DC design current) and a 140° C. burn-in (BI) temperature, a two to three month stress test will translate into eight to ten year of projected lifetime.

The described embodiments can ensure whole chip reliability by providing millions of EM segments that can be operated under higher than normal current to account for all statistical variations. In addition, the detection circuit is more reliable than the EM resistors and the rest of chip to ensure that the detection circuit should not fail earlier than all the EM testing resistors. Variations induced by other factors such as temperature should not affect the monitor detection accuracy.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

In addition, as will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “computer” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.