Inventor
Fen Chen
Inventor
Williston, VT, US
Overview
Patents· 72 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1022%
H01LSemiconductor devices14%
G01RMeasuring electric variables11%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H10DInorganic electric semiconductor devices7%
H10NElectric solid-state devices not otherwise provided for7%
H03KPulse technique5%
G01NInvestigating or analysing materials by determining their chemical or physical properties4%
G11CStatic stores4%
H10BElectronic memory devices4%
PatentTitleYear
11,011,231Data write-in method and non-volatile memory202110,794,948Electromigration monitor202010,677,833Electromigration monitor202010,545,110Moisture detection and ingression monitoring systems and methods of manufacture202010,545,111Moisture detection and ingression monitoring systems and methods of manufacture202010,388,567Thru-silicon-via structures201910,324,056Moisture detection and ingression monitoring systems and methods of manufacture201910,309,919Moisture detection and ingression monitoring systems and methods of manufacture201910,141,274Semiconductor chip with anti-reverse engineering function201810,126,260Moisture detection and ingression monitoring systems and methods of manufacture20189,891,261'Electromigration monitor'20189,893,023'Semiconductor chip with anti-reverse engineering function'20189,851,397Electromigration testing of interconnect analogues having bottom-connected sensory pins20179,851,398Via leakage and breakdown testing20179,812,359'Thru-silicon-via structures'20179,780,031'Wiring structures'20179,711,464'Semiconductor chip with anti-reverse engineering function'20179,613,853'Copper wire and dielectric with air gaps'20179,453,873'Non-planar field effect transistor test structure and lateral dielectric breakdown testing method'20169,404,953'Structures and methods for monitoring dielectric reliability with through-silicon vias'20169,318,413'Integrated circuit structure with metal cap and methods of fabrication'20169,318,414'Integrated circuit structure with through-semiconductor via'20169,287,345'Semiconductor structure with thin film resistor and terminal bond pad'20169,230,914'Copper wire and dielectric with air gaps'20169,159,671'Copper wire and dielectric with air gaps'20159,093,503'Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure'20159,059,052'Alternating open-ended via chains for testing via formation and dielectric integrity'20159,029,172'On-chip poly-to-contact process monitoring and reliability evaluation system and method of use'20159,013,202'Testing structure and method of using the testing structure'20158,945,955'Method of changing reflectance or resistance of a region in an optoelectronic memory device'20158,917,104'Analyzing EM performance during IC manufacturing'20148,890,556'Real-time on-chip EM performance monitoring'20148,847,401'Semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure'20148,779,491'3D via capacitor with a floating conductive plate for improved reliability'20148,754,655'Test structure, method and circuit for simultaneously testing time dependent dielectric breakdown and electromigration or stress migration'20148,749,293'Stackable programmable passive device and a testing method'20148,609,504'3D via capacitor with a floating conductive plate for improved reliability'20138,569,888'Wiring structure and method of forming the structure'20138,563,336'Method for forming thin film resistor and terminal bond pad simultaneously'20138,525,153'Structure including voltage controlled negative resistance'20138,497,203'Semiconductor structures and methods of manufacture'20138,405,135'3D via capacitor with a floating conductive plate for improved reliability'20138,362,794'Method and system for assessing reliability of integrated circuit'20138,294,505'Stackable programmable passive device and a testing method'20128,288,747'Optoelectronic memory devices'20128,237,463'Method for managing circuit reliability'20128,178,434'On-chip embedded thermal antenna for chip cooling'20128,053,814'On-chip embedded thermal antenna for chip cooling'20118,018,017'Thermo-mechanical cleavable structure'20117,998,828'Method of forming metal ion transistor'20117,880,158'Phase-change TaN resistor based triple-state/multi-state read only memory'20117,859,025'Metal ion transistor'20107,843,062'Thermally programmable anti-reverse engineering interconnects wherein interconnects only conduct when heated above room temperature'20107,795,679'Device structures with a self-aligned damage layer and methods for forming such device structures'20107,768,815'Optoelectronic memory devices'20107,715,248'Phase-change TaN resistor based triple-state/multi-state read only memory'20107,709,401'Method of making thermally programmable anti-reverse engineering interconnects wherein interconnects only conduct when heated above room temperature'20107,601,602'Trench type buried on-chip precision programmable resistor'20097,571,637'Design structure for an on-chip real-time moisture sensor for and method of detecting moisture ingress in an integrated circuit chip'20097,500,208'Non-destructive evaluation of microstructure and interface roughness of electrically conducting lines in semiconductor integrated circuits in deep sub-micron regime'20097,381,981'Phase-change TaN resistor based triple-state/multi-state read only memory'20087,378,866'Method and apparatus for impedance matching in transmission circuits using tantalum nitride resistor devices'20087,345,503'Method and apparatus for impedance matching in transmission circuits using tantalum nitride resistor devices'20087,231,617'Determination of grain sizes of electrically conductive lines in semiconductor integrated circuits'20077,084,483'Trench type buried on-chip precision programmable resistor'20066,800,938'Semiconductor device having amorphous barrier layer for copper metallurgy'20046,794,706'Applications of space-charge-limited conduction induced current increase in nitride-oxide dielectric capacitors: voltage regulator for power supply system and others'20046,790,744'Monolithically integrated solid-state sige thermoelectric energy converter for high speed and low power circuits'20046,788,093'Methodology and apparatus using real-time optical signal for wafer-level device dielectrical reliability studies'20046,743,655'Negative differential resistance reoxidized nitride silicon-based photodiode and method'20046,639,242'Monolithically integrated solid-state SiGe thermoelectric energy converter for high speed and low power circuits'20036,445,021'Negative differential resistance reoxidized nitride silicon-based photodiode and method'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2020Patents assigned to IBM (66)· patent assignee history
2002–2020Based in Williston, VT, US· patent location history
2003Based in Willistion, VT, US· patent location history
2012–2015Patents assigned to CHEN FEN (16)· patent assignee history
2012–2014Patents assigned to FENG KAI D (4)· patent assignee history
2013Based in Essex Junction, VT, US· patent location history
2014–2015Patents assigned to DUFRESNE ROGER A (4)· patent assignee history
2016–2019Patents assigned to GLOBALFOUNDRIES INC (8)· patent assignee history
2019Based in Morgan Hill, CA, US· patent location history
2021Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 66 | 2002–2020 |
| CHEN FENself | 16 | 2012–2015 |
| GLOBALFOUNDRIES INC | 8 | 2016–2019 |
| DUFRESNE ROGER A | 4 | 2014–2015 |
| FENG KAI D | 4 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Williston, VT, US | 68 | 2002–2020 |
| San Jose, California, US | 1 | 2021 |
| Morgan Hill, California, US | 1 | 2019 |
| Essex Junction, VT, US | 1 | 2013 |
| Willistion, VT, US | 1 | 2003 |