Liquid crystal driving circuit having a common-signal output circuit and a segment-signal output circuit and method

This application claims the benefit of priority to Japanese Patent Application No. 2010-170777, filed Jul. 29, 2010, of which full contents are incorporated herein by reference.

1. Field of the Invention

The present invention relates to a liquid crystal driving circuit.

2. Description of the Related Art

In a segment-display type or a simple matrix driving type liquid crystal panel, a common signal and a segment signal are supplied to a common electrode and a segment electrode, respectively, and turning on/off is controlled in accordance with a voltage (potential difference) between both the electrodes, in general.

In these liquid crystal panels, performing time-division driving enables display of more segments (pixels) than the number of output terminals of an IC for driving a liquid crystal. For example, in a liquid crystal panel with the number m of common electrodes and the number n of segment electrodes, performing 1/m duty driving enables display of m×n segments at the maximum. Further, in the time-division driving, 1/S bias driving is performed so that each signal can obtain (S+1) potentials. For example, in FIG. 4 of Japanese Patent Laid-Open Publication No. H10-10491, disclosed is an LCD driving power circuit used for 1/3 bias driving.

Here, a configuration of a common liquid crystal driving circuit that performs time-division driving and an example of an operation thereof are illustrated in FIGS. 7 and 8 .

As illustrated in FIG. 7 , intermediate potentials V 1 and V 2 obtained by dividing a power supply voltage V 0 (=VDD−VSS) by a resistor R 1 to R 3 are supplied, in addition to power supply potentials VDD and VSS on a high-potential side and a low-potential side, to a common-signal output circuit 5 and a segment-signal output circuit 7 . Therefore, in this liquid crystal driving circuit, 1/3 bias driving (S=3) is performed.

Further, FIG. 8 illustrates an operation of the liquid crystal driving circuit that performs 1/4 duty driving (m=4). As illustrated in FIG. 8 , a common signal COMi (1≦i≦m) is at a power supply potential for a 1/4 period and of an intermediate potential for a 3/4 period, in one period T 0 , and the waveform is shifted by 1/4 period each. On the other hand, a segment signal SEGj (1≦j≦n) is at a potential according to turning on or off of four segments corresponding to segment electrodes to which the signal is supplied.

As such, use of the 1/m duty and 1/S bias driving method enable display of more segments than the number of output terminals of the IC for driving a liquid crystal.

The common electrode to which the common signal COMi is supplied and the segment electrode to which the segment signal SEGj is supplied are capacitively-coupled through liquid crystal, and thus, beard-like spike noise might be generated in one of the signals, which is caused by a change in potential of the other of the signals. Thus, in the liquid crystal driving circuit illustrated in FIG. 7 , similarly to FIG. 4 in Japanese Patent Laid-Open Publication No. H10-10491, capacitors C 1 and C 2 are used as stabilizing capacities so as to absorb the spike noise and to stabilize the intermediate potentials V 1 and V 2 . As illustrated in FIG. 9 , such a liquid crystal driving circuit is known that stabilizes the intermediate potentials V 1 and V 2 using voltage follower circuits configured by operational amplifiers OP 1 and OP 2 , respectively.

However, since the capacitance of the capacitor used as the stabilizing capacity is required to be sufficiently large in accordance with the liquid crystal panel, the capacitor usually results in an external component, which increases a mounting area of a circuit board. On the other hand, since output impedance of the operational amplifier which makes up the voltage follower circuit is required to be sufficiently small, current consumption is increased. Further, if the output impedance is not sufficiently small, as illustrated in FIG. 10 , the spike noise Sp is not sufficiently absorbed, which might cause such defective display that an image remains in the liquid crystal panel.

Thus, in order to ensure favorable display quality, the current consumption of the liquid crystal driving circuit and the mounting area of the circuit board are in a trade-off relationship.

A liquid crystal driving circuit according to an aspect of the present invention, includes: a plurality of resistors connected in series between a first potential and a second potential lower than the first potential; one or more voltage follower circuits configured to impedance-convert one or more intermediate potentials between the first potential and the second potential, to be outputted, respectively, the one or more intermediate potentials generated at one or more connection points between the plurality of resistors, respectively; a common-signal output circuit configured to supply common signals to common electrodes of a liquid crystal panel, respectively, the common signals being at the first potential, the second potential, and the one or more intermediate potentials in a predetermined order; and a segment-signal output circuit configured to supply segment signals to segment electrodes of the liquid crystal panel, respectively, each of the segment signals being at the first potential, the second potential, and the one or more intermediate potentials in accordance with the common signals, the segment-signal output circuit configured to change the potentials of the segment signals in a ramp form, at least in a case where the potentials of the segment signals are changed with a maximum possible potential difference.

Other features of the present invention will become apparent from descriptions of this specification and of the accompanying drawings.

For more thorough understanding of the present invention and advantages thereof, the following description should be read in conjunction with the accompanying drawings, in which:

FIG. 1 is a circuit block diagram illustrating an example of specific configurations of a common-signal output circuit 1 and a segment-signal output circuit 3 ;

FIG. 2 is a circuit block diagram illustrating an outline of a configuration of an entire liquid crystal driving circuit according to an embodiment of the present invention;

FIG. 3 is a diagram for explaining an operation of a liquid crystal driving circuit according to an embodiment of the present invention:

FIG. 4 is a circuit block diagram illustrating another configuration example of a current supply circuit;

FIG. 5 is a diagram illustrating another example of a driving method of a liquid crystal driving circuit;

FIG. 6 is a diagram illustrating still another example of a driving method of a liquid crystal driving circuit;

FIG. 7 is a circuit block diagram illustrating an example of a configuration of a general liquid crystal driving circuit provided with an external capacitor;

FIG. 8 is a diagram for explaining an operation of a liquid crystal driving circuit illustrated in FIG. 7 ;

FIG. 9 is a circuit block diagram illustrating an example of a configuration of a general liquid crystal driving circuit provided with a voltage follower circuit; and

FIG. 10 is a diagram illustrating an operation of a liquid crystal driving circuit illustrated in FIG. 9 .

At least the following details will become apparent from descriptions of this specification and of the accompanying drawings.

—Outline of Configuration of Entire Liquid Crystal Driving Circuit—

An outline of a configuration of an entire liquid crystal driving circuit according to an embodiment of the present invention will hereinafter be described referring to FIG. 2 .

The liquid crystal driving circuit illustrated in FIG. 2 is a circuit configured to drive a liquid crystal panel 9 and includes resistors R 1 to R 3 , operational amplifiers OP 1 and OP 2 , a common-signal output circuit 1 , and a segment-signal output circuit 3 .

The resistors R 1 to R 3 are connected in series in this order. One end of the resistor R 1 is connected to a power supply potential VDD (first potential) on a high potential side, while one end of the resistor R 3 is connected to a power supply potential VSS (second potential) on a low potential side.

The operational amplifier OP 1 has a non-inverting input connected to a connection point between the resistors R 1 and R 2 , and an inverting input and an output, which are connected to each other, thereby making up a voltage follower circuit. The operational amplifier OP 2 has a non-inverting input connected to a connection point between the resistors R 2 and R 3 , and an inverting input and an output, which are connected to each other, thereby making up a voltage follower circuit.

The power supply potentials VDD and VSS and the intermediate potentials V 1 and V 2 respectively outputted from the operational amplifiers OP 1 and OP 2 are supplied to both of the common-signal output circuit 1 and the segment-signal output circuit 3 . Common signals COM 1 to COMm outputted from the common-signal output circuit 1 are supplied to m pieces of common electrodes (not shown) of the liquid crystal panel 9 , respectively. On the other hand, segment signals SEG 1 to SEGn outputted from the segment-signal output circuit 3 are supplied to n pieces of segment electrodes (not shown) of the liquid crystal panel 9 , respectively.

—Configurations of Common-Signal Output Circuit and Segment-Signal Output Circuit—

More specific configurations of the common-signal output circuit 1 and the segment-signal output circuit 3 will hereinafter be described referring to FIG. 1 . FIG. 1 illustrates only one circuit configured to output an arbitrary common signal COMi (1≦i≦m) among the common-signal output circuits 1 , and only one circuit configured to output an arbitrary segment signal SEGj (1≦j≦n) among the segment-signal output circuits 3 .

The common-signal output circuit 1 includes a ramp waveform generation circuit 10 and an output selection circuit 20 .

The ramp waveform generation circuit 10 includes a resistor R 11 , a current source 1512 , a PMOS (P-channel Metal-Oxide Semiconductor) transistors T 11 and T 13 , and an NMOS (N-channel MOS) transistors T 12 and T 14 . The current source IS 12 is configured with an NMOS transistor whose gate is applied with a predetermined bias voltage, for example.

The resistor R 11 connected to the power supply potential VDD, the transistors T 11 and T 12 , and the current source IS 12 connected to the power supply potential VSS are connected in series in this order, and correspond to a first current supply circuit. Clock signals S 11 and S 12 are inputted to the gates of the transistors T 11 and T 12 , respectively.

A source of the transistor T 13 is connected to the power supply potential VDD, a drain thereof is connected to a connection point between the transistors T 11 and T 12 , and a clock signal S 13 is inputted to a gate thereof. A source of the transistor T 14 is connected to the power supply potential VSS, a drain thereof is connected to the connection point between the transistors T 11 and T 12 , and a clock signal S 14 is inputted to a gate thereof.

The output selection circuit 20 includes multiplexers (selection circuits) M 21 and M 22 . The 2-input to 1-output multiplexers M 21 and M 22 are each configured with two analog switches, for example.

A clock signal S 22 is inputted to a selection control input of the multiplexer M 22 . Data inputs thereof corresponding to a low level and a high level of the clock signal S 22 are connected to the intermediate potentials V 1 and V 2 , respectively.

A clock signal S 21 is inputted to a selection control input of the multiplexer M 21 . A data input thereof corresponding to a low level of the clock signal S 21 is connected to an output of the multiplexer M 22 , and a data input thereof corresponding to a high level is connected to a connection point between the transistors T 11 and T 12 . Then, the common signal COMi is outputted from the multiplexer M 21 .

The segment-signal output circuit 3 includes a ramp waveform generation circuit 30 and an output selection circuit 40 .

The ramp waveform generation circuit 30 includes current sources IS 31 and IS 32 , PMOS transistors T 31 and T 33 , and NMOS transistors T 32 and T 34 . The current sources IS 31 and IS 32 are configured with a PMOS transistor and an NMOS transistor whose gates are applied with predetermined bias voltages, respectively, for example.

The current source IS 31 connected to the power supply potential VDD, the transistors T 31 and T 32 , and the current source IS 32 connected to the power supply potential VSS are connected in series in this order, and correspond to a second current supply circuit. Clock signals S 31 and S 32 are inputted to gates of the transistors T 31 and T 32 , respectively.

A source of the transistor T 33 is connected to the power supply potential VDD, a drain thereof is connected to a connection point between the transistors T 31 and T 32 , and a clock signal S 33 is inputted to a gate. A source of the transistor T 34 is connected to the power supply potential VSS, a drain thereof is connected to the connection point between the transistors T 31 and T 32 , and a clock signal S 34 is inputted to a gate thereof.

The output selection circuit 40 includes multiplexers M 41 and M 42 . The 2-input to 1-output multiplexers M 41 and M 42 are each configured with two analog switches, for example.

The clock signal S 22 is inputted to a selection control input of the multiplexer M 42 , similarly to the multiplexer M 22 . Data inputs thereof corresponding to a low level and a high level of the clock signal S 22 are connected to the intermediate potentials V 2 and V 1 , respectively, contrary to the case of the multiplexer M 22 .

A clock signal S 41 is inputted to a selection control input of the multiplexer M 41 . A data input thereof corresponding to a low level of the clock signal S 41 is connected to an output of the multiplexer M 42 , and a data input thereof corresponding to a high level is connected to the connection point between the transistors T 31 and T 32 . Then, the segment signal SEGj is outputted from the multiplexer M 41 .

—Operation of Liquid Crystal Driving Circuit—

An operation of the liquid crystal driving circuit according to an embodiment of the present invention will hereinafter be described referring to FIGS. 1 to 3 as appropriate.

The resistors R 1 to R 3 divide a supply voltage V 0 (=VDD−VSS). The voltage follower circuit, configured with the operational amplifier OP 1 , impedance-converts the intermediate potential V 1 generated at the connection point between the resistors R 1 and R 2 , to be outputted. On the other hand, the voltage follower circuit, configured with the operational amplifier OP 2 , impedance-converts the intermediate potential V 2 generated at the connection point between the resistors R 2 and R 3 , to be outputted.

The resistors R 1 to R 3 , whose resistance values are equal, are used. Therefore, VDD−V 1 =V 1 −V 2 =V 2 −VSS=1/3V 0 is given, and the liquid crystal driving circuit performs 1/3 bias driving.

Here, referring to FIG. 3 , a description will be given of an example of a specific operation of the common-signal output circuit 1 and the segment-signal output circuit 3 in the case where the liquid crystal driving circuit performs 1/4 duty driving (m=4).

FIG. 3 illustrates an operation in the case where the common-signal output circuit 1 illustrated in FIG. 1 outputs the common signal COM 1 , and in the case of outputting the common signals COM 2 to COM 4 , the waveforms thereof result in waveforms obtained by shifting the waveform of the common signal COM 1 by 1/4 period each. Illustrated is a waveform of the segment signal SEGj in the case where two segments corresponding to the common signals COM 2 and COM 3 are turned on and two segments corresponding to the common signals COM 1 and COM 4 are turned off, among the four segments corresponding to the segment signal SEGj.

First, an operation of the common-signal output circuit 1 will be described.

The clock signal S 21 is a clock signal with 1/4 duty, and a high-level period of the signal indicates a time period during which n pieces of the segments corresponding to the common signal COM 1 are selected. Therefore, in the case where the common-signal output circuit 1 outputs the common signals COM 2 to COM 4 , the waveform of the clock signal S 21 is shifted by 1/4 period each. Hereinafter, the time period during which n pieces of the segments corresponding to the common signal COMi are selected and the time period during which they are not selected will be referred to as a selection period and a non-selection period of the common signal COMi, respectively.

The clock signal S 22 is a clock signal with 1/2 duty whose 1 period (cycle) is equal to the selection period of each of the common signals. The clock signals S 11 and S 12 are both inverted signals of the clock signal S 22 . Moreover, the clock signal S 13 is a clock signal whose falling edge alone is delayed with respect to that of the clock signal S 11 by a predetermined delay time period, and the clock signal S 14 is a clock signal whose rising edge alone is delayed with respect to that of the clock signal S 12 by a predetermined delay time period.

If the clock signal S 21 goes high (high level) and enters the selection period of the common signal COM 1 , the potential of the common signal COM 1 outputted from the multiplexer M 21 becomes equal to a potential at the connection point between the transistors T 11 and T 12 . At the same time, the clock signals S 11 , S 12 , and S 14 go low (low level) and the transistor T 11 is turned on and the transistors T 12 and T 14 are turned off, and thus, the potential of the common signal COM 1 becomes equal to the power supply potential VDD.

The clock signal S 13 goes low with a delay of a predetermined delay time period with respect to the clock signal S 11 and the transistor T 13 is turned on, resulting in sufficiently small output impedance.

If the clock signals S 11 to S 13 go high concurrently in the selection period of the common signal COM 1 , the transistors T 11 and T 13 are turned off, and the transistor T 12 is turned on. Therefore, a sink current corresponding to a first constant-current signal is supplied to the common electrode of the liquid crystal panel 9 from the current source IS 12 , as the common signal COM 1 . The potential of the common signal COM 1 falls in a ramp form due to the sink current to become equal to the power supply potential VSS, resulting in a ramp waveform Ra 1 falling from the power supply potential VDD to the power supply potential VSS.

The clock signal S 14 goes high with a delay of a predetermined delay time period with respect to the clock signal S 12 and the transistor T 14 is turned on, resulting in sufficiently small output impedance. The delay period is set such that the clock signal S 14 goes high at least after the potential of the common signal COM 1 reaches the power supply potential VSS.

If the clock signal S 21 goes low and enters the non-selection period of the common signal COM 1 , the potential of the common signal COM 1 becomes equal to an output potential of the multiplexer M 22 . Concurrently, the clock signal S 22 goes high resulting in the potential of the common signal COM 1 becoming equal to the intermediate potential V 2 .

If the clock signal S 22 goes low in the non-selection period of the common signal COM 1 , the potential of the common signal COM 1 becomes equal to the intermediate potential V 1 . Thus, in the non-selection period of the common signal COM 1 , the potential of the common signal COM 1 alternately becomes equal to the intermediate potential V 2 or V 1 in accordance with the level of the clock signal S 22 .

As described above, the common-signal output circuit 1 changes the potential of the common signal COM 1 in the ramp form at least if the potential falls from the power supply potential VDD to the power supply potential VSS.

As is understood from FIG. 3 , in such a driving method, the potential of the common signal COM 1 does not rise from the power supply potential VSS to the power supply potential VDD. Thus, the ramp waveform generation circuit 10 includes, as a current source, only the current source IS 12 connected to the power supply potential VSS.

Subsequently, an operation of the segment-signal output circuit 3 will be described.

A high-level period of the clock signal S 41 indicates the selection period of the common signal COMi, corresponding to a segment to be turned on, among the four segments corresponding to the segment signal SEGj. As described above, among the four segments, the two segments corresponding to the common signals COM 2 and COM 3 are turned on, and the clock signal S 41 is high during the selection periods of the common signals COM 2 and COM 3 .

The clock signals S 31 and S 32 both are signals equivalent to the clock signal S 22 . The clock signal S 33 is a clock signal whose falling edge alone is delayed with respect to that of the clock signal S 31 by a predetermined delay time period, and the clock signal S 34 is a clock signal whose rising edge alone is delayed with respect to that of the clock signal S 32 by the predetermined delay time period.

During the selection periods of the common signals COM 1 and COM 4 , the clock signal S 41 is low. Therefore, the potential of the segment signal SEGj outputted from the multiplexer M 41 becomes equal to the output potential of the multiplexer M 42 , and becomes equal to the intermediate potential V 1 while the clock signal S 22 is high and becomes equal to the intermediate potential V 2 while the clock signal S 22 is low.

When the selection period of the common signal COM 2 is started, the clock signal S 41 goes high, and the potential of the segment signal SEGj becomes equal to the potential of the connection point between the transistors T 31 and T 32 . At the same time, the clock signals S 31 to S 33 go high, the transistors T 31 and T 33 are turned off, and the transistor T 32 is turned on. Therefore, a sink current is supplied to the segment electrode of the liquid crystal panel 9 from the current source IS 32 as the segment signal SEGj. Then, the potential of the segment signal SEGj falls in the ramp form, due to the sink current, become equal to the power supply potential VSS, resulting in a ramp waveform Ra 2 falling from the intermediate potential V 2 to the power supply voltage VSS.

The clock signal S 34 goes high with a delay of a predetermined delay period with respect to the clock signal S 32 by a predetermined delay period and the transistor T 34 is turned on, resulting in sufficiently small output impedance. The delay period is set such that the clock signal S 34 goes high at least after the potential of the segment signal SEGj reaches the power supply potential VSS.

In the selection period of the common signal COM 2 , when the clock signals S 31 , S 32 , and S 34 go low at the same time, the transistor T 31 is turned on and the transistors T 32 and T 34 are turned off. Therefore, a source current is supplied to the segment electrode of the liquid crystal panel 9 from the current source IS 31 as the segment signal SEGj. Then, the potential of the segment signal SEGj rises in the ramp form due to the source current to the power supply potential VDD, resulting in a ramp waveform Ra 3 rising from the power supply potential VSS to the power supply potential VDD.

The clock signal S 33 goes low with a delay of a predetermined delay time period with respect to the clock signal S 31 and the transistor T 33 is turned on, resulting in sufficiently small output impedance. The delay period is set such that the clock signal S 33 goes low at least after the potential of the segment signal SEGj reaches the power supply potential VDD.

When the selection period of the common signal COM 3 is started, the clock signals S 31 to S 33 go high at the same time, and the transistors T 31 and T 33 are turned off and the transistor T 32 is turned on. Therefore, a sink current is supplied to the segment electrode of the liquid crystal panel 9 from the current source IS 32 as the segment signal SEGj. Then, the potential of the segment signal SEGj falls in the ramp form to the power supply potential VSS due to the sink current, resulting in a ramp waveform Ra 4 falling from the power supply potential VDD to the power supply potential VSS.

The clock signal S 34 goes high with a delay of a predetermined delay period with respect to the clock signal S 32 and the transistor T 34 is turned on, resulting in sufficiently small output impedance.

In the selection period of the common signal COM 3 , the operation in the case where the clock signals S 31 , S 32 , and S 34 go low at the same time, is similar to that in the case of the selection period of the common signal COM 2 . Therefore, the potential of the segment signal SEGj results in a ramp waveform Ra 5 rising from the power supply potential VSS to the power supply potential VDD similarly to the ramp waveform Ra 3 .

As described above, the segment-signal output circuit 3 changes the potential of the segment signal SEGj in the ramp form, at least if the potential falls from the power supply potential VDD to the power supply potential VSS or if the potential rises from the power supply potential VSS to the power supply potential VDD.

In order to realize this function, in an embodiment of the present invention, the segment-signal output circuit 3 changes the potential of the segment signal SEGj in the ramp form if the potential falls to the power supply potential VSS or rises to the power supply potential VDD. Therefore, other than the case of being changed in the ramp form with a potential difference of the power supply voltage V 0 , the potential of the segment signal SEGj might be changed in the ramp form with a potential difference of 1/3 V 0 (=V 2 −VSS) as in the ramp waveform Ra 2 .

Further, in an embodiment of the present invention, the source current supplied from the current source IS 31 and the sink current supplied from the current source IS 32 as the segment signal SEGj both correspond to a second constant-current signal.

As such, the liquid crystal driving circuit in an embodiment of the present invention changes the common signal COMi and the segment signal SEGj in the ramp form at least if the potential is changed with a potential difference of the power supply voltage V 0 . That is, if the potential of the signal is changed with the maximum potential difference, a rising time and a falling time are provided, thereby reducing a slew rate.

Therefore, even if the output impedance of the operational amplifier is equivalent to that in the case of the liquid crystal driving circuit illustrated in FIGS. 9 and 10 , the size and convergence time of the spike noises Sp can be reduced as illustrated in FIG. 3 . Thus, while favorable display quality is ensured, current consumption and a mounting area on the circuit board can be suppressed at the same time.

The slew rate can be reduced also by attenuating a high-frequency component using an RC filter instead of setting the common signal COMi and the segment signal SEGj in the ramp waveform. However, if the RC filter is used, the slew rate immediately after rising or falling is equivalent to that in the case of the ramp waveform, but, since time for reaching the power supply potential VDD or VSS becomes long, display defects such as flickering might occur in the liquid crystal panel.

—Configuration Example of Current Supply Circuit—

In an embodiment of the present invention, ramp waveforms of the common signal COMi and the segment signal SEGj have inclinations according to the currents supplied from the current sources IS 12 , IS 31 , and IS 32 . Therefore, the inclinations of the ramp waveforms can be changed by making the current values of the supplied currents variable.

FIG. 4 illustrates a configuration, as an example, in which inclination of a ramp waveform can be changed in accordance with current-value setting information (G 1 , G 2 , G 3 , and G 4 ) stored in a setting register SR using four circuits corresponding to the second current supply circuits among the ramp waveform generation circuits 30 .

A current source IS 311 connected to the power supply potential VDD, transistors T 311 and T 321 and a current source IS 321 connected to the power supply potential VSS are connected in series in this order, and correspond to one second current supply circuit. Also, an output signal of an OR circuit (logical sum circuit) O 311 , to which the clock signal S 31 and an inverting signal of the current-value setting signal G 1 are inputted, is inputted to a gate of the transistor T 311 . On the other hand, an output signal of an AND circuit (logical product circuit) A 321 , to which the clock signal S 32 and the current-value setting signal G 1 are inputted, is inputted to a gate of the transistor T 321 .

In the case of the current-value setting signal G 1 =1, the second current supply circuit can supply a current from the current source IS 311 or IS 321 in accordance with the clock signals S 31 and S 32 . On the other hand, in the case of the current-value setting signal G 1 =0, since both of the transistors T 311 and T 321 are turned off regardless of the clock signals S 31 and S 32 , a current is not supplied from the current sources IS 311 and IS 321 . Therefore, the second current supply circuit is set to be in use or not in use in accordance with the current-value setting signal G 1 . Other three second current supply circuits also have similar configurations and are set to be in use or not in use in accordance with the current-value setting signals G 2 to G 4 , respectively.

As such, by setting the current-value setting information (G 1 , G 2 , G 3 , and G 4 ) as appropriate, the number of the second current supply circuits can be set, which is configured to supply currents corresponding to the second constant-current signals as the segment signals SEGj, and the inclination of the ramp waveform can be changed. Similarly, the inclination of the ramp waveform can be changed in the common signal COMi.

If the inclination of the ramp waveform is small, the spike noises Sp cannot sufficiently be suppressed, which might cause an image to remain. On the other hand, if the inclination of the ramp waveform is great, time for the potentials of the common signal COMi and the segment signal SEGj to reach the power supply voltage VDD or VSS become long, which might cause flickering or the like. Thus, by connecting the liquid crystal panel 9 in actuality and changing the inclination of the ramp waveform while the state of display is being checked, an adjustment can be made so as to obtain the optimal display quality.

—Other Driving Methods of Liquid Crystal Driving Circuit—

In an embodiment according to the present invention, the liquid crystal driving circuit has been described which is configured to use 1/3 bias driving as the driving method, but it is not limited thereto.

FIG. 5 illustrates an operation of the liquid crystal driving circuit configured to perform 1/2 bias driving. As illustrated in FIG. 5 , in the 1/2 bias driving method, the segment signal SEGj is not at the intermediate potential V 1 but at only the power supply potential VDD or VSS which is sufficiently stable as compared with the intermediate potential V 1 . Therefore, in this driving method, it is only necessary that only the segment signal SEGj is set in the ramp waveform, thereby suppressing the spike noises generated in the common signal COMi. Since all the changes in the potential of the segment signal SEGj are changes in the potential difference of the power supply voltage V 0 , the potential of the segment signal SEGj results in being changed in a ramp form on every occasion.

A 1/3 bias driving method is illustrated in FIG. 6 . In this driving method, the potentials of the common signal COMi and the segment signal SEGj is changed with a potential difference of 2/3 V 0 , which is surrounded by broken lines, but the potentials thereof are not changed with a potential difference of the power supply voltage V 0 . Therefore, in this driving method, the potential is changed in the ramp form at least in the case where the potentials of the common signal COMi and the segment signal SEGj are changed with the potential difference 2/3 V 0 which is the maximum possible potential difference.

In any driving method, it is only necessary that the potential is changed in the ramp form at least in the case where the potentials of the common signal COMi and the segment signal SEGj are changed with the maximum potential difference, and the potential may be changed in the ramp form in the case where the potentials thereof are changed with other differences. For example, a configuration may be such that the potentials of the common signal COMi and the segment signal SEGj are changed in the ramp form on every occasion.

As described above, in the liquid crystal driving circuit including the segment-signal output circuit 3 illustrated in FIG. 1 , at least in the case where the potential of the segment signal SEGj is changed with the potential difference which is the maximum possible potential difference, by changing the potential of the segment signal SEGj in the ramp form, the slew rate can be reduced and the spike noises Sp generated in the common signal COMi can be suppressed, so that favorable display quality can be ensured while current consumption and a mounting area on the circuit board can be suppressed.

Moreover, in the liquid crustal driving circuit further including the common-signal output circuit 1 illustrated in FIG. 1 , at least in the case where the potential of the common signal COMi is changed with the maximum possible potential difference, by changing the potential of the common signal COMi in the ramp form, the slew rate can be reduced and the spike noises Sp generated in the segment signal SEGj can also be suppressed.

Moreover, at least in the case where the potentials of the common signal COMi and the segment signal SEGj are changed with the potential difference of the power supply voltage V 0 , by changing the potentials of the common signal COMi and the segment signal SEGj in the ramp form, the spike noises Sp generated in the common signal COMi and the segment signal SEGj can be suppressed, in the driving method that has a change in potential difference of the power supply voltage V 0 .

Moreover, by supplying the first and second constant-current signals supplied from the current sources IS 12 , IS 31 , and IS 32 , as the common signal COMi and the segment signal SEGj, to the common electrode and the segment electrode of the liquid crystal panel 9 , respectively, the potentials of the common signal COMi and the segment signal SEGj can be changed in the ramp form.

Moreover, by setting the number of the first and second current supply circuits configured to respectively supply the first and second constant-current signals, using a plurality of the first and second current supply circuits, the inclinations of the ramp waveforms of the common signal COMi and the segment signal SEGj can be changed, and the liquid crystal panel 9 can be adjusted to be of optimal display quality.

The above embodiments of the present invention are simply for facilitating the understanding of the present invention and are not in any way to be construed as limiting the present invention. The present invention may variously be changed or altered without departing from its spirit and encompass equivalents thereof.