Coating and developing apparatus and method

This application is based on and claims the benefit of priority to Japanese Patent Application No. 2010-156592 filed on Jul. 9, 2010, the entire contents of which are incorporated herein by reference.

1. Field of the Invention

The present disclosure relates to a coating and developing apparatus and method for applying a resist to a substrate and developing the resist after exposure.

2. Description of Related Art

A semiconductor manufacturing process includes a photolithography process comprising applying a photoresist (hereinafter simply referred to as a resist) to a surface of a semiconductor wafer (hereinafter simply referred to as a wafer), exposing the resist in a predetermined pattern, and developing the exposed resist to form a resist pattern. A coating and developing apparatus for forming such a resist pattern includes a processing block having processing modules for performing various types of processing of a wafer.

The processing block is comprised of a stack of unit blocks for forming various types of coating films (e.g. resist film) and unit blocks for performing developing processing, as described e.g. in Japanese Patent Laid-Open Publication No. 2007-115831. A wafer undergoes processing in various processing modules, provided in the unit blocks, according to a predetermined sequence.

In order to meet recent demands for finer resist patterns, increased yield, etc., processing modules provided in a processing block are becoming diversified. For example, besides a resist film-forming module for applying a resist onto a substrate, such as a wafer and a developing module for supplying a developer to the substrate, a processing block may also be provide with a back surface cleaning module for cleaning the back surface of the substrate after resist coating and a liquid processing module that supplies a chemical solution onto the resist film to form an upper film over the resist film. With an increased number of diverse processing modules provided in a processing block of a coating and developing apparatus, there is a problem of how to reduce the increase in the footprint of the apparatus.

Stacking a plurality of unit blocks in a coating and developing apparatus, as described above, is effective for reducing the footprint of the apparatus. However, because a wafer is transported sequentially to the unit blocks, the operation of the entire coating and developing apparatus must be stopped when an abnormality occurs in one processing module or one unit block, or when performing maintenance of one processing module or one unit block. This significant lowers the operation efficiency of the apparatus.

The present disclosure provides a technique which can reduce the increase in the footprint of a processing block and which enables partial stop of a coating and developing apparatus upon the occurrence of an abnormality or upon maintenance, thereby reducing the lowing of the operation efficiency of the apparatus.

In one embodiment, there is provided a coating and developing apparatus including a carrier block, a processing block, and an interface block connectable to an exposure apparatus, said coating and developing apparatus being configured to transfer a substrate, which has been carried by a carrier into the carrier block, to the processing block, form at least two coating films, including a resist film, on the substrate in the processing block, send the substrate to the exposure apparatus via the interface block, develop the substrate after exposure, which has returned via the interface block, in the processing block, and transfer the substrate to the carrier block, wherein: the processing block includes a plurality of early-stage processing unit blocks vertically stacked on each other; a plurality of later-stage processing unit blocks vertically stacked on each other and provided on an interface block side of a stack of the early-stage processing unit blocks such that each of later-stage processing unit blocks is disposed laterally adjacent to respective ones of the early-stage processing unit blocks; a plurality of developing unit blocks vertically stacked on each other and vertically stacked on a stack of the early-stage processing unit blocks; and a plurality of auxiliary processing unit blocks vertically stacked on each other and provided on the interface block side of a stack of the developing processing unit blocks such that each of the auxiliary processing unit blocks is disposed laterally adjacent to respective ones of the developing processing unit blocks; each of the early-stage processing unit blocks is configured to perform the same coating processing of a substrate, has a plurality of processing modules, including an antireflection film-forming module as a liquid processing module for forming a lower antireflection film, a resist film-forming module as a liquid processing module for forming a resist film on the lower antireflection film, and heating modules for heating the substrate, and is provided with a transport mechanism that moves on a linear transport passage, extending from the carrier block side to the interface block side, to transport the substrate between the processing modules; each of the later-stage processing unit blocks is configured to perform the same coating processing of a substrate, has a plurality of processing modules, including an upper film-forming module as a liquid processing module for forming an upper film on the resist film, and heating modules for heating the substrate, and is provided with a transport mechanism that moves on a linear transport passage, extending from the carrier block side to the interface block side, to transport the substrate between the processing modules; each of the developing unit blocks is configured to perform the same developing processing of a substrate, has a plurality of processing modules, including developing modules for supplying a developer to the substrate, and heating modules for heating the substrate, and is provided with a transport mechanism that moves on a linear transport passage, extending from the carrier block side to the interface block side, to transport the substrate between the processing modules; each of the auxiliary unit blocks is configured to perform the same auxiliary processing of a substrate, has a plurality of processing modules, and is provided with a transport mechanism that moves on a linear transport passage, extending from the carrier block side to the interface block side, to transport the substrate between the processing modules; the coating and developing apparatus further includes: a plurality of first transfer units, each of which are disposed between the laterally adjacent early-stage processing unit and later-stage processing unit block to transfer a substrate therebetween; a plurality of second transfer units, each of which is disposed between the laterally adjacent developing unit block and auxiliary processing unit block to transfer a substrate therebetween; a vertically movable auxiliary transfer mechanism is provided to transport a substrate between the first transfer units and between the second transfer units; a plurality of third transfer units, provided on the carrier block side of each of the early-stage processing unit blocks and on the carrier block side of each of the developing unit blocks, each for transferring a substrate to the transport mechanism of each early-stage processing unit or from each developing unit block; a first transfer mechanism for transferring a substrate to distribute substrates from the carrier to the third transfer units associated with the early-stage processing unit blocks, and for transferring a substrate to return substrates from third transfer unit associated with the developing unit blocks to the carrier; and a second transfer mechanism for receiving a substrate before exposure which has been processed in the processing block, and for transferring a substrate to distribute substrates after exposure to the developing unit blocks.

In another embodiment, there is provided a coating and developing method, employing the aforementioned coating and developing apparatus, for processing a substrate upon occurrence of a failure in one of the early-stage processing unit blocks upon maintenance on it, the method including: forming a lower antireflection film and a resist film on a substrate by using the early-stage processing unit block other than the one early-stage processing unit block; thereafter transporting the substrate by the auxiliary transfer mechanism to the later-stage processing unit block disposed laterally adjacent to one early-stage processing unit block; and thereafter forming an upper film on the substrate by using the later-stage processing unit block disposed laterally adjacent to one early-stage processing unit block.

In yet another embodiment, there is provided a coating and developing method, employing the aforementioned coating and developing apparatus, for processing a substrate upon occurrence of a failure in one of the later-stage processing unit blocks or upon maintenance on it, the method including: forming a lower antireflection film and a resist film on a substrate by using the early-stage processing unit block disposed laterally adjacent to the one later-stage processing unit block; thereafter transporting the substrate by the auxiliary transfer mechanism from the early-stage unit processing block disposed laterally adjacent to the one later-stage processing unit block to the later-stage processing unit block other than the one later-stage processing unit block; and thereafter forming an upper film on the substrate by using the later-stage processing unit block other than the one later-stage processing unit block.

In yet another embodiment, there is provided a non-transitory storage medium in which a computer program for use in a coating and developing apparatus is stored, said computer program being for executing at least one of the aforementioned coating and developing methods.

FIG. 1 is a plan view of a coating and developing apparatus in one embodiment;

FIG. 2 is a perspective view of the coating and developing apparatus;

FIG. 3 is a vertical sectional side view of the coating and developing apparatus;

FIG. 4 is a vertical sectional side view of the liquid processing modules of the coating and developing apparatus;

FIG. 5 is a vertical sectional front view of a posterior processing block;

FIG. 6 is a vertical sectional front view of an interface block;

FIG. 7 is a diagram showing the construction of the control section of the coating and developing apparatus;

FIG. 8 is a flow diagram illustrating wafer transport routes in the coating and developing apparatus;

FIG. 9 is a flow diagram illustrating wafer transport routes in the coating and developing apparatus;

FIG. 10 is a flow diagram illustrating wafer transport routes in the coating and developing apparatus;

FIG. 11 is a vertical sectional front view of another interface block;

FIG. 12 is a vertical sectional front view of yet another interface block; and

FIG. 13 is a vertical sectional side view of a coating and developing apparatus.

The construction of a coating and developing apparatus 1 will now be described with reference to FIGS. 1 to 3 . The coating and developing apparatus 1 includes a carrier block S 1 for receiving and delivering carriers C in each of which a plurality of, for example 25, wafers W are hermetically housed, a processing block S 2 for performing processing of the wafers W, and an interface block S 3 , the blocks being arrayed linearly. To the interface block S 3 is connected to an exposure apparatus S 4 for performing immersion exposure. For the convenience of description of positional relationships in a plan view of the apparatus, the right side of FIG. 1 is hereinafter referred to as “anterior”, the left side as “posterior”, the upper side as “left”, and the lower side as “right”.

The carrier block S 1 includes stages 11 for placing the carriers C thereon, shutters 12 provided in a wall in front of the stages 11 , and a transfer arm 13 for taking wafers W out of the carriers C via the shutters 12 . The transfer arm 13 has five wafer holders 14 arranged in the vertical direction, and is configured to be movable back and forth, vertically movable, rotatable on a vertical axis and movable in the carrier C arrangement direction. The below-described control section 51 assigns ID numbers to wafers W in each carrier C, and the transfer arm 13 transfers the wafers W to a transfer module BU 1 of the processing block 520 in a sequential manner such that 5 wafers are transferred at a time and that the wafers W are transferred in order of increasing ID number.

An element having a space on which a wafer W can be placed is herein referred to as “module”. A module for carrying out processing of a wafer W, such as heating, processing with a liquid, supply of a gas, peripheral exposure, etc., is herein referred to as “processing module”; and a processing module for supplying a chemical solution or a cleaning liquid is herein referred to as “liquid processing module”.

The processing block S 20 consists of an anterior processing block S 2 provided on the carrier block S 1 side and a posterior processing block S 3 provided on the interface block S 4 side. The following description is given with reference also to FIG. 4 which is a schematic sectional side view of the anterior processing block S 2 and the posterior processing block S 3 . The anterior processing block S 2 is comprised of a stack of first to sixth anterior unit blocks B 1 to B 6 , stacked in this order from the lowest unit block B 1 , each for performing liquid processing of a wafer W. The anterior unit blocks B 1 to B 6 each have a liquid processing module for supplying a processing liquid (e.g. a film-forming liquid or a developer) to a substrate to perform liquid processing of the substrate, a heating module for heating the substrate, a main arm A which is a transport means for each unit block, and a transport region R 1 in which the main arm A moves. The layout of the modules, the main arm and the transport region are substantially the same among the anterior unit blocks. A wafer W is transported by the main arm A and is subjected to processing in each anterior unit block independently of the other blocks.

The first anterior unit block B 1 , as a representative of the six anterior unit blocks, will now be described with reference to FIG. 1 . The transport region R 1 , having a form of linear transport passage extending from the carrier block S 1 side toward the posterior processing block S 3 side, is formed in the center of the first anterior unit block B 1 . A liquid processing unit 21 is disposed on the right of the transport region R 1 , and shelf units U 1 to U 6 are disposed on the left of the transport region R 1 .

The liquid processing unit 21 is provided with an antireflection film-forming module BCT 1 and a resist film-forming module COT 1 , arranged in this order from the side of the carrier block S 1 to the side of the posterior processing block S 3 . The antireflection film-forming module BCT 1 includes two spin chucks 22 . Each spin chuck 22 is capable of attracting and holding a central portion of the back surface of a wafer W and is rotatable on a vertical axis. A top-open processing cup 23 surrounds the periphery of the spin chuck 22 and prevents scattering of a chemical solution. Upon processing of a wafer W, the wafer W is housed in the processing cup 23 , with the central portion of the back surface of the wafer W being held by the spin chuck 22 .

The antireflection film-forming module BCT 1 has a nozzle 24 which is shared by the two processing cups 23 . The nozzle 24 is supported by an arm 25 . A drive mechanism 26 , via the arm 25 , moves the nozzle 24 in the arrangement direction of the processing cups 23 and vertically moves the nozzle 24 . Thus, the nozzle 24 can be moved by means of the drive mechanism 26 between the two processing cups 23 . The nozzle 24 can therefore eject an antireflection film-forming chemical solution toward the center of a wafer W held by each spin chuck 22 . The chemical solution, which has been supplied from the nozzle 24 to the wafer W, spreads to the periphery of the wafer W due to centrifugal force caused by the rotation of the wafer W on a vertical axis, whereby an antireflection film is formed on the wafer W. Though not depicted, the antireflection film-forming module BCT 1 is provided with a nozzle for supplying a solvent to a peripheral portion of a wafer W to remove an unnecessary film in the peripheral portion.

The resist film-forming module COT 1 has substantially the same mechanical construction as the antireflection film-forming module BCT 1 . Thus, the resist film-forming module COT 1 has two processing cups 23 for processing of a wafer W and has two spin chucks 22 , and the two processing cups 23 and the two spin chucks 22 share one nozzle 24 . Instead of the antireflection film-forming chemical solution, a resist is supplied from the nozzle 24 .

The shelf units U 1 to U 6 are arranged in this order from the side of the carrier block S 1 to the side of the posterior processing block S 3 . The shelf units U 1 to U 6 are each comprised of heating modules 27 , stacked e.g. in two stages, for performing heating of a wafer W. The anterior unit block B 1 thus has 12 heating modules 27 . The main arm A 1 is provided in the transport region R 1 . The main arm A 1 is configured to be movable back and forth, vertically movable, rotatable on a vertical axis and movable from the side of the carrier block S 1 to the side of the posterior processing block S 3 , so that a wafer W can be transferred between all the modules of the anterior unit block B 1 .

The anterior unit blocks B 2 and B 3 will now be described. The second anterior unit block B 2 and the third anterior unit block B 3 each have the same construction as the above-described first anterior unit block B 1 . As shown in FIG. 4 , reference symbol “BCT 2 ” is used for the antireflection film-forming module provided in the second anterior unit block B 2 , and reference symbol “COT 2 ” is used for the resist film-forming module. Further, reference symbol “BCT 3 ” is used for the antireflection film-forming module provided in the third anterior unit block B 3 , and reference symbol “COT 3 ” is used for the resist film-forming module. The anterior unit blocks B 1 to B 3 constitute early-stage processing unit blocks for performing early-stage processing of a sequence of coating film-forming steps.

The anterior unit blocks B 4 to B 6 , which are unit blocks for developing processing, will now be described. The fourth anterior unit block B 4 differs from the first anterior unit block B 1 in that instead of the one antireflection film-forming module (BCT 1 ) and the one resist film-forming module (COT 1 ) of the latter, the former is provided with two developing modules DEV 1 , DEV 2 . The fifth anterior unit block 65 and the sixth anterior unit block B 6 each have the same construction as the fourth anterior unit block B 4 , and are each provided with two developing modules. Reference symbols “DEV 3 ” and “DEV 4 ” are used for the developing modules provided in the fifth anterior unit block B 5 . Reference symbols “DEV 5 ” and “DEV 6 ” are used for the developing modules provided in the sixth anterior unit block 66 . Each of the developing modules (DEV 1 to DEV 6 ) has the same mechanical construction as each of the resist film-forming modules (COT 1 to COT 3 ), but supplies a developer instead of a resist.

As shown in FIGS. 1 and 3 , a shelf unit U 7 , vertically extending across the anterior unit blocks B 1 to B 6 , is provided in the anterior processing block S 2 at a position facing the carrier block S 1 -side ends of the transport regions R 1 of the anterior unit blocks 61 to 66 . The shelf unit U 7 is comprised of a stack of a plurality of modules. In particular, hydrophobizing modules ADH 1 , ADH 2 and transfer modules CPL 11 , CPL 12 are provided in height positions corresponding to the first anterior unit block B 1 . Hydrophobizing modules ADH 3 , ADH 4 and transfer modules CPL 13 , CPL 14 are provided in height positions corresponding to the second anterior unit block B 2 . Hydrophobizing modules ADH 5 , ADH 6 and transfer modules CPL 15 , CPL 16 are provided in height positions corresponding to the third anterior unit block B 3 .

A transfer module CPL 21 and a transfer module BU 11 are provided in height positions corresponding to the fourth anterior unit block B 4 . A transfer module CPL 22 and a transfer module BU 12 are provided in height positions corresponding to the fifth anterior unit block 65 . A transfer module CPL 23 and a transfer module BU 13 are provided in height positions corresponding to the sixth anterior unit block B 6 . A transfer module with the reference symbol “CPL” is provided with a cooling stage for cooling a wafer W placed on it. A transfer module with the symbol “BU” is configured to be capable of housing and retaining a plurality of wafers W.

The hydrophobizing modules ADH 1 to ADH 4 supply a processing gas to a wafer W to enhance the hydrophobicity of the surface of the wafer W, thereby preventing a film from peeling off the wafer W upon immersion exposure. Especially by enhancing the hydrophobicity of the bevel portion (peripheral end portion) of the wafer W, even when a film(s) is removed from the bevel portion in a liquid processing module(s) and the surface of the bevel portion becomes exposed, the exposed surface has water repellency. This can prevent the remaining film(s) from peeling at the end portion, lying adjacent to the exposed bevel portion, upon immersion exposure.

Further, transfer modules BU 1 and CPL 10 , constituting a transfer section for wafer loading and unloading, are provided in the shelf unit U 7 in height positions accessible by the transfer arm 13 of the carrier block S 1 . The transfer module BU 1 has vertically-arranged 5 wafer holders to receive wafers W at a time from the transfer arm 13 . Wafers W, which have been transported to the transfer module BU 1 , are distributed to the anterior unit blocks B 1 to B 3 in order of increasing ID number assigned by the control section 51 . The transfer module CPL 0 is employed to return a wafer W to the carrier C.

The shelf unit U 7 is provided with an inspection module (INSP) 31 . The inspection module 31 inspects a wafer W after development for the presence or absence of an abnormality on various inspection items, such as pattern collapse, abnormal line width, poor resist dissolution, etc. When carrying wafers W out of the anterior unit blocks B 4 to B 6 , those which are scheduled to be carried into the inspection module 31 , are transported to the transfer modules BU 11 to BU 13 . On the other hand, those wafers W which are not scheduled to be carried into the inspection module 31 are returned to the carrier C without transporting them to the transfer modules BU 11 to BU 13 . By thus setting a transport path for each wafer, transport of wafers W is controlled such that the wafers W return to the carrier C in order of ID number, i.e. in order of transport from the carrier C. In the anterior processing block S 2 , a transfer arm 30 as a first transfer mechanism, configured to be vertically movable and movable back and forth, is provided in the vicinity of the shelf unit U 7 . The transfer arm 30 transports a wafer W between the modules of the shelf unit U 7

FIG. 5 is a vertical sectional front view of the posterior processing block S 3 . The posterior processing block S 3 is comprised of a stack of first to sixth posterior unit blocks D 1 to D 6 , stacked in this order from the lowest unit block D 1 , each for performing liquid processing of a wafer W. The posterior unit blocks D 1 to D 6 are located laterally adjacent to the anterior unit blocks B 1 to B 6 , respectively, and are located at the same level as the anterior unit blocks B 1 to B 6 , respectively. The posterior unit blocks D 1 to D 6 each have a liquid processing module, a heating module, a main arm E, and a transport region R 2 in which the main arm E moves. In a plan view, the modules, the main arm and the layout of the transport region are the same among the posterior unit blocks D 1 to D 6 . A wafer W is transported by the main arm E and is subjected to processing in each posterior unit block independently of the other blocks. The first posterior unit block D 1 , as a representative of the six posterior unit blocks, will now be described with reference to FIG. 1 .

The transport region R 2 , having a form of a linear transport passage extending from the anterior processing block S 2 side toward the interface block S 4 side, is formed in the center of the first posterior unit block D 1 . A liquid processing unit 32 is disposed on the right of the transport region R 2 , and shelf units U 8 and U 9 are disposed on the left of the transport region R 2 .

The liquid processing unit 32 is provided with a protective film-forming module TCT 1 . The protective film-forming module TCT 1 has the same mechanical construction as the above-described antireflection film-forming module BCT 1 except that a chemical solution for the formation of a water-repellent protective film, as an upper film, is supplied to a wafer W. Thus, the protective film-forming module TCT 1 has two processing cups 23 each for processing a wafer W and has two spin chucks 22 , and the two processing cups 23 and the two spin chucks 22 share one nozzle 24 .

The shelf units U 8 , U 9 are arranged in this order from the side of the carrier block S 1 to the side of the interface block S 4 . The shelf units U 8 , U 9 are each comprised of heating modules 33 , stacked e.g. in two stages, for performing heating of a wafer W. The posterior unit block D 1 thus has 4 heating modules 33 . The main arm E 1 is provided in the transport region R 2 . The main arm E 1 is configured to be movable back and forth, vertically movable, rotatable on a vertical axis and movable from the side of the anterior processing block S 2 to the side of the interface block S 4 , so that a wafer W can be transferred between all the modules of the posterior unit block D 1 .

The posterior unit blocks D 2 and D 3 will now be described. The second posterior unit block D 2 and the third posterior unit block D 3 each have the same construction as the above-described first posterior unit block D 1 . Reference symbol “TCT 2 ” is used for the protective film-forming module provided in the second posterior unit block D 2 . Reference symbol “TCT 3 ” is used for the protective film-forming module provided in the third posterior unit block D 3 . The posterior unit blocks D 1 to D 3 constitute later-stage processing unit blocks for performing later-stage processing of a sequence of coating film-forming steps.

The posterior unit blocks D 4 to D 6 , which constitute auxiliary unit blocks, will now be described. The fourth posterior unit block D 4 differs from the first posterior unit block D 1 in that instead of the protective film-forming module of the latter, the former is provided with a back surface cleaning module BST 1 . The back surface cleaning module BST 1 has the same construction as the antireflection film-forming module BCT except that instead of a nozzle 24 for supplying a chemical solution to the front surface of a wafer W, the former is provided with a nozzle for supplying a cleaning liquid to the back surface and the bevel portion of a wafer W to clean the back surface of the wafer W. The back surface cleaning module BST 1 may be configured to clean only the back surface of a wafer W or only the bevel portion. The shelf units U 8 , U 9 are each comprised of one heating module 33 . Except for the above differences, the fourth posterior unit block D 4 has the same construction as the first posterior unit block D 1 .

The fifth posterior unit block D 5 and the sixth posterior unit block D 6 each have the same construction as the fourth posterior unit block D 4 . Reference symbol “BST 2 ” is used for the back surface cleaning module of the fifth posterior unit block D 5 , and reference symbol “BST 3 ” is used for the back surface cleaning module of the sixth posterior unit block D 6 . Note that the reference signs designating the antireflection film-forming modules (BCT 1 to BCT 3 ), the resist film-forming modules (COT 1 to COT 3 ), the protective film-forming modules (TCT 1 to TCT 3 ), the back surface cleaning modules (BST 1 to BST 3 ) and the developing modules (DEV 1 to DEV 6 ) are sometimes simplified by removing the numeral part thereof (e.g., COT 1 →COT) in a case where there is no need to distinguish individual modules from each other.

As shown in FIGS. 1 and 3 , a shelf unit U 10 , vertically extending across the posterior unit blocks D 1 to D 6 , is provided in the posterior processing block S 3 at a position facing the anterior processing block S 2 -side ends of the transport regions R 2 of the posterior unit blocks D 1 to D 6 . The construction of the shelf unit U 10 will now be described. The shelf unit U 10 is comprised of a stack of a plurality of modules. A transfer module CPL 31 is provided in a height position corresponding to the first posterior unit block D 1 . A transfer module CPL 32 is provided in a height position corresponding to the second posterior unit block D 2 , and a transfer module CPL 33 is provided in a height position corresponding to the third posterior unit block D 3 . Further, a transfer module CPL 41 is provided in a height position corresponding to the fourth posterior unit block D 4 , a transfer module CPL 42 is provided in a height position corresponding to the fifth posterior unit block D 5 , and a transfer module CPL 43 is provided in a height position corresponding to the sixth posterior unit block D 6 .

Each module of the shelf unit U 10 is accessible by the main arm E of a posterior unit block D located at the same level as the module and by the main arm A of an anterior unit block B located at the same level as the module. In the posterior processing block S 3 , a transfer arm 40 , constituting an auxiliary transfer mechanism, is provided in the vicinity of the shelf unit U 10 . The transfer arm 40 is configured to be vertically movable and movable back and forth with respect to the shelf unit U 10 . The transfer arm 40 transports a wafer W between the modules, lying in height positions corresponding to the unit blocks B 1 to B 6 , of the shelf unit U 10 .

The construction of the interface block S 4 will now be described with reference also to FIG. 6 . The interface block S 4 is provided with a shelf unit U 11 in a position accessible by the main arms E 1 to E 6 of the posterior unit blocks D 1 to D 6 . The shelf unit U 11 has transfer modules TRS 1 to TRS 3 , TRS 4 to TRS 6 and TRS 7 to TRS 9 in height positions corresponding to the unit blocks D 4 , D 5 and D 6 , respectively, and has transfer modules CPL 51 , CPL 52 and CPL 53 in height positions corresponding to the unit blocks D 1 , D 2 and D 3 , respectively. The shelf unit U 11 also has transfer modules BU 21 to BU 23 and CPL 54 . These modules are stacked on top of each other.

The interface block S 4 is provided with a stack of a plurality of, for example four, post-exposure cleaning modules PIR 1 to PIR 4 . Each post-exposure cleaning module PIR has the same mechanical construction as each resist film-forming module COT, but supplies, instead of a resist, a chemical solution for removal of a protective film and for cleaning to the surface of a wafer W.

The interface block S 4 is also provided with three interface arms 35 , 36 , 37 . The interface arms 32 , 33 , 34 are configured to be vertically movable and movable back and forth. The interface arm 35 is also movable in a horizontal direction. The interface arm 35 approaches the exposure apparatus S 5 and the transfer modules BU 21 , CPL 52 , CPL 51 to transfer a wafer W between them. The interface arm 36 approaches the transfer modules BU 22 , BU 23 , TRS 1 to TRS 6 to transfer a wafer W between these modules. The interface arm 37 approaches all the modules of the shelf unit U 11 and the post-exposure cleaning modules PIR 1 to PIR 4 to transfer a wafer W between these modules.

The control section 51 provided in the coating and developing apparatus 1 will now be described with reference to FIG. 7 . In FIG. 7 , reference numeral 52 indicates a bus, 53 indicates a CPU, and 54 indicates a program. The program 54 contains instructions (steps) to output control signals to various components of the coating and developing apparatus 1 , to transport wafers W between modules in the below-described manners, and to carry out processing of each wafer W, such as supply of a chemical solution or a cleaning liquid, heating, etc. The program 54 is stored in a storage medium such as flexible disk, compact disk, hard disk, MO (magneto-optical) disk, memory card, etc., and installed in the control section 51 .

A memory 55 is connected to a bus 52 . The memory 55 contains an area in which values of process parameters, such as processing temperature, processing time, the amount of a chemical solution supplied, electric power, etc. are written. When the CPU 53 executes the instructions of the program 54 , the process parameters are retrieved, and control signals according to the parameter values are sent to the components of the modules of the coating and developing apparatus 1 .

The memory 55 contains a transport schedule storage area 56 . The ID of a wafer W, the modules to which the wafer W is to be transported and the order of transport to the modules are, in their relation, stored as a transport schedule in the transport schedule storage area 56 . The transport schedule also specifies which one of the two processing cups 23 of a liquid processing module a wafer W is to be carried into. Though the transport schedule is set prior to processing of wafers W, it is changed upon a determination to stop wafer transport to a unit block(s) or a module(s), as will be described later.

A setting section 57 is connected to the bus 52 . The setting section 57 is, for example, comprised of a keyboard and a mouse, a tough panel, or the like, so that the user can select a transport mode for wafers W. As will be described later, besides mode switching performed by the user, transport modes are switched automatically in some cases. Upon switching to a transport mode, control signals according to the switched transport mode are sent to the main arms. A, E, the transfer arms 13 , 30 , 40 and the interface arms 35 to 37 so that wafers W will be transported along switched transport routes. The user can also specify a wafer W to be inspected in the inspection module 31 by specifying the wafer ID via the setting section 57 .

The main arms A and the main arms E each output a positional signal, indicating the position of the main arm, to the control section 51 and, based on the positional signal, the control section 51 determines the presence or absence of an abnormality in the operation of the main arm. The processing modules each output a signal, indicating the operation of the module, to the control section 51 and, based on the signal, the control section 51 determines the presence or absence of an abnormality in the operation of the processing module. The control section 51 changes the transport mode when it determines the presence of an operational abnormality in one of the main arms A, E and the processing modules of the unit blocks.

<Normal Transport Mode>

Transport routes for wafers W in the coating and developing apparatus 1 during the implementation of a normal transport mode will now be described. FIG. 8 schematically shows the flow of processing, together with the relevant unit blocks, in the normal transport mode. Wafers W, which have been transported from a carrier C to the buffer module BU 1 , are distributed to the first to third anterior unit blocks B 1 to B 3 . After processing in one of the three unit blocks, the wafers W are each transported along one of the following routes: the first anterior unit block B 1 →the first posterior unit block D 1 ; the second anterior unit block B 2 →the second posterior unit block D 2 ; the third anterior unit block B 3 →the third posterior unit block D 3 . After processing in the first to third posterior unit blocks D 1 to D 3 , the wafers W undergo processing in the fourth to sixth posterior unit blocks D 4 to D 6 . Thereafter, the wafers W are each carried into the exposure apparatus (EXP) S 5 . The wafers W from the exposure apparatus are distributed to the fourth to sixth posterior unit blocks D 4 to D 6 . Thereafter, the wafers W are each transported along one of the following routes: the fourth posterior unit block D 4 →the fourth anterior unit block B 4 ; the fifth posterior unit block D 5 →the fifth anterior unit block B 5 ; the sixth posterior unit block D 6 →the sixth anterior unit block B 6 , and returned to the carrier C.

In this embodiment, wafers W distributed to the posterior unit blocks D 1 , D 2 and D 3 are distributed to the posterior unit blocks D 4 , D 5 and D 6 , respectively. Further, wafers W are distributed to the unit blocks B 1 to B 3 in order of increasing wafer number assigned by the control section 51 and in a cyclic manner, e.g. in the order of unit block B 1 , B 2 , B 3 , B 1 , B 2 , B 3 , B 1 . . . .

The wafer transport route will now be described in greater detail. A wafer W which is distributed to the first anterior unit block B 1 , is transported in the order of: the buffer module BU 1 →the transfer arm 30 →the hydrophobizing module ADH 1 or ADH 2 . The wafer W after hydrophobizing processing is then transported by the main arm A 1 in the following order: the transfer module CPL 11 →the antireflection film-forming module BCT 1 →the heating module 27 →the transfer module CPL 12 →the resist film-forming module COT 1 →the heating module 27 →the transfer module CPL 31 . An antireflection film and a resist film are thus sequentially formed on the wafer W, and the wafer W is carried into the first posterior unit block D 1 .

The wafer W is transported by the main arm E 1 in the order of the protective film-forming module TCT 1 →the heating module 33 . A protective film is thus formed on the wafer W. Subsequently, the wafer W is transported to the transfer module CPL 51 of the interface block S 4 , and then transferred in the order of the interface arm 37 →the transfer module TRS 1 →the main arm E 4 . The wafer W is then transported to the back surface cleaning module BST 1 , where the back surface of the wafer is cleaned. Thereafter, the wafer W is transported in the order of the main arm E 4 →the transfer module TRS 2 . Thus, the wafer W is again carried into the interface block S 4 . Thereafter, the substrate W is transported in the following order: the interface arm 36 →the transfer module BU 22 or BU 23 →the interface arm 37 →the transfer module CPL 54 →the interface arm 35 →the exposure apparatus S 5 . The wafer W is thus subjected to immersion exposure.

The wafer W after immersion exposure is transported in the following order: the interface arm 35 →the transfer module BU 21 →the interface arm 37 →one of the post-exposure cleaning modules PIR 1 to PIR 4 the interface arm 37 →the transfer module TRS 3 . Thereafter, the wafer W is again carried by the main arm E 4 into the fourth posterior unit block D 4 , and transported in the order of the heating module 33 →the transfer module CPL 41 .

Thereafter, the wafer W is carried by the main arm A 4 into the fourth anterior unit block B 4 and transported in the following order: the developing module DEV 1 or DEV 2 →the heating module 27 →the transfer module CPL 21 →the transfer arm 30 →the transfer module BU 12 →the transfer arm 30 →the inspection module (INSP) 31 . Thus, the wafer W undergoes development, heating (post bake) and inspection. The wafer W after inspection is transported in the order of the transfer arm 30 →the transfer module CPL 10 →the transfer arm 13 , and is returned by the transfer arm 13 to the carrier C. A wafer W which is not an inspection object, after development and heating, is transported in the following order: the transfer module CPL 21 →the transfer arm 30 →the transfer arm 13 →the carrier C.

A wafer W which is distributed to the second anterior unit block B 2 , is transported in a similar manner to a wafer W distributed to the first anterior unit block B 1 . The transport route will be briefly described. The wafer W is transported in the order of: the buffer module BU 1 →the transfer arm 30 →the hydrophobizing module ADH 3 or ADH 4 . The wafer W is then transported by the main arm A 2 in the following order: the transfer module CPL 13 →the antireflection film-forming module BCT 2 →the heating module 27 →the transfer module CPL 14 →the resist film-forming module COT 2 →the heating module 27 →the transfer module CPL 32 .

Thereafter, the wafer W is transported in the following order: the main arm E 2 →the protective film-forming module TCT 2 →the main arm E 2 →the heating module 33 →the main arm E 2 →the transfer module CPL 52 →the interface arm 37 →the transfer module TRS 4 →the main arm E 5 →the back surface cleaning module BST 2 →the main arm E 5 →the transfer module TRS 5 . Thus, the wafer W is carried into the interface block S 4 .

In the interface block S 4 , the wafer W is transported in a similar manner to a wafer W distributed to the fist anterior unit block B 1 and, after post-exposure cleaning, the wafer W is transferred to the transfer module TRS 6 . Thereafter, the wafer W is transported in the following order: the main arm E 5 →the heating module 33 →the main arm E 5 →the transfer module CPL 42 →the main arm A 5 →the developing module DEV 3 or DEV 4 →the heating module 27 →the transfer module CPL 22 →the transfer arm 30 →the transfer module BU 12 →the transfer arm 30 →the inspection module 31 . Thereafter, the wafer W is returned to the carrier C along the same route as a wafer distributed to the unit block B 4 . A wafer W which is not an inspection object, after development and heating, is transported to the transfer module CPL 22 . The wafer W is then returned to the carrier C along the same route as a wafer distributed to the unit block B 4 .

A wafer W which is distributed to the third anterior unit block 133 , is also transported in a similar manner to a wafer W distributed to the first anterior unit block 131 . The transport route will be briefly described. The wafer W is transported in the order of: the buffer module BU 1 →the transfer arm 30 →the hydrophobizing module ADH 5 or ADH 6 . The wafer W is then transported by the main arm A 3 in the following order: the transfer module CPL 15 →the antireflection film-forming module BCT 3 →the heating module 27 →the transfer module CPL 16 →the resist film-forming module COT 3 →the heating module 27 →the transfer module CPL 35 .

Thereafter, the wafer W is transported in the following order: the main arm E 3 →the protective film-forming module TCT 3 →the main arm E 3 →the heating module 33 →the main arm E 3 →the transfer module CPL 53 →the interface arm 37 the transfer module TRS 7 →the main arm E 6 →the back surface cleaning module BST 3 the main arm E 6 the transfer module TRS 8 . Thus, the wafer W is carried into the interface block S 4 .

In the interface block S 4 , the wafer W is transported in a similar manner to a wafer W distributed to the fist anterior unit block B 1 and, after post-exposure cleaning, the wafer W is transferred to the transfer module TRS 9 . Thereafter, the wafer W is transported in the following order: the main arm E 6 →the heating module 33 →the main arm E 6 →the transfer module CPL 43 →the main arm A 6 →the developing module DEV 5 or DEV 6 →the heating module 27 →the transfer module CPL 23 →the transfer arm 30 →the transfer module BU 13 →the transfer arm 30 →the inspection module 31 . Thereafter, the wafer W is returned to the carrier C along the same route as a wafer distributed to the fourth anterior unit block 134 . A wafer W which is not an inspection object, after development and heating, is transported to the transfer module CPL 23 . The wafer W is then returned to the carrier C along the same route as a wafer distributed to the fourth anterior unit block B 4 .

<Transport Mode A>

Transport of wafers W during the implementation of a transport mode A will now be described. The transport mode A is a mode which is to be implemented when one of the anterior unit blocks B 1 to B 3 becomes unable to perform processing. In the transport mode A, after wafers W are processed in usable anterior unit blocks (two of the blocks B 1 to B 3 ), the wafers W are distributively transported to the posterior unit blocks D 1 to D 3 . The following description, made with reference to FIG. 9 , illustrates the case where the control section 51 detects an abnormality in the main arm A 1 . Upon detection of the abnormality, the control section 51 stops the operation of the main arm A 1 and the operation of each processing module of the anterior unit block B 1 . The transfer arm 30 then transport subsequent wafers W alternately to the second and third anterior unit blocks B 2 , B 3 . Each wafer W is transported and processed in the anterior unit block B 2 or B 3 along the above-described transport route, and is then transported to the transfer module CPL 32 or CPL 33 of the shelf unit U 10 .

Of the wafers W which have been transported to the transfer modules CPL 32 and CPL 33 , those wafers W which were scheduled to be processed in the first anterior unit block B 1 in the normal transport mode (in the case of no abnormality in the main arm A 1 ), are each transported by the transfer arm 40 to the transfer module 31 and carried by the main arm E 1 into the posterior unit block D 1 . The other wafers W are each carried by the main arm E 2 or E 3 from the transfer module CPL 32 or CPL 33 into the posterior unit block D 2 or D 3 . The wafers W which have been carried into the posterior unit block D 2 or D 3 , are each transported and processed in the same manner as in the normal transport mode. The user can perform repair on the first anterior unit block B 1 to which transport of wafers W has been stopped. Further, by changing the wafer transport route in the manner described above, the user can stop the operation of the first anterior unit block B 1 to perform its maintenance, such as periodic inspection, check of adjustment, etc.

When the anterior unit block B 2 or B 3 becomes unable to perform processing, wafers W are processed in usable anterior unit blocks as in the above-described case. Thereafter, the wafers W are distributed to those transfer modules CPL which are for carrying the wafers W into the posterior unit blocks D 1 to D 3 .

<Transport Mode B>

Transport of wafers W during the implementation of a transport mode B will now be described. The transport mode B is a mode which is to be implemented when one of the posterior unit blocks D 1 to D 3 becomes unable to perform processing. In the transport mode B, wafers W which have undergone processing in the anterior unit blocks B 1 to B 3 are distributed to usable ones of the posterior unit blocks D 1 to D 3 and, after processing in the usable unit blocks, the wafers W are distributed to the posterior unit blocks D 4 to D 6 .

The following description, made with reference to FIG. 10 , illustrates the case where an abnormality is detected in the main arm E 1 . Upon detection of the abnormality, the control section 51 stops the operation of the main arm E 1 and the operation of each processing module of the posterior unit block D 1 . Subsequent wafers W, which have been processed in the anterior unit block B 1 and transported to the transfer module CPL 31 , are distributively transported by the transfer arm 40 alternately to the transfer modules CPL 32 , CPL 33 of the shelf unit U 10 . The wafers W are then carried from the transfer modules CPL 32 , CPL 33 into the posterior unit blocks D 2 , D 3 , respectively, where the wafers W undergo processing. Thereafter, the wafers W are each transported to the transfer module CPL 52 or CPL 53 of the shelf unit U 11 .

Of the wafers W which have been transported to the transfer modules CPL 52 and CPL 53 , those wafers W which were scheduled to be carried into the first posterior unit block D 1 in the normal transport mode (in the case of no abnormality in the main arm E 1 ), are transported to the transfer module TRS 1 corresponding to the posterior unit block D 4 , and processed in the unit block D 4 . The other wafers W which have been transported to the transfer modules CPL 52 and CPL 53 are, as in the normal transport mode, carried into the transfer modules TRS 4 , TRS 7 , corresponding to the posterior unit blocks D 5 , D 6 , respectively, and processed in the posterior unit blocks D 5 , D 6 . After processing in the posterior unit blocks D 4 to D 6 , the wafers W are transported in the same manner as in the normal transport mode. The user can perform repair or maintenance on the first posterior unit block D 1 to which transport of wafers W has been stopped.

When the posterior unit block D 2 or D 3 becomes unable to perform processing, as in the above-described case, wafers W are distributed by the transfer arm 40 to usable ones of the posterior unit blocks D 1 to D 3 and, after processing in the usable unit blocks, the wafers W are distributed to the posterior unit blocks D 4 to D 6 .

Switching between the above-described transport modes is performed automatically during processing of wafers W. However, it is also possible for the user to instruct the control section 51 on switching to the mode A or B by selecting, e.g. via the setting section 57 , a unit block to which transport of wafers W is to be stopped. As described above, the user can perform maintenance on the stopped unit block.

Though in the above-described cases transport of wafers W is stopped to one of unit blocks which are tripled and have the same construction, it is also possible stop wafer transport to two of unit blocks having the same construction. Further, the modes A and B may be implemented in combination. Thus, it is possible to simultaneously stop transport of wafers W to one or two of the anterior unit blocks B 1 to B 3 and to one or two of the posterior unit blocks D 1 to D 3 .

In the coating and developing apparatus 1 , it is possible to stop transport of wafers W to particular unit blocks based on the results of inspection of wafers W in the inspection module 31 . In particular, when an abnormality is detected in a wafer W, the control section 51 stores the abnormality-related inspection item, the ID of the wafer W and the transport route, in their relation, in the memory 55 as an inspection history. The control section 51 , based on the past inspection histories of wafers W stored in the memory, determines whether an abnormality has been detected for the same inspection item and in a predetermined proportion of wafers W which have passed through the same unit blocks that the first defective wafer W has passed through.

Processing of wafers W is continued if it is determined that the proportion of wafers W in which an abnormality has been detected is less than the predetermined proportion. If it is determined that the proportion of wafers W in which an abnormality has been detected is not less than the predetermined proportion, the control section 51 determines to stop transport of wafers W to the unit blocks. The control section 51 then controls the operation of the transfer arms and the interface arms so that wafers W are distributed to the unit blocks of the same type as and other than a unit block to which transport of wafers is stopped. Thus, processing of wafers W is continued with the use of the unit blocks other than the unit blocks to which transport of wafers is stopped. Further, the control section 51 stops the operation of the processing modules and the main arm of a unit block to which transport of wafers is stopped, so that the user can perform inspection or maintenance on the unit block.

In the case of stopping wafer transport to particular unit blocks based on the results of inspection of wafers W as described above, unlike the above-described transport modes A, B, wafer transport is stopped to all the unit blocks that wafers W having an abnormality have passed through. Thus, wafer transport is stopped to those ones of the unit blocks B 1 to B 3 , D 1 to D 3 , B 4 to B 6 and D 4 to D 6 which wafers W having an abnormality have passed through.

In the coating and developing apparatus 1 , it is also possible to stop transport of wafers W to particular processing modules. In particular, when an abnormality is detected in a wafer W, the control section 51 stores the inspection history in the memory 55 as described above. The control section 51 , based on the past inspection histories of wafers W stored in the memory, determines whether an abnormality has been detected for the same inspection item and in a predetermined proportion of wafers W which have passed through the same processing modules that the first defective wafer W has passed through. If the criterion is met, the control section 51 stops transport of wafers W to the processing modules. Thus, in a unit block, wafers W are transported to the processing module of the same type as and other than a processing module to which transport of wafers is stopped, and transport of wafers W in the unit block is continued. However, with reference to a liquid processing module with the reference symbol BCT, COT, TCT or BST, one module is provide in each unit block. Therefore, when the stop of wafer transport to such a liquid processing module is determined, transport of wafers W to the unit block including the liquid processing module is stopped. The user can select via the setting section 57 whether to stop transport of wafers W to unit blocks or processing modules.

The coating and developing apparatus 1 has the following constructional features: a stack of the three anterior unit blocks B 1 to B 3 is provided for performing processing (early-stage film-forming processing) to form a lower antireflection film and a resist film on a wafer W; a stack of the posterior unit blocks D 1 to D 3 is provided for performing processing (later-stage film-forming processing) to form an upper film on the resist film; the stacks are anteroposteriorly coupled, and the transfer modules (CPL 31 to CPL 33 ) are provided for transfer of a wafer W between the anterior unit blocks (B 1 to B 3 ) and the corresponding posterior unit blocks (D 1 to D 3 ); and the transfer arm 40 is provided which is capable of transferring a wafer W between transfer modules of different layers (heights). Owing to such apparatus construction, even when one of the anterior unit blocks B 1 to B 3 becomes unusable e.g. due to a failure or maintenance, it is possible to process wafers W in usable anterior unit blocks, and to distribute the wafers W after processing to the posterior unit blocks D 1 to D 3 . Further, even when one of the posterior unit blocks D 1 to D 3 becomes unusable e.g. due to a failure or maintenance, it is possible to process wafers W in the anterior unit blocks 61 to 63 , and to distribute the wafers W after processing to usable ones of the posterior unit blocks D 1 to D 3 . The lowering of the throughput can therefore be reduced. Further, in the coating and developing apparatus 1 , the anterior unit blocks B 4 to B 6 for performing developing processing are stacked on the stack of the anterior unit blocks. B 1 to B 3 . This enables small installation area of the apparatus with a reduced length from the carrier block S 1 to the interface block S 3 .

In the coating and developing apparatus 1 , the shelf units U 8 , U 9 of the posterior unit blocks D 1 to D 3 may each be provided with an inspection module and a peripheral exposure module WEE for performing peripheral exposure of a substrate W after resist coating, in addition to the heating module 33 . In that case, a wafer W which has been carried into each of the posterior unit blocks D 1 to D 3 is transported in the order of the peripheral exposure module WEE→the inspection module→one of the protective film-forming modules TCT 1 to TCT 3 .

In the inspection module, a wafer W is inspected e.g. for the presence or absence of foreign matter on the surface of a resist film and the thickness of the resist film. When an abnormality is detected in a wafer W, wafer transport to unit blocks or processing blocks which have processed the wafer W can be stopped as described above. It is also possible to transport a wafer W in each of the posterior unit blocks D 1 to D 3 in the order of one of the protective film-forming modules TCT 1 to TCT 3 →the heating module 33 →the inspection module, and to inspect a wafer W after the formation of a protective film for foreign matter and the thickness of each film. Also in that case, when an abnormality is detected in a wafer W, the control section 51 makes the above-described determination based on the transport schedule and, if the criterion is met, stops transport of wafers W to processing modules or unit blocks that the defective wafer W has passed through.

With reference to the liquid processing modules with the reference symbols BCT, COT, TCT, BST, DEV, wafer transport may be stopped to an individual processing cup when stopping wafer transport to such processing modules based on the inspection results of one of the above-described inspection modules. Thus, transport of wafers W to the processing cup 23 of a processing module which has processed a wafer W in which an abnormality has occurred is stopped, whereas transport of wafers W to the processing cup 23 which shares a nozzle 24 with the stopped processing cup 23 may be continued. In the case of thus stopping transport of wafers W to an individual processing cup 23 , in order to adjust the number of wafers W to be processed in the apparatus, the apparatus may be operated in the following manner: For example, when nonuse of one processing cup 23 of one antireflection film-forming module (e.g. BCT 1 ) is determined, it is possible to set the apparatus not to use one processing cup 23 of one resist film-forming module (e.g. COT 1 ) which lies in the same unit block. Similarly, when nonuse of one processing cup 23 of one resist film film-forming module (e.g. COT 1 ) is determined, it is possible to set the apparatus not to use one processing cup 23 of one antireflection film-forming module (e.g. BCT 1 ) which lies in the same unit block. Further, also in the unit block(s) (e.g. BCT 2 and/or BCT 3 ) having the same construction as the unit block in which wafer transport to the one processing cup 23 of the resist film-forming module (e.g. COT 1 ) and to the one processing cup 23 of the antireflection film-forming module (e.g. BCT 1 ) is stopped, it is possible to stop wafer transport to one processing cup 23 of one of the resist film-forming modules and to one processing cup 23 of one of the antireflection film-forming modules in order to adjust the number of wafers W to be processed.

In the coating and developing apparatus 1 , instead of the protective-film forming modules TCT 1 to TCT 3 for forming a protective film overlaying a resist film, it is possible to use upper film-forming modules for forming a different type of film overlaying a resist film, for example, upper antireflection film-forming modules for forming an upper antireflection film. Further, instead of performing hydrophobizing processing in the hydrophobizing modules ADH 1 to ADH 6 before the formation of an antireflection film in the antireflection film-forming modules BCT 1 to BCT 3 , the hydrophobizing processing may be performed after the formation of an antireflection film and before resist coating, or after resist coating and before transporting wafers W to the posterior unit blocks D 1 to D 3 .

A chemical solution which has been supplied to a wafer W e.g. in the liquid processing unit 21 of the first anterior unit block B 1 , is discharged toward a not-shown drainage path provided below the coating and developing apparatus. Chemical solutions which are supplied to wafers W in the antireflection film-forming modules BCT 1 to BCT 3 and the resist film-forming modules COT 1 to COT 3 have a high viscosity than a developer. Accordingly, all the chemical solutions can be rapidly discharged by disposing the developing modules DEV 1 to DEV 6 in the upper anterior unit blocks and disposing the other liquid processing modules in the lower anterior unit blocks as in this embodiment. This can prevent vaporization of the chemical solutions in the processing modules, thereby preventing a change in the processing environment in each liquid processing unit 21 . However, a unit block(s) including a developing module DEV may be disposed below a unit block(s) including an antireflection film-forming module and a resist film-forming module.

FIG. 11 shows another interface block S 4 . The interface block S 4 of FIG. 11 differs from the interface block S 4 shown in FIG. 6 only in the provision of a stack of pre-exposure cleaning modules RD 1 to RD 4 . The pre-exposure cleaning modules RD 1 to RD 4 supply a cleaning liquid to the surface of a wafer W before exposure to rinse dissolved matter off the surface of the wafer W.

Wafers W which have been processed in the posterior unit blocks D 4 , D 5 , D 6 and transported respectively to the transfer modules TRS 2 , TRS 5 , TRS 8 of the interface block S 4 of FIG. 11 , are each transported by the interface arm 36 to one of the pre-exposure cleaning modules RD 1 to RD 4 , where the wafer is subjected to pre-exposure cleaning. After the cleaning, the wafer W is transported in the following order: the interface arm 36 →the transfer module BU 22 or BU 23 →the interface arm 37 →the transfer module CPL 54 →the exposure apparatus S 5 .

FIG. 11 shows yet another interface block S 4 . The interface block S 4 of FIG. 12 is provided with a stack of back surface cleaning modules BST 1 to BST 4 . In cases where back surface cleaning modules BST are provided in the interface block S 4 as in this embodiment, the back surface cleaning modules BST 1 to BST 3 are not provided in the posterior processing block S 2 connected to the interface block S 4 .

In the interface block S 4 , wafers W which have been transported to the transfer modules CPL 51 , CPL 52 , CPL 53 are each transported in the order of the interface arm 37 →the transfer module BU 22 →one of the back surface cleaning modules BST 1 to BST 4 , where the back surface of the wafer W is cleaned. The wafer W is then transported in the order of the interface arm 36 →the transfer module BU 23 →the interface arm 37 . Thereafter, the wafer W is transported along the above-described transport route and transferred to the exposure apparatus S 5 . In cases where back surface cleaning modules (BST) are provided in the interface block S 4 as in this embodiment, post-exposure cleaning modules (PIR) may be provided, instead of the back surface cleaning modules BST 1 to BST 3 , in the posterior unit blocks D 4 to D 6 .

The coating and developing apparatus 1 may be provided with a transport mode C to transport wafers W while bypassing an unusable one of the posterior unit blocks D 4 to D 6 . In the transport mode C, wafer transport is stopped to those ones of the transfer modules of the shelf unit U 10 of the posterior processing block S 3 and the transfer modules of the shelf unit U 11 of the interface block S 4 , which are for transferring wafers W to a unit block which has become unusable. Wafers W after exposure, which have been transported to transfer modules of the shelf unit U 10 , are distributed to the anterior unit blocks B 4 to B 6 .

In particular, upon the occurrence of a failure e.g. in the main arm E 4 of the posterior unit block D 4 , the interface arm 37 stops access to the transfer modules TRS 1 to TRS 4 corresponding to the posterior unit block D 4 . Wafers W which have been processed in the posterior unit blocks D 1 to D 3 and carried into the transfer modules CPL 51 to CPL 53 are distributed by the interface arm 37 to the transfer modules TRS 4 , TRS 7 corresponding to the posterior unit blocks D 5 , D 6 . Further, the interface arm 37 distributes wafers W after exposure to the transfer modules TRS 6 , TRS 9 corresponding to the posterior unit blocks D 5 , D 6 . Of wafers W after exposure which have been transported from the posterior unit blocks D 5 , D 6 to the transfer modules CPL 42 , CPL 43 , respectively, those wafers W which were scheduled to be transported through the posterior unit block D 4 are transferred by the transfer arm 40 to the transfer module CPL 41 . The wafers W which have been carried into the transfer modules CPL 41 , CPL 42 , CPL 43 are transported to the anterior unit blocks B 4 , B 5 , B 6 , respectively, and undergo developing processing.

The coating and developing apparatus 1 may be provided with a transport mode D to transport wafers W while bypassing an unusable one of the anterior unit blocks B 4 to B 6 . In the transport mode D, of wafers W which have undergone exposure processing and have been transported to the transfer modules CPL 41 , CPL 42 , CPL 43 of the shelf unit U 10 , those wafers W which have been transferred to a transfer module (e.g. CPL 41 ) corresponding to a unit block which has become unusable (e.g. B 4 ), are each transported by the transfer arm 40 to another transfer module (e.g. CPL 42 or CPL 43 ). Each wafer W is subjected to developing processing in a usable unit block (e.g. B 5 or B 6 ) of the anterior unit blocks B 4 to B 6 .

In particular, upon the occurrence of a failure e.g. in the main arm A 4 of the anterior unit block B 4 , the transfer arm 40 transports wafers W, which have undergone exposure processing and have been transported to the transfer module CPL 41 , alternately to the transfer modules CPL 42 , CPL 43 . The wafers W in the transfer modules CPL 42 , CPL 43 are then subjected to developing processing in the anterior unit blocks B 5 , B 6 , respectively. As with the transport mode A or B, the user can arbitrarily switch the normal transport mode to the transport mode C or D. The transport mode C or D may be implemented simultaneously with the transport mode A or B.

As shown in FIG. 13 , instead of the transfer arm (a single transfer mechanism) 40 shown in FIG. 1 , it is possible to provide a first transfer arm (a first transfer device) 41 which transports a wafer W between the transfer modules, corresponding to the unit blocks B 1 to B 3 , in the shelf unit U 10 , and a second transfer arm (a second transfer device) 42 which transports a wafer W between the transfer modules, corresponding to the unit blocks B 4 to B 6 , in the shelf unit U 10 . By thus providing the two separate transfer arms 41 , 42 which transport a wafer W independent of each other, it becomes possible to reduce the transport load on each arm and increase the throughput.