Data dependent SRAM write assist

This invention relates generally to semiconductor chips, and more specifically to an SRAM (Static Random Access Memory) having a data dependent write assist feature.

A semiconductor chip comprises an SRAM (static random access memory) having a data dependent write assist to provide increased write performance.

During write of an SRAM cell, true and complement bit lines are driven to “1” and “0” (or “0” and “1”) depending on a logical value to be written to the SRAM cell. A word line turns on pass gates, and the logical value driven on the true and complement bits lines are written through the pass gates into a data retention circuit comprising cross coupled inverters in the SRAM cell. During a write, a circuit driving a bit line low (“0”) must compete, for a while, with an inverter of the cross coupled inverters driving “1” until overcome, assuming that data in the SRAM cell is being changed.

In an embodiment of the invention, a voltage supply of a first inverter is reduced if a “0” is going to be driven onto a first bit line (e.g., the true bit line) that is connected, through a pass gate, to an output of the first inverter. Drive capability of the first inverter is reduced by the reduced voltage supply, making it faster for the circuit driving the first bit line to write data into the SRAM cell. Similarly, if a second bit line (e.g., the complement bit line) is driven low (“0”), a voltage supply of a second inverter is reduced, thereby making the second inverter easier to overcome.

FIG. 1 shows a schematic of a chip having an SRAM with a data dependent SRAM write assist.

FIG. 2 shows a simulation under nominal conditions of an SRAM write for an SRAM with a data dependent write assist circuit and for an SRAM write for an SRAM without a data dependent write assist circuit.

FIG. 3 shows a series of simulations used to determine how much to reduce a voltage supply on a cross coupled inverter in an SRAM cell for a desired power/performance tradeoff.

FIG. 4 is a flow chart of a method embodiment of the invention.

FIG. 5 shows additional detail of an SRAM cell.

In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and within which are shown by way of illustration specific embodiments by which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the invention.

Embodiments of the present invention provide a data dependent SRAM (static random access memory) write assist in an SRAM on a semiconductor chip. The data dependent SRAM write assist provides for improved (faster) write times when data is being written to the SRAM.

With reference now to FIG. 1 , a semiconductor chip 10 comprises an SRAM 20 . In the schematic and description thereof, all FETs beginning with “N” (e.g., N 1 ) are N-channel Field Effect Transistors (NFETs); all FETs beginning with “P” (e.g., P 1 ) are P-channel Field Effect Transistors (PFETs).

SRAM 20 comprises one or more SRAM cells 110 . SRAM cell 110 further comprises cross coupled inverters 111 and 112 to store a bit of data. N 1 and N 2 are coupled to a word line WL. When WL is activated, N 1 and N 2 turn on and couple bit lines BLT (bit line true) and BLC (bit line complement) to the cross coupled inverters 111 and 112 . Inverter 111 drives node 116 ; inverter 112 drives node 115 . During a write, BLT and BLC are driven to “0” and “1” (or “1” and “0”, depending on a logical value to be written into SRAM cell 110 ).

Typically in an SRAM 20 , WL is connected to a number (e.g., 32, 64, 128, and so on) of SRAM cells 110 , although only a single SRAM cell 110 is shown for simplicity. Likewise, bit lines BLT and BLC are typically connected to a number (e.g., 32, 64, 128, and so on) of SRAM cells 110 ; again, only a single SRAM cell 110 is shown for simplicity. Vdd 1 and Vdd 2 are connected to each SRAM cell 110 that BLT and BLC are connected to.

Data dependent write assist circuit 120 drives BLT and BLC when WR_EN (write enable) is active (“1”).

When DT (data true) is “1”, DC (data complement) is “0”. DT will turn on N 5 ; DC, being “0”, will have N 6 turned off. BLC will be pulled low “0” through N 5 and N 7 . N 1 , activated by WL being “1”, will need to overcome current driven from inverter 112 , assuming that inverter 112 is driving a “1” (that is, a bit stored in SRAM cell 110 is being changed). BLC will need to pull node 115 low enough to cause inverter 111 to drive a “1” instead of a “0”. If inverter 112 were already driving a “0” data stored in SRAM cell 110 is not being changed. Similarly, if DT is “0”, DC will be “1”; BLT will be driven to “0” through N 6 and N 7 , and an output of inverter 111 must be overcome (assuming data in SRAM cell 110 is being changed) to write the “0” in SRAM cell 110 .

P 5 , P 6 , P 7 , and P 8 in data dependent write assist circuit 120 drive BLT and BLC to Vdd when WR_EN is “0” and RD (read) is “0”, thereby precharging BLT and BLC to Vdd. When WR_EN is “0” (not writing data) and RD is “1” (read data), BLT and BLC are driven only by cross coupled inverters 111 and 112 through N 1 and N 2 , and a sense amplifier coupled to BLT and BLC determines whether a logical “1” or a logical “0” is stored in SRAM cell 110 .

Data dependent write assist circuit 120 , during a write (WR_EN=“1”) drives either Vdd or Vwr on Vdd 1 , and, at the same time, drives Vwr or Vdd onto Vdd 2 , depending upon whether data to be written to SRAM cell 110 is a “1” or a “0”. Vwr is a lower voltage than Vdd. Vwr will be supplied to either inverter 112 or inverter 111 depending on DT and DC.

Assume that DT=“1” (and, therefore, DC=“0”) during a write. NAND 121 will receive a “1” from WR_EN and a “1” from DT; NAND 121 will respond by driving a “0” to P 1 thereby connecting Vwr to Vdd 1 . Inverter 123 will output a “1” to P 2 , isolating Vdd from Vdd 1 . Inverter 112 will therefore have a reduced voltage supply and will, therefore, be easier to pull down through N 1 , N 5 and N 7 .

Similarly, when DT=“0” (and, therefore, DC=“1”) during a write, NAND 122 will drive a “0”, turning on P 3 and, through inverter 124 , turn off P 4 , thereby driving Vwr instead of Vdd onto Vdd 2 and making inverter 111 easier to overcome through N 2 , N 6 and N 7 .

FIG. 5 shows SRAM cell 110 in more detail. Inverter 111 further comprises PFET PA and NFET NA. A source of PA is connected to Vdd 2 and a source of NA is connected to Gnd. Drains of PA and NA are connected together at node 116 (see also FIG. 1 ). Inverter 112 comprises PFET PB and NFET NB. PB comprises a source connected to Vdd 1 ; NB comprises a sourced connected to Gnd. Drains of PB and NB are connected together at node 115 .

For exemplary purposes, SRAM cell 110 is shown having NFET pass gates (N 1 , N 2 ). This is a conventional SRAM cell using current technologies. It is contemplated that an SRAM cell may also be made having PFET pass gates. In such an embodiment, to write data into cross coupled inverters 111 , 112 , a bit line (BLT, BLC) would have to overcome an output of 111 , or 112 by pulling upwards, through a PFET pass gate, rather than pulling an output of 111 or 112 down. In general, “overcoming” an inverter is needed to change data stored in the cross coupled inverters. It will also be understood that, in the variant embodiment using PFET pass gates, reducing a supply voltage to make inverter 111 or 112 easier to overcome may also be implemented by raising a “ground” voltage supply to the inverter which is to be overcome, versus reducing a Vdd supply (such as Vwr instead of Vdd) to that inverter.

Turning now to FIG. 2 , a simulation showing comparative performance of writing an SRAM cell with and without benefit of data dependent write assist circuit 120 is shown. Nominal Vdd (0.85 volts) and nominal process conditions are used in the simulation of FIG. 2 . A write operation begins with a rise of WL. Vdd 1 is shown to fall from 0.85 volts to approximately 0.65 volts in a case having benefit of data dependent write assist. In a case simulated without benefit of data dependent write assist circuit 120 , both cross coupled inverters in the SRAM cell use Vdd (i.e., Vwr=Vdd) as a supply voltage. Nodes 115 , 116 ( FIG. 1 ) in the case without benefit of data dependent write assist are identified with a suffix “B” (e.g., nodes 115 B, 116 B). In the case simulated with benefit of data dependent write assist circuit 120 (Vwr=approximately 0.65 volts), nodes 115 , 116 ( FIG. 1 ) are identified with a suffix “A” (nodes 115 A, 116 A). Vdd 1 returns to Vdd when WL falls, as both NAND 121 and NAND 122 output “1”, which causes inverters 123 and 124 to output “0”, turning on P 2 and P 4 . Even at the nominal conditions used in the simulations of FIG. 2 , a significant write performance is achieved through use of data dependent write assist circuit 120 .

P 1 , P 2 , P 3 , and P 4 ( FIG. 1 ) must be designed large enough to bring Vdd 1 and Vdd 2 to Vwr and back to Vdd quickly enough (see simulation results of FIG. 2 ) to be effective in improving performance. Vdd 1 and Vdd 2 will supply voltage to inverters 111 and 112 for a number of SRAM cells 110 in typical SRAMs 20 , and will, therefore, have significant capacitance that must be partially discharged and re-charged by P 1 , P 2 , P 3 , and P 4 .

FIG. 3 shows a series of simulations using data dependent write assist circuit 120 , where Vwr is varied to determine an optimal value for Vwr. What is actually plotted is Vdd 1 when Vwr is selected for Vdd 1 , using NAND 121 and P 1 shown in FIG. 1 . The simulations of FIG. 3 assume a worst case set of parameters in environmental and process conditions, such as high thresholds on N 1 and N 2 , a low value of Vdd (0.8 volts), for examples. Each simulation run changes Vwr (Vdd 1 ) by 0.050 volts. Slowest responses to a rising WL occur when Vdd−Vdd 1 is 0.050 volts, that is, the least simulated amount of reduction of Vdd 1 from Vdd. As Vdd−Vdd 1 is increased, write performance improves (gets faster), but does not improve significantly beyond a Vdd−Vdd 1 of about 150 mV (millivolts). Since power is consumed to lower Vdd 1 and bring Vdd 1 back to Vdd at the end of a write cycle, a value of about 150 mV for Vdd−Vdd 1 , for the design simulated, is a reasonable tradeoff between power and increased write performance. Optimal value for Vdd−Vdd 1 will vary depending on technology. For example, an SRAM in an older technology using a Vdd of 1.5 volts may have an optimal value of Vdd−Vdd 1 greater than 150 mV). In addition, when low power consumption is a bigger concern than performance, a designer may choose a smaller value of Vdd−Vdd 1 ; for example, as seen in FIG. 3 , much of the benefit of data dependent write assist circuit 120 comes from a 100 mV value for Vdd−Vdd 1 (note that Vdd−Vdd 1 =0.0 was not simulated in FIG. 3 ).

Embodiments of the invention may be expressed as methods. FIG. 4 is a flowchart of a method 400 to improve performance of an SRAM, such as SRAM 20 of FIG. 1 . Method 400 begins at 402 .

In block 404 , an SRAM is created, comprising, for each bit to be stored in the SRAM, a first inverter (such as inverter 111 in FIG. 1 ) and a second inverter (such as inverter 112 in FIG. 1 ) are cross coupled to retain a bit of data. Pass gate transistors may be used as shown in FIG. 1 to gate data from a bit line true (BLT, FIG. 1 ) and a bit line complement (BLC, FIG. 1 ) to the cross coupled inverters.

In block 406 , circuitry determines, during a write, whether the first inverter or the second inverter must be overcome to write data into the cross coupled inverters. If it is determined that the first inverter must be overcome, in block 408 a supply voltage connected to the first inverter is reduced, making the first inverter easier to overcome. If it is determined in block 406 that the second inverter is to be overcome, then in block 410 a supply voltage connected to the second inverter is reduced, making the second inverter easier to overcome.

Block 412 ends method 400 .