Stacked-die electronics package with planar and three-dimensional inductor elements

This application is a divisional of and claims priority to U.S. application Ser. No. 11/457,409, entitled “A Stacked-Die Electronics Package with Planar and Three-Dimensional Inductor Elements,” filed Jul. 13, 2006, to issue as U.S. Pat. No. 7,932,590 on Apr. 26, 2011, the entire contents of which are hereby incorporated by reference.

The following U.S. patent application is relied upon and is incorporated by reference in its entirety in this application: U.S. patent application Ser. No. 11/456,685 filed Jul. 11, 2006.

The invention relates to an integrated circuit package, and more particularly, to incorporating passive components on a back side of a substrate having a fabricated integrated circuit device.

As electronic packages increase in both required functionality and the number of functions an electronic package is expected to perform, passive components are frequently needed to accomplish specific circuit tuning. Circuit tuning either adds tunable characteristics to the package or enables the package to perform properly. Enabling proper performance is especially required in many radio-frequency (RF) applications. For example, high-Q inductors are frequently needed in RF applications.

Adding discrete passive components to electronic packages typically results in an increase in both the size and weight of the package. These increases counter contemporary goals of increased portability and miniaturization. Adding discrete passive components in electronic packages also requires a dedicated production line, frequently including surface mounting equipment and added process setups. The added equipment and processes increase both capital investment and assembly lead-time, resulting in higher product costs.

Currently, these problems are being addressed by fabricating passive components, (e.g., inductors, capacitors, and resistors) over the active circuitry of an integrated circuit device. Integrating passive components requires various fabrication methods such as thin-film, photolithographic, and plating processes. Vias are formed over a top passivation layer of an integrated circuit device thus allowing integrated passive components to connect to the underlying integrated circuitry elements.

Consequently, current solutions for adding passive components to an integrated circuit device require custom-designed contact via openings to be at the top passivation layer for each product device. If a product is not initially designed to accept passive components, they cannot be simply added to the device. Therefore, what is need is a simple, inexpensive, and reliable means to add passive components to any integrated circuit without requiring, for example, custom designed contact vias or precise photolithography.

In an exemplary embodiment, the present invention is an integrated circuit device with a first substrate and a second substrate. The first substrate has a front side having one or more integrated circuit devices and a plurality of bond pads fabricated on its surface. The second substrate has a smaller area than the first substrate. The front side of the second substrate has one or more integrated circuit devices fabricated on its surface. At least one passive component is fabricated onto a back side of the second substrate. An electrical conductor allows electrical communications between the at least one passive component of the second substrate and at least one of the one or more integrated circuit devices of the first substrate.

In another exemplary embodiment, the present invention is an integrated circuit device with a first substrate and a second substrate. The first substrate has a front side with one or more integrated circuit devices and a plurality of bond pads fabricated on its surface. The second substrate has a smaller area than the first substrate. A front side of the second substrate has one or more integrated circuit devices fabricated on its surface. A first portion of at least one passive component is fabricated onto a back side of the second substrate. A second portion of at least one passive component is fabricated onto the front side of the first substrate, the second portion of the at least one passive component is formed so as to mirror the first portion. An electrical conductor allows electrical communications between the two portions of the at least one passive component.

In another exemplary embodiment, the present invention is a method of forming one or more passive components on a plurality of substrates. The method includes selecting a first substrate and a second substrate such that an area of the second substrate is less than an area of the first substrate, forming at least one integrated circuit on a front side of each of the first and second substrates, forming a plurality of bond pads on the front side of the first substrate, and forming a photoresist layer over a back side of the second substrate. The photoresist layer is then patterned and etched to form one or more passive component structures on the back side of the second substrate. The etched areas are filled with a metal and the one or more passive component structures are electrically bonded to selected ones of the plurality of bond pads.

In another exemplary embodiment, the present invention is a method of forming one or more passive components on a plurality of substrates where the method includes selecting a first substrate and a second substrate such that an area of the second substrate is less than an area of the first substrate, forming at least one integrated circuit on a front side of each of the first and second substrates, and forming a plurality of bond pads on the front side of the first substrate. A first portion of at least one passive component structure is formed on a back side of the second substrate. A second portion of at least one passive component structure is formed over the at least one integrated circuit on the front side of the first substrate where the second portion being a mirror image of the first portion. The first and second portions of the at least one passive component structure are then electrically bonded.

FIG. 1 is an isometric drawing of a passive element fabricated on a back side of an integrated circuit substrate in accordance with an exemplary embodiment of the present invention.

FIG. 2 illustrates integrated circuit dice fabricated in accordance with an exemplary method of the present invention and mounted in a ball grid array (BGA) package.

FIG. 3A illustrates integrated circuit dice fabricated in accordance with another exemplary method of the present invention and mounted in a ball grid array (BGA) package.

FIG. 3B is a detail drawing of an inductor formed in portions on different integrated circuit dice.

FIGS. 4A-4F are exemplary fabrication steps of an integrated circuit device produced in accordance with the present invention.

In FIG. 1 , an integrated circuit die 100 includes a substrate 101 having a front side 103 and a back side 105 . In a specific exemplary embodiment, the substrate 101 is portion of a silicon wafer. However, a skilled artisan will recognize that other semiconducting and non-semiconducting materials may be used instead of silicon for the substrate 101 . Other semiconducting materials include, for example, elemental semiconductors such as germanium, compound semiconductors such as group III-V, and II-VI materials, and semiconducting alloys (e.g., Al x Ga 1-x As, HG 1-x CD x Te). Additionally, non-semiconducting materials such as, for example, a polyethylene-terephthalate (PET) substrate deposited with silicon dioxide or a quartz photomask, each of which may be deposited with polysilicon followed by an excimer laser annealing (EDA) anneal step.

On the back side 105 of the substrate 101 , one or more passive components are formed. In this exemplary embodiment, a large single inductor 107 is formed. The inductor 107 terminates with a bond pad 109 on either end. Techniques disclosed herein apply readily to various types of passive components (e.g., inductors, resistors, capacitors, etc.). The passive components may be fabricated individually or in various combinations and with varying sizes. FIG. 1 therefore should be viewed as merely illustrative only of a generalized concept to be described in greater detail below.

With reference to FIG. 2 , a stacked-die ball grid array (BGA) package 200 includes a BGA substrate 201 and a plurality of BGA balls 203 . The BGA package type is generally known in the art. Mounted to the BGA substrate 201 is a first integrated circuit die 207 fabricated in accordance with methods known in the art. There is a plurality of contact vias 211 fabricated on the front side of the first integrated circuit die 207 .

A second integrated circuit die 209 fabricated in accordance with an exemplary embodiment of the present invention is mounted on top of the first integrated circuit die 207 . The first integrated circuit die is mounted to the BGA substrate with a first adhesive 202 . The second integrated circuit die 209 is mounted to the front side of the first integrated circuit die with a second adhesive 204 . The first and second adhesives 202 , 204 may be, for example, various types of electrically or non-electrically-conductive tape or epoxy.

One or more passive components 213 are fabricated on the back side of the second integrated circuit die 209 . Each of the one or more passive components 213 has an associated plurality of passive component bond pads 215 . The plurality of passive component bond pads 215 is also fabricated on the back side of the second integrated circuit die 209 . In a specific exemplary embodiment, the one or more passive components 213 is an inductor. Each inductor will therefore have at least two associated bond pads. If an electrically-conductive tape or epoxy is used for the second adhesive 204 , it must be insulated from the one or more passive components 213 and the associated plurality of passive component bond pads 215 so as to not electrically short either the components or pads.

Electrical connections are made from the one or more passive components 213 through the plurality of passive component bond pads 215 to the plurality of contact vias 211 . Electrical communication occurs between the one or more passive components 213 on the second integrated circuit die 209 and the plurality of contact vias 211 on the first integrated circuit die 211 through, for example, conductive epoxy, solder, conductive polymers, metal-to-metal bonding, etc.

Integrated circuit devices (not shown) are fabricated on the front side of each the first and second integrated circuit dice 207 , 209 . A plurality of bond wires 215 connect the front side integrated circuit devices to the BGA substrate 201 . The BGA substrate 201 and the integrated circuit dice 207 , 209 are protected with an encapsulant 219 .

In FIG. 3A , a stacked-die ball grid array (BGA) package 300 includes a first integrated circuit die 301 and a second integrated circuit die 303 . The first and second integrated circuit dice 301 , 303 each are fabricated with a portion of an inductor 305 , 307 . An inductor first portion 307 is fabricated on the front side of the first integrated circuit die 301 . An inductor second portion 305 is fabricated on the back side of the second integrated circuit die 303 . Details of exemplary techniques for fabricating the inductor portions 305 , 307 are disclosed below.

Mounting the first and second integrated circuit dice 301 , 303 brings the two inductor portions 305 , 307 in proximity to each other. An interconnecting material 309 forms an electrical connection between the two portions 305 , 307 of the inductor. Thus, a complete inductor is formed. The interconnecting material may be comprised of, for example, solder, metal-to-metal bonding, electrically-conductive polymer, or various other bonding techniques known in the art.

With reference to FIG. 3B , a formed inductor 350 is shown independent of the first and second integrated circuit dice 301 , 303 ( FIG. 3A ) to enhance clarity. The inductor first portion 305 is formed into the back side of the second integrated circuit die 303 (not shown) to mirror the inductor second portion 307 formed into the front side of the first integrated circuit die 301 (not shown). The interconnecting material 309 electrically connects the two inductor portions 305 , 307 together. One of skill in the art will recognize that the inductance value of the formed inductor 350 may be tuned depending upon a choice of adhesive 204 ( FIGS. 2 and 3A ) or other material selected for adhering the first and second integrated circuit dice 301 , 303 . Fabrication techniques for forming the inductor portions 305 , 307 are described below.

Exemplary fabrication steps for producing integrated circuit dice according to various embodiments of the present invention are presented graphically with reference to FIGS. 4A-4F . Using the techniques disclosed, integrated passive components may be readily produced using, for example, thin-film and plating techniques on the back side of a substrate (such as, for example, a silicon wafer). The substrate is then singulated into individual dice. An integrated circuit device is formed using traditional fabrication techniques on a front side of the substrate. Integrated passive components are then fabricated on the back side of the substrate. (In the case of an inductor fabricated on the front side of an integrated circuit die (e.g., the inductor first portion 307 , FIGS. 3A and 3B ), process steps are nearly identical and will be referenced as needed.)

In FIG. 4A , the substrate 401 has integrated circuit devices 403 fabricated upon the front side of the substrate 401 . The integrated circuit devices 403 are optionally covered with a temporary coating 405 . The temporary coating 405 protects the integrated circuit devices 403 for later processing steps which occur on the back side of the substrate 401 . The temporary coating 405 may be, for example, an organic or metallic coating (e.g., photoresist or a deposited or sputtered metal layer). (A temporary coating may not be needed if fabricating an inductor first portion on the front side of a die. Alternatively, a nitride or other dielectric film passivation layer may be added over the integrated circuit components prior to fabricating the inductor.)

In FIG. 4B , an optional dielectric material 407 is formed on the back side of the substrate 401 . The optional dielectric material may be either an organic or inorganic material. In a specific exemplary embodiment, the optional dielectric material 407 is a high-k dielectric material (e.g., zirconium-doped tantalum oxide, zirconium oxide, tantalum pentoxide, etc.). A high-k dielectric layer increases the Q-factor of an inductor. (The nitride or other dielectric film passivation layer disclosed above may be used as the optional dielectric material 407 if fabricating an inductor first portion on the front side of a die.)

With reference to FIG. 4C , a metal seed layer 409 is applied to either the back side of the substrate 401 or to the optional dielectric material 407 . The metal seed layer 409 forms a seed metal layer for additional layers. The metal seed layer 409 may be, for example, an electrolytically plated metal layers such as a titanium-tungsten-copper (TiW—Cu) layer. Skilled artisans will recognize that other metals may be selected. The metal seed layer 409 is then coated with photoresist. Various passive components may be patterned and etched leaving an etched photoresist layer 411 .

In FIG. 4D , a metal deposition 413 deposits metal into the open areas in the etched photoresist layer 411 thus forming a metal structure. The metal deposition 413 may be, for example, an electroplated layer comprised substantially of copper. Other techniques for forming one or more metal layers, for example, sputtering, may also be used. Additionally, other metals may be chosen so as to affect electrical characteristics of the passive component. For example, a metal having low conductivity may be used for forming resistive elements. Also, a combination of various metal types or metal alloys may be used in different geometric areas. A skilled artisan will recognize that certain types of metal may not require the metal seed layer 409 . In these cases, a patterned photoresist 411 may be applied directly to the back side of the substrate 401 and metal applied (e.g., deposited, sputtered, etc.) without a need for either the optional dielectric material 407 or the metal seed layer 409 . The choice of layers is dependent upon factors such as metal choice and metal-forming methods employed.

In FIG. 4E , the photoresist layer 411 may be stripped and exposed portions of the metal seed layer 409 , if used, are etched. Alternatively, the photoresist layer 411 may simply be left in place. If present, exposed portions of the optional dielectric material 407 are also removed. The temporary coating 405 ( FIGS. 4A-4E ) is removed as illustrated in FIG. 4F .

All fabrication operations disclosed herein may be carried out at the substrate (e.g., wafer) level prior to singulation of individual dice formed before package assembly. Electrical connections can be achieved by joining appropriate areas with, for example, solder, conductive polymer, or metal-to-metal bonding processes. An optional polymer material, such as epoxy or acrylic, can be used to fill any gaps between the individual die and the substrate of the packaging device to assist in further anchoring the integrated circuit device to the package substrate. The integrated circuit device will then undergo a standard wire bonding process to connect bond pads on the individual die to the package substrate.

In the foregoing specification, the present invention has been described with reference to specific embodiments thereof. It will, however, be evident to a skilled artisan that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, skilled artisans will appreciate that embodiments of the present invention may be readily used in various types of semiconductor packaging such as Quad Flat-Pack No-Lead (QFN), Dual Flat-Pack No-Lead (DFN), QTAPP® (thin array plastic package), ULGA® (ultra-thin land grid array), BCC® (bumped chip carrier), or other package types. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.