Application initiated tracing of its operation beginning with reset

This application claims priority under 35 U.S.C. 119(e)(1) to U.S. Provisional Application No. 61/309,645 filed Mar. 2, 2010.

The technical field of this invention is trace upon system reset.

Trace of program and system activity currently uses high speed application interfaces available as part of the functional capability of a System On Chip (SOC). It desirable that these interfaces provide trace capability from release of a warm reset.

This invention disables high speed interfaces for trace upon a cold reset. After release of the cold reset, application code enables trace using a register that is cleared only by a cold reset. The register value is not changed by warm reset. Once trace is enabled the application code initiates a warm reset. The high speed application interface then begins to move trace data through the high speed interface as it is generated.

This invention permits operation of an application to be observed from the release of warm reset without an emulator or test equipment connected to the application.

This invention includes a state machine entering a first state upon cold reset of the data processing system. Trace information collection and trace information export are prohibited in the first state. The state machine transits from said first state to a second state upon a change in a predetermined bit to a first state. Direct memory access setup is enabled in the second state. The state machine transits from the second state to a third state upon set up of the direct memory access. Trace information collection is enabled in the third state. The state machine transits from the third state to a fourth state upon a direct memory access request corresponding to the direct memory access setup in the second state. Trace data export via direct memory access from the trace collection unit is enabled in the fourth state.

The state machine additionally initiates a warm reset of the central processing unit upon entry into the second state.

The change in the predetermined bit state occurs via a memory mapped write to a predetermined register.

The state machine additionally enables trace information collection in the fourth state.

The state machine transits from the fourth state to the first state upon a change in a predetermined bit to an opposite second state.

These and other aspects of this invention are illustrated in the drawings, in which:

FIG. 1 is a block diagram of an example System On Chip (SOC) to which this invention is applicable; and

FIG. 2 is a state diagram of operation of one embodiment of this invention.

In a system where debug is desired, it is often desirable to collect information about system operation with hardware monitors of central processing units (CPUs), direct memory access (DMA) units and other units. The information generated by these units may be merged into a single stream of instrumentation data and exported using as trace data using a functional interface such as USB3, Gigabit Ethernet, Rapid IO, Aurora, or others. This invention activates the trace function with the execution of application code with the tracing system activity including system activity following a system reset.

FIG. 1 illustrates typical SOC 100 using this invention. As indicated by its name SOC 100 is fabricated upon a single integrated circuit (chip). SOC 100 includes one or more central processing units (CPUs) 110 providing program controlled data processing operations. CPUs 110 are connected to various input/output (I/O) peripherals via an interconnection fabric 140 . The example of FIG. 1 illustrates these I/O peripherals include Universal Serial Port 3 (USB3) 151 , Gigabit Ethernet 152 , Rapid I/O 153 and other interfaces 154 . Interconnect fabric 140 includes at least one direct memory access (DMA) unit 145 . SOC 100 includes other connections 155 to Interconnect Fabric 140 . Trace collection unit 130 collects trace information from one or more areas of SOC 100 in a manner known in the art, places this trace information in an internal buffer or FIFO and may output trace information via Interconnect Fabric 140 and one of the I/O peripherals. This process is aided by connection to DMAs 145 . Trace collection unit 130 is controlled via an enable signal by debug control logic 120 . Debug control logic 120 receives a cold reset signal and supplies a warm reset signal CPUs 110 . Debug control logic 120 includes memory mapped register 125 used in a manner described below. FIG. 1 does not illustrate all memory read/write connections for clarity.

In this invention a cold reset of SOC 100 establishes an operating mode where the application manages the export of trace data, without the aid of an external Debug and Test Controller (DTC). Following this cold reset:

Trace collection may or may not be enabled;

Transfer of trace information from the collection to an exporting interface is disabled; and

The application code may enable the collection of trace data and the export of trace data via a high speed interface.

Subsequent to or concurrent with enabling trace data collection, the application code initiates a CPU warm reset. The reset does not affect the register values controlling the collection of trace and the export of trace data via the high speed interface. These register values may be stored in memory mapped register 125 . This enables collection and export of trace data from the release of warm reset. A subsequent cold reset reestablishes the state described above. A memory mapped register 125 bit write both initiates the collection of trace data and sets up a DMA transfer of trace data from trace collection unit 130 to the high speed interface.

FIG. 2 illustrates the states of a state machine implementing this invention. The preferred embodiment includes state machine 200 within debug control logic 130 . A cold reset initializes state machine 200 to state “00” 201 . A subsequent write to a predetermined register bit trace_from_reset (set_trace_from_reset) in memory mapped register 125 causes a transition to state “10” 201 . This is the memory mapped register bit noted above. If this write does not occur (˜set_trace_reset), state machine 200 remains in state “00” 201 .

State machine 200 enters state “10” 202 following set_trace_from_reset. State “10” 202 causes a warm reset of CPUs 110 and initiates setup of a DMA transfer from Trace Collection unit 130 . This set up is later used for trace information movement.

State machine 200 automatically moves from state “10” 202 to state “11” 203 following the DMA transfer setup. State machine 200 waits in state “11” 203 until the DMA requests data from Trace Collection unit 130 . Trace Collection unit 130 may not have any data yet available. State machine 200 transitions to state “01” 203 when DMA request (DMA_req) occurs. If this DMA request does not occur (˜DMA_req), state machine 200 remains in state “11” 203 . Trace collection is enabled in state “01” 201 and in state “11” 203 via the ena signal ( FIG. 1 ).

State machine 200 enables output of trace data according to the previously set up DMA request. FIG. 1 illustrates trace collection unit 130 communicating with DMA unit 145 via request (req) and acknowledge (ack) lines. Trace information is them output from trace collection unit 130 via interconnect fabric 140 and one or more of the I/O peripherals 151 , 152 , 153 and 154 .

State machine 200 remains in state “01” as long as the trace_from_reset register bit in memory mapped register 125 is a logic 1 (set_trace_reset). State machine 200 transitions to initial state “00” 201 when the trace_from_reset register bit is no longer logic 1 (˜set_trace_reset). This bit change is accomplished via a memory mapped write to register 125 the same as the previous transition of this register bit.

This function may be implemented many other ways. The architecture shown in FIG. 1 is abstract and represents the numerous ways of implementing a typical SOC architecture.