Inventor
Gary L. Swoboda
Inventor
Sugar Land, TX, US
Overview
Patents· 232 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing47%
G01RMeasuring electric variables29%
H04LTransmission of digital information, e.g. telegraphic communication10%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
H03KPulse technique1%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%
Y02TClimate change mitigation technologies related to transportation1%
G05BControl or regulating systems in general0%
G11CStatic stores0%
PatentTitleYear
10,955,471Operating state machine controllers after powering, decoupling, monitoring, coupling communications202110,649,029TCKC/TMSC counter, gating circuitry for selection, deselection, technology specific outputs2020RE047864Series equivalent scans across multiple scan topologies202010,539,594Detecting power supply sag in an integrated circuit202010,438,023Pipeline processor data and attribute register, secure emulation logic, gating201910,371,748Monitoring communication link in powered-up device for synchronization point sequence201910,101,391Adapter circuitry with link and system interfaces to core circuitry201810,060,956Detecting power supply sag in an integrated circuit201810,054,638TCK, TMS(C) clock, gating circuitry providing selection and deselection outputs201810,048,314Scan path only one-bit scan register when component not selected201810,025,955Pipeline processor execution stages, secure emulation logic, gating debug/profile output20189,977,079Operating two tap system after detecting shared bus synchronization sequence20189,952,285Adapter circuitry with global bypass register, legacy test data, multiplexer20189,933,484Taps with TO-T2, T4 classes with, without topology selection logic20189,903,914'Target system recognizing synchronization point sequence on mode select input'20189,903,912'Status register between test data I/O of scan port SUT'20189,784,792'Taps of different scan classes with, without topology selection logic'20179,710,349'Storing first computer trace information in memory of second computer'20179,684,583'Trace data export to remote memory using memory mapped write transactions'20179,639,447'Trace data export to remote memory using remotely generated reads'20179,633,213'Secure emulation logic between page attribute table and test interface'20179,612,283'Blocking the effects of scan chain testing upon a change in scan chain topology'20179,557,355'Detecting power supply sag in an integrated circuit'20179,536,025'Transmitting LSB timestamp datum in parallel and MSB in series'20179,529,045'Taps with class T0-T2, T4 capabilities and topology selection logic'20169,523,738'TCK/TMS(C) counter circuitry with third, fourth count and reset outputs'20169,497,097'Inserting sequence numbers into data blocks merged from data streams'20169,494,648'Comparator with load signal output connected to timestamp value register'2016RE046193'Distributed power control for controlling power consumption based on detected activity of logic blocks'20169,423,458'Transporting ordered test data, mode select, ready, precharge packet bits'20169,423,459'Taps with class T0-T2 and T3, T4(W), and T5(W) capabilities'20169,395,413'Blocking the effects of scan chain testing upon a change in scan chain topology'20169,342,468'Memory time stamp register external to first and second processors'20169,310,434'Scan topology discovery in target systems'20169,285,426'Blocking the effects of scan chain testing upon a change in scan chain topology'20169,267,990'CLK/TMS counter having reset output coupled to fourth count output'20169,239,748'Comparator circuitry coupled to first, second time stamp overlap bits'20169,222,980'IC test circuitry and adapter with data transport control register'20159,194,910'Class T0-T2 and T4 TAPS with, without topology selection logic'20159,189,354'Pseudo dedicated debug port with an application interface'20159,170,889'Recovery from the loss of synchronization with finite state machines'20159,157,958'Blocking the effects of scan chain testing upon a change in scan chain topology'20159,123,404'Self clocking for data extraction'20159,116,207'IC gating selection on first/second and deselection on second/third counts'20159,083,623'Inserting source, sequence numbers into data stream from separate sources'20159,063,197'Blocking the effects of scan chain testing upon a change in scan chain topology'20159,032,265'IC test adapter circuitry having scan control register bits'20159,009,554'IC class T0-T2 taps with and without topology selection logic'20159,009,551'Adapter circuitry resetting scan test logic to mandatory feature set'20158,984,319'Adapter power up circuitry forcing tap states and decoupling tap'20158,966,647'Comparing central time stamp bits from bus and client circuitry'20158,938,651'Blocking the effects of scan chain testing upon a change in scan chain topology'20158,924,767'Minimizing the use of chip routing resources when using timestamped instrumentation data by transmitting the most significant bits of the timestamp in series and transmitting the least significant bits of the timestamp in parallel'20148,880,926'Counter/gating producing technology specific function outputs from TCK and TMS(C)'20148,881,114'Stored program writing stall information when a processor stalls waiting for another processor'20148,874,982'Test circuit adapter circuitry having a link control register'20148,868,799'Trace data transfer system having burst and minimum threshold inputs'20148,826,088'Scan topology discovery in target systems'20148,707,118'Data, mode and ready bit packets on bidirectional control/data leads'20148,656,234'Test port connected to master output of override selection logic'20148,631,289'Scan topology discovery in target systems'20148,627,145'High volume recording of instrumentation data varying instrumentation volumes to prevent data loss'20148,607,088'Synchronizing remote devices with synchronization sequence on JTAG control lead'20138,589,746'Bidirectional clock, data, and control to functional and test circuitry'20138,543,875'Moving third tap controller from exit2-DR state to pause-DR state'20138,522,093'Advanced/enhanced protocol circuitry connected to TCK, TMS, and topology circuitry'20138,473,920'Application initiated tracing of its operation beginning with reset'20138,464,111'Select, override and master override controlling multiplexing TDI and TDO'20138,458,505'Adapter and scan test logic synchronizing from idle state'20138,384,420'Preventing hangs in a system with synchronized operation using stalls'20138,375,366'Embedding event information in the timing stream'20138,359,502'TDI multiplexer gating controlled by override selection logic'20138,352,816'Adapter leads connected to test circuitry and third leads set'20138,341,474'Moving all TAP controllers through update-IR state after selecting individual TAPs'20128,341,471'Apparatus and method for synchronization within systems having modules processing a clock signal at different rates'20128,266,486'Preventing erroneous operation in a system which may enable unsupported features'20128,261,143'Select signal and component override signal controlling multiplexing TDI/TDO'20128,255,749'Ascertaining configuration by storing data signals in a topology register'20128,225,126'Adaptor detecting sequence on TMS and coupling TAP to TCK'20128,219,863'TAP state count specifying advanced mode command and command data'20128,201,004'Entry/exit control to/from a low power state in a complex multi level memory system'20128,136,003'JTAG debug test system adapter with three sets of leads'20128,122,311'Apparatus and method for clock signal synchronization in JTAG testing in systems having selectable modules processing data signals at different rates'20128,112,668'Dynamic broadcast of configuration loads supporting multiple transfer formats'20128,095,840'Serial scan chain in a star configuration'20128,078,898'Synchronizing TAP controllers with sequence on TMS lead'20118,067,955'Preventing erroneous operation in a system where synchronized operation is required'20118,055,947'Comparing supplied and sampled link ID bits on TMS lead'20118,041,999'Effecting adapter commands upon sequential target system TAP states'20118,037,355'Powering up adapter and scan test logic TAP controllers'20117,992,064'Selecting a scan topology'20117,991,959'Visualizing contents and states of hierarchical storage systems'20117,992,065'Automatic scan format selection based on scan topology selection'20117,992,049'Monitoring of memory and external events'20117,984,348'Series equivalent scans across multiple scan topologies'20117,984,347'System and method for sharing a communications link between multiple communications protocols'20117,962,814'Mode selection based on special sequence of state machine states'20117,958,419'Entering a shift-DR state in one of star connected components'20117,924,050'Key based pin sharing selection'20117,919,986'Power up biasing in a system having multiple input biasing modes'20117,917,753'Transferring control between programs of different security levels'20117,900,109'BDX data in stable states'20117,890,316'Synchronizing on-chip data processor trace and timing information for export'20117,886,271'Embedding event information in the timing stream'20117,886,194'Event-generating instructions'20117,886,198'Method and system of identifying overlays used by a program'20117,884,641'Setting operating mode of an interface using multiple protocols'20117,809,987'Accepting link ID upon supplied and sampled bits matching'20107,802,149'Navigating trace data'20107,797,686'Behavior of trace in non-emulatable code'20107,793,152'Zero-bit scans defining command window and control level'20107,788,642'Displaying cache information using mark-up techniques'20107,788,538'Event and stall selection'20107,783,925'Receiving control, data, and control segments of communication scan packets'20107,779,206'Cache inspection with inspection bypass feature'20107,779,321'Entering command based on number of states in advanced mode'20107,761,762'Adapter implemented background data transfers while tap in non-scan state'20107,761,285'Data processing condition detector with table lookup'20107,747,901'Auxiliary link control commands'20107,739,453'Providing information associated with a cache'20107,739,669'Paced trace transmission'20107,721,263'Debug event instruction'20107,698,544'Automatic halting of a processor in debug mode due to reset'20107,681,084'TOD or time stamp inserted into trace recording stream'20107,676,697'Using a delay line to cancel clock insertion delays'20107,613,951'Scaled time trace'20097,607,047'Method and system of identifying overlays'20097,603,589'Method and system for debugging a software program'20097,603,521'Prioritizing caches having a common cache level'20097,593,841'Emulation export sequence with distributed control'20097,590,894'Method of translating system events into signals for activity monitoring'20097,590,912'Using a chip as a simulation engine'20097,590,893'Recording control point in trace receivers'20097,571,366'Sequential signals selecting mode and stopping transfers of interface adaptor'20097,561,596'Systems and methods for multiplexing and demultiplexing multiple data sources'20097,562,259'Distributed depth trace receiver'20097,555,681'Multi-port trace receiver'20097,555,682'Distributed width trace receiver'20097,552,360'Debug and test system with format select register circuitry'20097,519,497'Apparatus and method for state selectable trace stream generation'20097,519,111'Apparatus and method for providing system and test clock signals to an integrated circuit on a single pin'20097,464,311'Apparatus and method for device selective scans in data streaming test environment for a processing unit having multiple cores'20087,463,653'Apparatus and method for compression of the timing trace stream'20087,428,666'Apparatus and method for trace stream identification of a pipeline flattener secondary code flush following a return to primary code execution'20087,417,567'High speed data recording with input duty cycle distortion'20087,404,106'Apparatus and method for reporting program halts in an unprotected pipeline at non-interruptible points in code execution'20087,391,344'High speed data recording with input duty cycle distortion'20087,392,431'Emulation system with peripherals recording emulation frame when stop generated'20087,334,114'Real-time monitoring, alignment, and translation of CPU stalls or events'20087,325,169'Apparatus and method for trace stream identification of multiple target processor events'20087,318,017'Collecting and exporting on-chip data processor trace and timing information with differing collection and export formats'20087,318,176'Tracing program counter addresses using native program counter format and instruction count format'20087,315,808'Correlating on-chip data processor trace information for export'20087,310,749'Apparatus and method for trace stream identification of a processor debug halt signal'20077,299,386'Apparatus and method for detecting address characteristics for use with a trigger generation unit in a target processor'20077,274,313'High speed data recording with input duty cycle distortion'20077,237,151'Apparatus and method for trace stream identification of a processor reset'20077,225,365'Apparatus and method for identification of a new secondary code start point following a return from a secondary code execution'20077,209,058'Trace receiver data compression'20077,210,072'Apparatus and method for trace stream identification of a pipeline flattener primary code flush following initiation of an interrupt service routine'20077,206,734'Exporting on-chip data processor trace information with variable proportions of control and data'20077,113,902'Data processing condition detector with table lookup'20067,089,437'Apparatus for determining power consumed by a bus of a digital signal processor using counted number of logic state transitions on bus'20067,076,419'Using sign extension to compress on-chip data processor trace and timing information for export'20067,047,451'Tracing program counter addresses using native program counter format and instruction count format'20067,043,418'Synchronizing on-chip data processor trace and timing information for export'20067,020,600'Apparatus and method for improvement of communication between an emulator unit and a host device'20066,996,747'Program counter trace stack, access port, and serial scan path'20066,985,848'Obtaining and exporting on-chip data processor trace and timing information'20066,981,178'Separation of debug windows by IDS bit'20056,947,884'Scan interface with TDM feature for permitting signal overlay'20056,948,155'Little offset in multicycle event maintaining cycle accurate tracing of stop events'20056,931,636'Multiprocessor emulation support using dynamic linking'20056,928,403'Automatic detection of connectivity between an emulator and a target device'20056,920,416'Electronic systems testing employing embedded serial scan generator'20056,912,675'Using selective omission to compress on-chip data processor trace and timing information for export'20056,868,376'Debug bi-phase export and data recovery'20056,865,504'Apparatus and method for a reconfigurable pod interface for use with an emulator unit'20056,859,897'Range based detection of memory access'20056,836,882'Pipeline flattener for simplifying event detection during data processor debug operations'20046,836,757'Emulation system employing serial test port and alternative data transfer protocol'20046,820,051'Software emulation monitor employed with hardware suspend mode'20046,820,222'Apparatus and method for processor power measurement in a digital signal processor using trace data and simulation techniques'20046,795,879'Apparatus and method for wait state analysis in a digital signal processing system'20046,785,850'System and method for automatically configuring a debug system'20046,775,793'Data exchange system and method for processors'20046,760,866'Process of operating a processor with domains and clocks'20046,754,852'Debug trigger builder'20046,754,599'Debug output loosely coupled with processor block'20046,738,929'Dynamically configurable debug port for concurrent support of debug functions from multiple data processing cores'20046,725,391'Clock modes for a debug port with on the fly clock switching'20046,708,290'Configurable debug system with wire list walking'20046,704,895'Integrated circuit with emulation register in JTAG JAP'20046,671,665'Emulation system with search and identification of optional emulation peripherals'20036,647,511'Reconfigurable datapath for processor debug functions'20036,643,803'Emulation suspend mode with instruction jamming'20036,606,590'Emulation system with address comparison unit and data comparison unit ownership arbitration'20036,567,933'Emulation suspension mode with stop mode extension'20036,564,339'Emulation suspension mode handling multiple stops and starts'20036,557,116'Emulation suspension mode with frame controlled resource access'20036,553,513'Emulation suspend mode with differing response to differing classes of interrupts'20036,545,549'Remotely controllable phase locked loop clock circuit'20036,546,505'Processor condition sensing circuits, systems and methods'20036,539,497'IC with selectively applied functional and test clocks'20036,522,985'Emulation devices, systems and methods utilizing state machines'20036,388,533'Programmable ring oscillator'20026,349,392'Devices, systems and methods for mode driven stops'20026,324,684'Processor having real-time execution control for debug functions without a debug monitor'20016,085,336'Data processing devices, systems and methods with mode driven stops'20006,038,622'Peripheral access with synchronization feature'20006,032,268'Processor condition sensing circuits, systems and methods'20005,952,863'Circuit and method for generating non-overlapping clock signals for an integrated circuit'19995,937,179'Integrated circuit design system with shared hardware accelerator and processes of designing integrated circuits'19995,922,070'Pipelined data processing including program counter recycling'19995,919,255'Method and apparatus for processing an interrupt'19995,903,746'Apparatus and method for automatically sequencing clocks in a data processing system when entering or leaving a low power state'19995,884,023'Method for testing an integrated circuit with user definable trace function'19995,841,670'Emulation devices, systems and methods with distributed control of clock domains'19985,828,824'Method for debugging an integrated circuit using extended operating modes'19985,805,792'Emulation devices, systems, and methods'19985,790,609'Apparatus for cleanly switching between various clock sources in a data processing system'19985,724,566'Pipelined data processing including interrupts'19985,684,721'Electronic systems and emulation and testing devices, cables, systems and methods'19975,657,328'Scan design with expanded access capability'19975,621,651'Emulation devices, systems and methods with distributed control of test interfaces in clock domains'19975,564,028'Pipelined data processing including instruction trace'19965,551,050'System and method using synchronized processors to perform real time internal monitoring of a data processing device'19965,535,331'Processor condition sensing circuits, systems and methods'19965,329,471'Emulation devices, systems and methods utilizing state machines'19944,514,801'Microcomputer with table-read and table-write instructions'19854,514,805'Interrupt operation in systems emulator mode for microcomputer'19854,450,521'Digital processor or microcomputer using peripheral control circuitry to provide multiple memory configurations and offset addressing capability'1984Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1984–2021Patents assigned to TEXAS INSTRUMENTS INC (228)· patent assignee history
1984–1985Based in Austin, TX, US· patent location history
1994–2021Based in Sugar Land, TX, US· patent location history
1998–2015Based in Sugarland, TX, US· patent location history
2011–2015Patents assigned to SWOBODA GARY L (24)· patent assignee history
2011Based in Parker, TX, US· patent location history
2012–2013Patents assigned to MCGOWAN ROBERT A (2)· patent assignee history
2013–2014Patents assigned to AGARWALA MANISHA (2)· patent assignee history
2013–2014Patents assigned to SOHM OLIVER P (2)· patent assignee history
2015Based in Sugar Lane, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 228 | 1984–2021 |
| SWOBODA GARY Lself | 24 | 2011–2015 |
| AGARWALA MANISHA | 2 | 2013–2014 |
| MCGOWAN ROBERT A | 2 | 2012–2013 |
| SOHM OLIVER P | 2 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sugar Land, Texas, US | 158 | 1994–2021 |
| Sugarland, Texas, US | 67 | 1998–2015 |
| Austin, Texas, US | 3 | 1984–1985 |
| Sugar Lane, Texas, US | 2 | 2015 |
| Parker, Texas, US | 1 | 2011 |