OP-AMP sharing with input and output reset

The present application claims priority to U.S. Provisional Application Ser. No. 61/289,956, filed Dec. 23, 2009, incorporated herein by reference.

This disclosure relates generally to electronic circuits, and in particular, but not exclusively, is related to Switched Capacitor (SC) gain amplifiers and Pipelined Algorithmic Analog to Digital Converters (ADC).

Due to their relatively simple implementation and low cost in the application of intermediate speed and resolution, Pipelined Algorithmic Analog-to-Digital Converters (ADC) are found in various applications, including image sensors, communication and television. A component found at each stage of a Pipelined Algorithmic ADC is an operational amplifier (OP-AMP). The majority of the power consumption of a pipeline ADC is in the OP-AMPs, so OP-AMP sharing is desirable to minimize the number of OP-AMPs used. However, without the use of a reset phase in an OP-AMP sharing structure to eliminate residual signals from prior phases, amplification during a phase may be affected by a residue from a prior phase stored in capacitances of the OP-AMP input pair. This problem becomes more pronounced when a large or full-swing input signal exists, for example, when an image sensor pixel is exposed to bright light, resulting in a white pixel, that may either be converted improperly or may affect conversion of a following pixel. This is an example of a phenomenon known as the memory effect.

One method to reduce the occurrence of the memory effect in Pipeline ADCs is to insert a charge-reset phase between clock cycles. However, this has the effect of reducing the clock speed of the Pipeline ADC.

An operational amplifier with two pairs of differential inputs for use with an input switch capacitor network. The operational amplifier has reset devices for resetting the second pair of differential inputs while amplifying the first pair of differential inputs, and for resetting the first pair of differential inputs while amplifying the second pair of differential inputs for reducing memory effect in electronic circuits. In an embodiment, the amplifier has an additional reset device for resetting the outputs during a prophase of amplifying the first pair of differential inputs and a prophase of amplifying the second pair of differential inputs.

In an embodiment, the operational amplifier has four inputs, a first and a second differential pairs, operational amplifier (OP-AMP) and outputs a single pair of differential output signals. Timing circuitry is provided for generating non-overlapping clocks. An input switched-capacitor (SC) network controlled by the non-overlapping clocks is configured such that the first pair of the differential input signals is amplified by the OP-AMP during a first phase, that the second pair of the differential input signals is amplified by the OP-AMP during a second phase. First input reset switch devices, coupled between signals of the first pair of differential input signals and a reference signal, and second input reset switch devices coupled between signals of the second pair of differential input signals and the reference signal, are provided to reset the amplifier inputs. In an embodiment, an additional reset device and signal is provided for resetting the amplifier output between amplification phases.

The embodiments are more fully appreciated in connection with the following detailed description taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout.

FIG. 1 illustrates the SC gain amplifier with OP-AMP sharing with input and output reset according to an embodiment of the present invention.

FIG. 2 illustrates the timing diagram of the SC gain amplifier and OP-AMP sharing with input and output reset according to an embodiment of the present invention.

FIG. 3 illustrates the schematics of two-stage OP-AMP according to an embodiment of the present invention.

An embodiment of the disclosed switched capacitor (SC) gain amplifier with OP-AMP sharing with input and output reset is described herein. In the following description numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc.

Rather than using OP-AMPs with one pair of differential inputs, the disclosed OP-AMP has two pairs of differential inputs, INP 0 -INN 0 and INP 1 -INN 1 , thereby allowing for input reset as well as output reset without having to insert a separate reset phase between clock cycles of the OP-AMP. If a reset phase is inserted between clock cycles of the OP-AMP, the operation of a functional block using said OP-AMP—such as a pipelined algorithmic ADC—may not be optimal because of the time required for a separate reset phase. Utilizing the disclosed OP-AMP in a pipelined algorithmic ADC may allow an increase in the operating clock speed of the pipeline ADC.

In the present amplifier, the outputs of an SC network and differential inputs of the OP-AMP are reset using switches 113 , 114 , 113 A, 114 A, that selectively couple a pair of differential inputs together and to to a reference signal VREFC. The output of the OP-AMP is reset with an output reset switch 116 which selectively couples the signals VON, VOP of the differential output together.

The SC network is coupled to the inputs of the OP-AMP, and has two capacitors 111 , 112 , 111 A, 112 A, 109 , 110 , 109 A, and 110 A coupled to each input of the SC network, and a pair of switches 101 , 102 , 103 , 104 , 105 , 106 , 107 , 108 , 101 A, 102 A, 103 A, 104 A, 105 A, 106 A, 107 A, 108 A coupled to each capacitor. Each pair of switches is controlled by one of two phase-clock signals, PH 1 and PH 2 as illustrated in FIG. 1 . The two phase-clock signals, PH 1 and PH 2 , are non-overlapping as is illustrated in FIG. 2 . Phase-clock signals PH 1 and PH 2 alternately sample differential input signals VIN and VIP into capacitors of the SC network in a first phase ( 220 ), and cause the amplifier to amplify the difference between the sampled differential input signals with the OP-AMP in a second phase ( 210 ). Similarly input signals VIN and VIP are sampled again into capacitors of the SC network in the second phase ( 210 ), and the difference between the sampled differential input signals is amplified by the OP-AMP in the following first phase ( 220 ), the first and second phases alternating. In both phases, gain is set by ratios of capacitances in the switched-capacitor network, such as ratios of capacitors 111 to 112 , and 111 A to 112 A in the second phase, and similarly by ratios of capacitors 109 to 110 and 109 A to 110 A in the first phase.

As can be seen in FIG. 3 with reference to FIG. 2 , the INP 0 -INN 0 differential signal pair from the SC network are amplified through differential pair 311 , 311 A and selected by selectors 313 , 313 A during the first phase ( 220 ) when PH 1 B is high, and the INP 1 -INN 1 differential signal pair are amplified by differential pair 314 , 314 A and enabled by selectors 316 , 316 A, during the second phase ( 210 ) when PH 2 B is high. Similarly, first differential pair reset devices 312 , 312 A act to reset intermediate nodes between pair 311 , 311 A and selectors 313 , 313 A during the second phase when PH 1 is high, and second differential pair reset devices 315 , 315 A act to reset intermediate nodes between pair 314 , 314 A and selectors 316 , 316 A during the first phase when PH 2 is high

Control signals PH 1 _ 0 and PH 2 _ 0 are also non-overlapping control signals, although PH 1 _ 0 overlaps PH 1 and PH 2 _ 0 overlaps PH 2 . Non-overlapping control signals PH 1 _ 0 and PH 2 _ 0 reset a pair of differential inputs of the OP-AMP during a phase when the OP-AMP is not amplifying the sampled differential input signals.

In the present embodiment, as seen in FIG. 2 , control signal PH 1 _ 0 is asserted when clock signal PH 1 is asserted, and PH 1 _ 0 is de-asserted before the falling edge of clock signal PH 1 . Similar logic can be applied to control signal PH 2 _ 0 and clock signal PH 2 . In other embodiments control signal PH 1 _ 0 may be asserted before the rising edge of clock signal PH 1 , and/or may be de-asserted after the falling edge of clock signal PH 1 , as long as control signal PH 1 _ 0 does not overlap clock signal PH 2 . Again, similar logic can be applied to control signal PH 2 _ 0 , which may be asserted before the rising edge of clock signal PH 2 , and/or may be de-asserted after the falling edge of clock signal PH 2 , as long as control signal PH 2 _ 0 is not asserted when clock PH 1 is asserted. During each clock cycle, each pair of differential inputs of the OP-AMP is reset once, and the differential output of the OP-AMP is reset twice. An OP-AMP with two pairs of differential inputs allows for the frequent reset of its input and output without increasing the clock period of the OP-AMP.

In more detail, FIG. 1 illustrates a SC gain amplifier with OP-AMP sharing with input and output reset. OP-AMP 115 has two differential input pairs, INP 0 and INN 0 and INP 1 and INN 1 . Note that since OP-AMP 115 is differential, only one side of the differential input pairs will be described. Each element in SC network coupled to a first differential input of OP-AMP 115 has a corresponding element coupled to a second differential input of OP-AMP 115 . The first and second differential inputs make up one differential input pair. For example, switch 101 couples differential output signal VON to differential input INP 0 of OP-AMP 115 , switch 101 A couples differential output signal VOP to differential input INN 0 of OP-AMP 115 . Similar logic can be applied to SC network elements 102 A thru 114 A.

Inputs INP 0 and INP 1 are connected to the SC subnetwork comprising switches 101 - 108 and capacitors 109 - 112 . Two switches are connected to each capacitor, with switches 101 and 102 coupled to capacitor 109 , switches 103 and 104 coupled to capacitor 110 , switches 105 and 106 coupled to capacitor 111 and switches 107 and 108 coupled to capacitors 112 , as shown in FIG. 1 . Switches 101 thru 108 are controlled by non-overlapping clocks PH 1 and PH 2 . Switches 113 and 114 connect either INP 0 and INP 1 respectively to reference signal VREFC to reset the signal. Switch 116 is coupled between the differential output, VON and VOP of OP-AMP 115 .

When a signal is asserted, a switch which is controlled by that signal is closed, when the signal is deasserted, the switch which is controlled by that signal is open. In the present embodiment, the disclosed switches are NMOS transistors, and it can be appreciated that clock signals PH 1 and PH 2 and control signals PH 1 _ 0 and PH 2 _ 0 are active-high signals. In other embodiments of the invention, the disclosed switches which comprise the SC network may be PMOS transistors, in which case, clock signals PH 1 and PH 2 , and control signals PH 1 _ 0 and PH 2 _ 0 are inverted to be active-low signals. In yet other embodiments of the present invention, the disclosed switches which comprise the SC network may be a combination of PMOS and NMOS transistors where clock signals which control the NMOS transistors are active-high and clock signals which control the PMOS transistors are active-low are used to obtain two non-overlapping phases for OP-AMP 115 .

A phase with clock signal PH 1 asserted and clock signal PH 2 deasserted is seen in time interval 210 in FIG. 2 . In this phase, switches 102 and 104 are closed, and input signal VIN is sampled and stored in capacitors 109 and 110 . During this phase, control signal PH 1 _ 0 is asserted, and the OP-AMP input INP 0 is reset with reference signal VREFC. Switches 105 and 107 are also closed, and OP-AMP 115 , output VON, is sampled at capacitor 111 , while a reference signal, REF_OUTN 1 is sampled at capacitor 112 . Capacitors 111 and 112 , along with OP-AMP 115 , form an SC gain amplifier having gain determined by a ratio of capacitance between capacitor 112 to capacitor 111 . In the same phase, input signal VIN is sampled at capacitors 109 and 110 . In the illustrated embodiment, control signal PH 1 _ 0 is de-asserted just before the falling edge of clock signal PH 1 . However, in other embodiments, control signal PH 1 _ 0 may be asserted before the rising edge of clock signal PH 1 , and/or de-asserted after the falling edge of clock signal PH 1 , as long as control signal PH 1 _ 0 is not asserted when clock signal PH 2 is asserted.

An alternate phase with clock signal PH 2 is asserted and clock signal PH 1 is deasserted as seen in time interval 220 in FIG. 2 , switches 106 and 108 are closed and input signal VIN is sampled and stored in capacitors 111 and 112 . During this time, control signal PH 2 _ 0 is asserted, and the OP-AMP input INP 1 is reset with reference signal VREFC. Switches 101 and 103 are also closed, signal VON is sampled at capacitor 109 and reference signal, REF_OUTN 0 is sampled at capacitor 110 . Capacitors 109 and 110 , along with OP-AMP 115 form an SC gain amplifier. The differential input INP 1 is reset with reference signal VREFC, while input signal VIN is sampled at capacitors 111 and 112 . In the present embodiment, control signal PH 2 _ 0 is de-asserted just before the falling edge of clock signal PH 2 . Similar logic can be applied to control signal PH 2 _ 0 , which may be asserted before the rising edge of clock signal PH 2 , and/or may be de-asserted after the falling edge of clock signal PH 2 , as long as control signal PH 2 _ 0 is not asserted when clock PH 1 is asserted.

Clock signals PH 1 and PH 2 as well as their complements PH 1 B and PH 2 B control OP-AMP 115 . A schematic showing representative circuitry of OP-AMP 115 can is illustrated in FIG. 3 . The differential output of OP-AMP 115 is selectively reset by switch 116 which is controlled by reset signal PH 12 _S. Reset signal PH 12 _S is pulsed at the rising edge of either clock signals PH 1 or PH 2 . The reset of the differential output signal at every rising edge of clock signals PH 1 and PH 2 is provided to reduce the output memory effect. The rising edge of reset signal may occur before the rising edge of either clock signals PH 1 or PH 2 .

FIG. 2 illustrates an example of the timing of clock signals and control signals used in the SC network. In FIG. 2 , the horizontal axis represents time and the vertical axis represents the amplitude of the signals. During time interval 210 , control signal PH 1 _ 0 is asserted and differential input pair INP 0 and INN 0 are reset with reference signal VREFC. Clock signal PH 1 is asserted, and clock signal PH 2 is de-asserted during this time interval, differential input pair INP 1 and INN 1 amplifies a signal sampled by capacitors 111 and 112 . Input signal VIN is sampled at capacitors 109 and 110 . Before the falling edge of clock signal PH 1 , control signal PH 1 _ 0 is deasserted. When clock signal PH 1 is de-asserted, time interval 230 begins, and during this time interval clock signals PH 1 and PH 2 , as well as control signals PH 1 _ 0 and PH 2 _ 0 are de-asserted, during this time, and none of the switches in the SC network are closed.

During time interval 220 , control signal PH 2 _ 0 is asserted and differential input pair INP 1 and INN 1 are reset with reference signal VREFC differential. Clock signal PH 2 is asserted, and clock signal PH 1 is de-asserted during this time interval, differential input pair INP 0 and INN 0 amplifies the signal sampled by capacitors 109 and 110 at time interval 210 . Input signal VIN is sampled at capacitors 111 and 112 . Before the falling edge of clock signal PH 2 , control signal PH 2 _ 0 is deasserted. When clock signal PH 2 is de-asserted, time interval 240 begins, and during the brief non-overlap interval clock signals PH 1 and PH 2 , as well as control signals PH 1 _ 0 and PH 2 _ 0 are de-asserted, and none of the switches in the SC network are closed.

As previously mentioned, control signal PH 1 _ 0 may be asserted before clock signal PH 1 is asserted, in this case, time interval 240 may be shortened, or may not exist at all. Control signal PH 1 _ 0 also may be de-asserted after the falling edge of clock signal PH 1 ; in this case, time interval 230 may be shortened, or may not exist at all, however some input offset error may be introduced by capacitive coupling associated with turning off these clocks if PH 1 _ 0 is not separate as illustrated. Similar logic may be applied to control signal PH 2 _ 0 .

FIG. 3 illustrates the OP-AMP, 115 as seen in FIG. 1 . OP-AMP 115 has two stages, telescopic OP-AMP stage 310 and common source OP-AMP stage 320 . Signals CMFB 1 and CMFB 2 are common mode feedback signals for the first and second stage, 310 and 320 respectively and cascode compensation is used for stability. Differential output signals VON 1 and VOP 1 are the output of telescopic OP-AMP 310 , and input of common source OP-AMP 320 . Differential output signals VON and VOP are the output of the common source OP-AMP 320 . Signals TCP, TCN, PB 1 , PB 2 , NB 1 and PB 1 _OUT are bias voltage signals.

Transistors 311 and 311 A form one differential input pair, INP 0 and INN 0 , while transistors 314 and 314 A form the second differential input pair, INP 1 and INN 1 . When PH 1 is asserted and PH 2 is deasserted, transistors 311 and 311 A are disconnected from the telescopic OP-AMP 310 and their drains are shorted via transistors 312 and 312 A respectively. When PH 2 is deasserted, locally inverted clock PH 2 B is asserted and transistors 314 and 314 A are connected through transistor 316 and 316 A to CP and CN respectively.

Recall in the previous discussion of FIG. 1 , when PH 1 is asserted, and PH 2 is deasserted, the differential input pair INP 0 and INN 0 are reset with reference signal VREFC. Transistors 312 and 312 A in FIG. 3 ensure that the drains of 311 and 311 A are reset to further reduce residual voltages from prior amplifer phases and cycles. The overlapping timing of complementary clock signals PH 1 B and PH 2 B ensure that at least one pair of differential input INP 0 and INN 0 or INP 1 and INN 1 is coupled to the telescopic OP-AMP 310 at all times.

When PH 2 is asserted and PH 1 is deasserted, transistors 314 and 314 A are disconnected from the telescopic OP-AMP 310 and the drains of transistors 314 and 314 A are shorted via transistors 315 and 315 A respectively. When PH 1 is deasserted, locally inverted clock PH 1 B is asserted and transistors 311 and 311 A are connected through transistors 313 and 313 A to telescopic OP-AMP 310 .

Recall in the previous discussion of FIG. 1 , when PH 2 is asserted, and PH 1 is deasserted, the differential input pair INP 1 and INN 1 are reset with reference signal VREFC. Transistors 315 and 315 A in FIG. 3 ensure that the drains of 314 and 314 A are reset to further reduce residual voltages remaining in the amplifier from prior amplifier phases and cycles.

The advantages of having two pairs of differential inputs include a reduction of power consumption. Most of the power consumed by a Pipeline ADC goes to the OP-AMP, and by time-sharing telescopic amplifier 310 and common source amplifier 320 , the overall power consumption of each stage of the Pipeline ADC can decrease. Transistors 313 , 313 A, 316 and 316 A ensure that at least one pair of differential inputs, INP 0 and INN 0 or INP 1 and INN 1 is coupled to the telescopic OP-AMP 310 at all times. Another advantage of having two pairs of differential inputs is that a pair of differential inputs can be reset without inserting a full reset phase between clock cycles.

The output of OP-AMP 115 is the differential pair VON, VOP, as previously mentioned in FIG. 1 . VON and VOP can be reset using switch 116 which is controlled by signal PH 12 _S. The signal PH 12 _S is pulsed at the rising edge of either PH 1 or PH 2 , and the frequent reset of this output signal may reduce the occurrence of memory effect in image sensors.

It can be appreciated that this disclosure can be applied to other SC circuits using different amplifiers, such as one-stage OP-AMP or OP-AMPs with PMOS input pairs instead of the NMOS pairs illustrated. In the present embodiment, the switches 101 - 108 and 113 and 114 in FIG. 1 which make up the SC network are shown as NMOS transistors. The switches which comprise the SC network could be PMOS transistors, or complimentary switches having a combination of NMOS and PMOS transistors.

While the illustrated OP-AMP has two pairs of differential inputs, it can be appreciated that the OP-AMP may have three, or four, or more pairs of differential inputs. One of the advantages of an OP-AMP with three or more pairs of differential inputs is that three or more stages of a Pipeline ADC may share a single OP-AMP, and therefore reduce the power consumption of the Pipeline ADC. In the case of an OP-AMP with three or more pairs of differential inputs, the SC network will also need to be expanded to accommodate the additional pairs of inputs.

The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the various embodiments. However, it will be apparent to one skilled in the art that specific details are not required in order to practice the embodiments as described. Thus, the foregoing descriptions of specific embodiments are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the embodiments to the precise forms disclosed; obviously, many modifications and variations are possible in view of the above teachings.