Semiconductor integrated circuit

This is a continuation of PCT International Application PCT/JP2010/002792 filed on Apr. 16, 2010, which claims priority to Japanese Patent Application No. 2009-104268 filed on Apr. 22, 2009. The disclosures of these applications including the specifications, the drawings, and the claims are hereby incorporated by reference in their entirety.

The present disclosure relates to semiconductor integrated circuits, and more specifically, relates to techniques for increasing accuracy of pattern dimensions of gate lines.

A gap between dimensions of lines and wavelength of exposure light is increasing as semiconductor integrated circuits become smaller. Thus, the semiconductor integrated circuits tend to be affected by diffracted light and coherent light from neighboring patterns, which results not only in poor reproduction of design patterns, but also in an increased possibility of a break or a short between neighboring patterns. Optical Proximity Correction (OPC) is known as a technique of reducing an effect of coherent light from neighboring patterns. OPC is a technique in which irregularities of line width due to space between lines are predicted, and patterns are corrected to compensate the irregularities, thereby making a final line width constant. However, the application of OPC may increase chip area because space between neighboring patterns is increased due to insertion of compensation patterns.

Patent Document 1 (U.S. Pat. No. 7,446,352) describes a technique of avoiding the effect of coherent light without using OPC. Patent Document 1 discloses a technique of configuring a logic cell by using only a one-dimensional pattern. The use of this technique does not only eliminate the need for OPC, but also allows easier application of a phase shift mask for a linear pattern. Thus, it is possible to reduce the effect of the diffracted light, and maximize contrast of a pattern.

However, if the technique disclosed in Patent Document 1 is used, a gate line is separated into segments at an arbitrary location. For example, in the case where a gate line is separated into segments at a location A as shown in FIG. 17 , it is not possible to completely avoid variations of the width of the gate line at a location B which is adjacent and opposite to the location A. Further, if a flip-flop or a latch is configured by only the linear gate lines disclosed in Patent Document 1 and gate lines allowing the separation at an arbitrary location, it reduces degree of freedom of the gate lines. Thus, two metal layers are used to complement the total wiring resources for achieving a circuit function. Thus, the cell height may be increased to ensure line tracks of the two metal layers in the cell. Further, yields may be reduced because of contact failure, since a double contact cannot be formed at a location where lines in adjacent layers intersect. Furthermore, another measure which considers EM (electromigration) is necessary to reduce the width of a power supply line. Therefore, in either case, a circuit area may be affected.

In view of this, it is an objective of the present disclosure to provide a semiconductor integrated circuit in which variations in dimensions between transistors are reduced and in which a circuit area is reduced.

A semiconductor integrated circuit according to one aspect of the present invention is a semiconductor integrated circuit having standard cells, wherein among the standard cells, a latch or a master slave flip-flop includes: a plurality of PMOS transistors formed on a substrate along a first direction such that a gate length direction of each of the PMOS transistors is parallel to the first direction; a plurality of NMOS transistors which are formed on the substrate along the first direction such that a gate length direction of each of the NMOS transistors is parallel to the first direction, and each of which is opposed to a corresponding one of the plurality of PMOS transistors in a second direction perpendicular to the first direction; and a plurality of gate lines which correspond to the plurality of PMOS transistors and the plurality of the NMOS transistors, and which are arranged parallel to each other and extend linearly along the second direction such that each of the gate lines passes through gate areas of the PMOS transistors and the NMOS transistors which correspond to each of the gate lines. According to the present disclosure, it is possible to reduce variations in dimensions between transistors, and possible to reduce a circuit area of a semiconductor integrated circuit.

FIG. 1 is an example layout of a semiconductor integrated circuit according to the first embodiment.

FIG. 2 is a drawing for explaining a circuit configuration of a latch circuit formed in the semiconductor integrated circuit shown in FIG. 1 .

FIG. 3 is a drawing for explaining a circuit configuration of a latch circuit formed in the semiconductor integrated circuit shown in FIG. 1 .

FIG. 4 is a drawing for explaining a plurality of PMOS transistors, a plurality of NMOS transistors, and a plurality of gate lines, shown in FIG. 1 .

FIG. 5 is an example layout of a semiconductor integrated circuit according to the first variation of the first embodiment.

FIG. 6 is a drawing for explaining a circuit configuration of a latch circuit formed in the semiconductor integrated circuit shown in FIG. 5 .

FIG. 7 is a drawing for explaining a circuit configuration of a latch circuit formed in the semiconductor integrated circuit shown in FIG. 5 .

FIG. 8 is an example layout of a semiconductor integrated circuit according to the second embodiment.

FIG. 9 is a drawing for explaining a plurality of PMOS transistors, a plurality of NMOS transistors, and a plurality of gate lines, shown in FIG. 8 .

FIG. 10 is a drawing for explaining a circuit configuration of a flip-flop circuit formed in the semiconductor integrated circuit shown in FIG. 8 .

FIG. 11 is a drawing for explaining a circuit configuration of a flip-flop circuit formed in the semiconductor integrated circuit shown in FIG. 8 .

FIG. 12 is a drawing for explaining a circuit configuration of a flip-flop circuit formed in the semiconductor integrated circuit shown in FIG. 8 .

FIG. 13 is an example layout of a semiconductor integrated circuit according to a variation of the second embodiment.

FIG. 14 is a drawing for explaining a plurality of PMOS transistors, a plurality of NMOS transistors, and a plurality of gate lines, shown in FIG. 13 .

FIG. 15 is a drawing for explaining a circuit configuration of a flip-flop circuit formed in the semiconductor integrated circuit shown in FIG. 13 .

FIG. 16 is a drawing for explaining a circuit configuration of a flip-flop circuit formed in the semiconductor integrated circuit shown in FIG. 13 .

FIG. 17 is a layout of a conventional semiconductor integrated circuit.

Embodiments will be described in detail hereinafter with reference to the drawings. In the drawings, like reference characters have been used to designate identical or equivalent elements, and explanation thereof is not repeated.

(First Embodiment)

FIG. 1 shows an example layout of a semiconductor integrated circuit according to the first embodiment. The semiconductor integrated circuit includes PMOS transistors P 101 , P 102 , . . . , P 108 , NMOS transistors N 101 , N 102 , . . . , N 108 , gate lines G 101 , G 102 , . . . , G 108 , and dummy gate lines GD 1 , GD 2 , . . . , GD 4 . Further, the semiconductor integrated circuit is provided with a plurality of lines (e.g., a power supply line LP, a ground line LG, input lines L 101 , L 102 , and an output line L 103 ) and a plurality of contacts. The power supply line LP and the ground line LG transmit a power supply voltage VDD and a ground voltage VSS, respectively. The input lines L 101 , L 102 transmit input signals Vin and VC, respectively. The output line L 103 transmits an output signal Vout. In FIG. 1 , lines L 11 and L 12 are shown as being transparent to facilitate understanding of the connection between the elements.

<Circuit Configuration>

The layout shown in FIG. 1 corresponds to the circuit configuration shown in FIG. 2 . A combinational circuit 11 includes the PMOS transistors P 101 , P 102 , . . . , P 104 , and NMOS transistors N 101 , N 102 , . . . , N 104 . Inverter circuits 12 , 13 , . . . , 15 include the PMOS transistors P 105 , P 106 , . . . , P 108 , respectively, and the NMOS transistors N 105 , N 106 , . . . , N 108 , respectively. The circuit configuration shown in FIG. 2 can be obtained by modifying the circuit configuration shown in FIG. 3 . Specifically, the combinational circuit 11 shown in FIG. 2 can be implemented by combining tri-state inverter circuits 16 , 17 , shown in FIG. 3 , together. That is, the semiconductor integrated circuit shown in FIG. 1 includes, as a standard cell, a latch circuit having the tri-state inverter circuits 16 , 17 and the inverter circuits 12 , 13 , . . . , 15 . According to the latch circuit, if the input signal VC transitions from a low level to a high level, an output (a control signal VC 1 ) of the inverter circuit 14 and an output (a control signal VC 2 ) of the inverter circuit 15 become a low level and a high level, respectively. As a result, an inverted signal of the input signal Vin is output as the output signal Vout. On the other hand, if the input signal VC transitions from a high level to a low level, an inverter loop is formed by the inverter circuit 12 and the tri-state inverter circuit 17 , and the logical level of the output signal Vout is maintained at the same logical level as before the transition of the input signal VC from a high level to a low level. The semiconductor integrated circuit shown in FIG. 1 may include not only the standard cell which functions as a latch circuit, but also other standard cells.

<Connection Between Elements>

Next, the connection between respective elements of the semiconductor integrated circuit shown in FIG. 1 will be briefly described. For example, the PMOS transistor P 101 shares, with the adjacent PMOS transistor P 102 , a P type diffusion region which serves as a source region for both transistors. The source region of the PMOS transistor P 101 (or the source region of the PMOS transistor P 102 ) is electrically connected to the power supply line LP via a contact. Further, a drain region of the PMOS transistor P 101 is electrically connected to a source region of the PMOS transistor P 104 via two contacts and a line. As a result, the PMOS transistors P 101 and P 104 are connected in series. On the other hand, the NMOS transistor N 101 shares, with the adjacent NMOS transistor N 102 , an N type diffusion region which serves as a drain region of the NMOS transistor N 101 and a source region of the NMOS transistor N 102 . As a result, the NMOS transistors N 101 and N 102 are connected in series. Further, a source region of the NMOS transistor N 101 is electrically connected to the ground line LG via a contact. The gate line G 101 is electrically connected to the input line L 101 via a contact. This structure allows the input signal Vin to be transmitted to each gate of the PMOS transistor P 101 and the NMOS transistor N 101 .

The line L 11 is electrically connected to the lines L 1 , L 2 via the contacts C 11 , C 12 , respectively. The line L 2 is electrically connected to the gate line G 104 via a contact C 1 . This structure allows an output (a control signal VC 2 ) of the inverter circuit 15 to be transmitted to the gates of the PMOS transistor P 104 and the NMOS transistor N 104 . The line L 12 , the line L 3 , and the gate line G 103 are electrically connected to each other via a contact C 13 . The line L 12 , the line L 4 , and the gate line G 106 are electrically connected to each other via a contact C 14 . This structure allows an output of the inverter circuit 12 to be transmitted to the respective gates of the PMOS transistor P 103 and the NMOS transistor N 103 , and an input of the inverter circuit 13 . Further, the line L 5 is electrically connected to the gate line G 105 via a contact C 2 . Thus, an input of the inverter circuit 12 is connected to the respective drains of the PMOS transistors P 103 , P 104 and NMOS transistors N 102 , N 103 .

Next, configuration and arrangement of a plurality of PMOS transistors, a plurality of NMOS transistors, and a plurality of gate lines, shown in FIG. 1 , will be described with reference to FIG. 4 . To facilitate understanding the connection between elements, FIG. 4 ( FIG. 9 and FIG. 14 as well) also shows contacts connected to a diffusion region (a source region/a drain region) or a gate line.

<PMOS Transistor>

The PMOS transistors P 101 , P 102 , . . . , P 108 are formed on the substrate along an X-axis direction such that the gate length direction of each of the PMOS transistors is parallel to the X-axis direction. Here, each of the PMOS transistors P 101 , P 102 , . . . , P 104 shares a P type diffusion region with its adjacent PMOS transistor. Similarly, the PMOS transistor P 105 shares, with the PMOS transistor P 106 , a P type diffusion region which serves as a source region for both transistors. The PMOS transistor P 107 shares a P type diffusion region with the PMOS transistor P 108 .

<NMOS Transistor>

Similar to the PMOS transistors P 101 , P 102 , . . . , P 108 , the NMOS transistors N 101 , N 102 , . . . , N 108 are formed on the substrate along the X-axis direction such that the gate length direction of each of the NMOS transistors is parallel to the X-axis direction. Further, the NMOS transistors N 101 , N 102 , . . . , N 108 are opposed to the PMOS transistors P 101 , P 102 , . . . , P 108 , respectively, in a Y-axis direction perpendicular to the X-axis direction. Here, each of the NMOS transistors N 101 , N 102 , . . . , N 104 shares an N type diffusion region with its adjacent NMOS transistor. Similarly, the NMOS transistor N 105 shares, with the NMOS transistor N 106 , an N type diffusion region which serves as a source region for both transistors. The NMOS transistor N 107 shares an N type diffusion region with the NMOS transistor N 108 .

<Gate Line>

The gate lines G 101 , G 102 , . . . , G 108 correspond to the PMOS transistors P 101 , P 102 , . . . , P 108 and the NMOS transistors N 101 , N 102 , . . . , N 108 , respectively. The gate lines G 101 , G 102 , . . . , G 108 are arranged parallel to each other and extend linearly along the Y-axis direction such that each of the gate lines G 101 , G 102 , . . . , G 108 passes through the gate areas of the PMOS transistors and the NMOS transistors which correspond to each of the gate lines G 101 , G 102 , . . . , G 108 . Specifically, each of the gate lines G 101 , G 102 , . . . , G 108 includes: a PMOS gate electrode portion which extends along the Y-axis direction in the gate area of the PMOS transistor so as to function as a gate electrode of the PMOS transistors P 101 , P 102 , . . . , P 108 ; an NMOS gate electrode portion which extends along the Y-axis direction in the gate area of the NMOS transistor so as to function as a gate electrode of the NMOS transistors N 101 , N 102 , . . . , N 108 ; and a line main portion which extends along the Y-axis direction to linearly connect the PMOS gate electrode portion and the NMOS gate electrode portion together.

<Dummy Gate Line>

The dummy gate lines GD 1 , GD 2 , . . . , GD 4 are arranged parallel to, and extend linearly along, the Y-axis direction, together with the gate lines G 101 , G 102 , . . . , G 108 . The dummy gate lines GD 1 , GD 4 are not electrically connected to any one of the PMOS transistors P 101 , P 102 , . . . , P 108 and the NMOS transistors N 101 , N 102 , . . . , N 108 . Here, the gate lines G 107 , G 105 are connected to the dummy gate lines GD 2 , GD 3 , respectively, via gate connecting lines, or may be connected to the dummy gate lines GD 2 , GD 3 via metal lines.

<Projections and Connecting Line>

Each of the plurality of gate lines may have a line main portion which linearly extends along the Y-axis direction, and a projection which projects out from a predetermined location of the line main portion toward the X-axis direction. Further, the projection may be electrically connected to a line via a contact. For example, in the semiconductor integrated circuit shown in FIG. 1 , the gate lines G 101 , G 102 , . . . , G 104 , G 106 , G 108 have such a projection as described above. Further, at least a pair of adjacent gate lines (or, at least a pair of adjacent gate line and dummy gate line) may be connected to each other via a connecting line extending from a predetermined location of one gate line to a predetermined location of the other gate line. For example, in the semiconductor integrated circuit shown in FIG. 1 , the gate line G 105 and the dummy gate line GD 3 are connected to each other via a connecting line extending from a predetermined location of the gate line G 105 to a predetermined location of the dummy gate line GD 3 . That is, the gate line G 105 , the dummy gate line GD 3 , and the connecting line form a gate region in the general shape of a letter “H” when viewed from above.

As described above, the PMOS transistors P 101 , P 102 , . . . , P 108 and the NMOS transistors N 101 , N 102 , . . . , N 108 are arranged such that the PMOS transistor and the NMOS transistor which receive the same signal in the respective gates in the circuit configuration are opposed to each other. Such arrangement allows the linearly extending gate lines G 101 , G 102 , . . . , G 108 to be laid out. Thus, unlike the conventional technique, there is no separation of the gate line at an arbitrary location, and therefore, it is possible to reduce variations in dimensions of a gate line provided close to the separation portion. Further, the adjacent gate lines are connected to each other at a predetermined location to form an H-shaped gate line. The H-shaped gate line allows the gate lines to be used as a wiring resource for a latch function. Thus, it is possible to avoid an increase in the cell height due to an increase in wiring resources of the two metal layers, and possible to reduce the size of a semiconductor integrated circuit.

(Variation of First Embodiment)

FIG. 5 shows an example layout of a semiconductor integrated circuit according to the first variation of the first embodiment. The semiconductor integrated circuit includes PMOS transistors P 111 , P 112 , NMOS transistors N 111 , N 112 , and gate lines G 111 , G 112 , in place of the PMOS transistor P 105 , the NMOS transistor N 105 , and the gate line G 105 shown in FIG. 1 . Here, an input line L 104 transmits an input signal VS.

The layout shown in FIG. 5 corresponds to the circuit configuration shown in FIG. 6 . A NAND circuit 12 a includes the PMOS transistors P 111 , P 112 and the NMOS transistors N 111 , N 112 . Further, the circuit configuration shown in FIG. 6 can be obtained by modifying the circuit configuration shown in FIG. 7 . That is, the semiconductor integrated circuit shown in FIG. 5 includes, as a standard cell, a latch circuit having tri-state inverter circuits 16 , 17 , the NAND circuit 12 a , and the inverter circuits 13 , 14 , 15 (i.e., a latch circuit having a setting function). According to this latch circuit, if the input signal VS is at a low level, an output of the NAND circuit 12 a is set to a high level. As a result, an output signal Vout can be set to a low level. Here, the semiconductor integrated circuit shown in FIG. 5 may include not only the standard cell which functions as a latch circuit, but also other standard cells.

(Second Embodiment)

FIG. 8 shows an example layout of a semiconductor integrated circuit according to the second embodiment. The semiconductor integrated circuit includes PMOS transistors P 201 , P 202 , . . . , P 208 , NMOS transistors N 201 , N 202 , . . . , N 208 , and gate lines G 201 , G 202 , . . . , G 208 , in place of the PMOS transistors P 101 , P 102 , . . . , P 104 , the NMOS transistors N 101 , N 102 , . . . , N 104 , and the gate lines G 101 , G 102 , . . . , G 104 . The semiconductor integrated circuit further includes dummy gate electrodes GD 5 , GD 6 . The input lines L 201 , L 202 transmit input signals Vin, VC, respectively. The output line L 203 transmits an output signal Vout. In FIG. 8 , lines L 201 , L 202 , L 203 , L 21 , L 22 , . . . , L 24 are shown as being transparent to facilitate understanding of the connection between elements.

As shown in FIG. 9 , the PMOS transistors P 201 , P 202 , . . . , P 208 are formed on the substrate along an X-axis direction such that the gate length direction of each of the PMOS transistors is parallel to the X-axis direction. Similar to the PMOS transistors P 201 , P 202 , . . . , P 208 , the NMOS transistors N 201 , N 202 , . . . , N 208 are formed on the substrate along the X-axis direction such that the gate length direction of each of the NMOS transistors is parallel to the X-axis direction. Further, the NMOS transistors N 201 , N 202 , . . . , N 208 are opposed to the PMOS transistors P 201 , P 202 , . . . , P 208 , respectively, in the Y-axis direction. The gate lines G 201 , G 202 , . . . , G 208 correspond to the PMOS transistors P 201 , P 202 , . . . , P 208 and the NMOS transistors N 201 , N 202 , . . . , N 208 , respectively. The gate lines G 201 , G 202 , . . . , G 208 are arranged parallel to each other and extend linearly along the Y-axis direction such that each of the gate lines G 201 , G 202 , . . . , G 208 passes through the gate areas of the PMOS transistors and the NMOS transistors which correspond to each of the gate lines G 201 , G 202 , . . . , G 208 . Here, the gate lines G 108 , G 204 , G 205 , G 105 are connected to the dummy gate lines GD 2 , GD 3 , GD 4 , GD 5 , respectively, via gate connecting lines, or may be connected to the dummy gate lines GD 2 , GD 3 , GD 4 , GD 5 via metal lines.

The layout shown in FIG. 8 corresponds to the circuit configuration shown in FIG. 10 . The combinational circuit 21 includes the PMOS transistors P 201 , P 202 , . . . , P 204 and the NMOS transistors N 201 , N 202 , . . . , N 204 . The combinational circuit 22 includes the PMOS transistors P 205 , P 206 , . . . , P 208 and the NMOS transistors N 205 , N 206 , . . . , N 208 . The circuit configuration shown in FIG. 10 can be obtained by modifying the circuit configuration shown in FIG. 11 . Specifically, the combinational circuit 21 shown in FIG. 10 can be implemented by combining tri-state inverter circuits 23 , 24 , shown in FIG. 11 , together. The combinational circuit 22 shown in FIG. 10 can be implemented by combining a combinational circuit 25 with a tri-state inverter circuit 26 shown in FIG. 11 . Further, the circuit configuration shown in FIG. 11 can be obtained by modifying the circuit configuration shown in FIG. 12 . Specifically, the combinational circuit 25 shown in FIG. 11 can be implemented by combining an inverter circuit 27 with a transfer gate 28 shown in FIG. 12 . That is, the semiconductor integrated circuit shown in FIG. 8 includes, as a standard cell, a flip-flop circuit having the tri-state inverter circuits 23 , 24 , 26 , the transfer gate 28 , and the inverter circuits 12 , 13 , . . . , 15 , 27 (i.e., a master slave D flip-flop circuit). Further, the semiconductor integrated circuit shown in FIG. 8 may include not only the standard cell which functions as a flip-flop circuit, but also other standard cells.

As described above, the PMOS transistors P 201 , P 202 , . . . , P 208 and the NMOS transistors N 201 , N 202 , . . . , N 208 are arranged such that the PMOS transistor and the NMOS transistor which receive the same signal in the respective gates in the circuit configuration are opposed to each other. Such arrangement allows the linearly extending gate lines G 201 , G 202 , . . . , G 208 to be laid out. As described, the latch configurations described in the first embodiment are combined together, and thereby, can be applied to a flip-flop circuit. Therefore, as in the case of the semiconductor integrated circuit shown in FIG. 1 , it is possible to reduce variations in dimensions between transistors, and possible to reduce the size of the semiconductor integrated circuit.

Turning to the configurations of the combinational circuits 21 , 22 shown in FIG. 8 , the layout of the combinational circuit 21 and the layout of the combinational circuit 22 are symmetrical, except the location of the contact C 201 . Thus, it is possible to easily design the layout of the combinational circuit 22 , based on the layout of the combinational circuit 21 .

(Variation of Second Embodiment)

FIG. 13 shows an example layout of a semiconductor integrated circuit according to a variation of the second embodiment. The semiconductor integrated circuit includes PMOS transistors P 301 , P 302 , . . . , P 304 , NMOS transistors N 301 , N 302 , . . . , N 304 , and gate lines G 301 , G 302 , . . . , G 304 , in place of the PMOS transistor P 201 , the NMOS transistor N 201 , and the gate line G 201 , shown in FIG. 8 . Further, the semiconductor integrated circuit further includes a dummy gate line GD 7 . Input lines L 301 , L 302 , L 303 , L 304 transmit input signals Vin 1 , Vin 2 , VC, VS, respectively. An output line L 305 transmits an output signal Vout. In FIG. 13 , the lines L 301 , L 302 , . . . , L 304 , L 31 , L 32 , . . . , L 36 are shown as being transparent to facilitate understanding of the connection between elements.

As shown in FIG. 14 , the PMOS transistors P 301 , P 302 , . . . , P 304 are formed on the substrate along an X-axis direction such that the gate length direction of each of the PMOS transistors is parallel to the X-axis direction. Similar to the PMOS transistors P 301 , P 302 , . . . , P 304 , the NMOS transistors N 301 , N 302 , . . . , N 304 are formed on the substrate along the X-axis direction such that the gate length direction of each of the NMOS transistors is parallel to the X-axis direction. Further, the NMOS transistors N 301 , N 302 , . . . , N 304 are opposed to the PMOS transistors P 301 , P 302 , . . . , P 304 , respectively, in a Y-axis direction. The gate line G 301 , G 302 , . . . , G 304 correspond to PMOS transistors P 301 , P 302 , . . . , P 304 and the NMOS transistors N 301 , N 302 , . . . , N 304 , respectively. The gate lines G 301 , G 302 , . . . , G 304 are arranged parallel to each other and extend linearly along the Y-axis direction such that each of the gate lines G 301 , G 302 , . . . , G 304 passes through the gate areas of the PMOS transistors and the NMOS transistors which correspond to each of the gate lines G 301 , G 302 , . . . , G 304 . Here, the gate lines G 301 , G 203 , G 201 , G 107 , G 105 are connected to dummy gate lines GD 2 , GD 3 , GD 4 , GD 5 , GD 6 , respectively, via a connecting line. The other gate lines are provided with a projection. The gate lines G 301 , G 203 , G 201 , G 107 , G 105 may be connected to the dummy gate lines GD 2 , GD 3 , GD 4 , GD 5 , GD 6 , respectively, via a metal line.

The layout shown in FIG. 13 corresponds to the circuit configuration shown in FIG. 15 . An inverter 31 includes a PMOS transistor P 300 and an NMOS transistor N 300 . A combinational circuit 32 includes unit circuits 33 , 34 , the PMOS transistors P 201 , P 202 , P 203 , and the NMOS transistors N 201 , N 202 , N 203 . The unit circuit 33 includes the PMOS transistors P 301 , P 302 , . . . , P 304 . The unit circuit 34 includes the NMOS transistors N 301 , N 302 , . . . , N 304 . The circuit configuration shown in FIG. 15 can be obtained by modifying the circuit configuration shown in FIG. 16 . Specifically, the combinational circuit 32 can be implemented by combining the unit circuits 33 , 34 , the PMOS transistor P 201 , the NMOS transistor N 203 , and the tri-state inverter circuit 24 , shown in FIG. 16 , together. That is, the semiconductor integrated circuit includes, as a standard cell, a flip-flop circuit having the inverter circuits 31 , 12 , 13 , . . . , 15 , 27 , the unit circuits 33 , 34 , the PMOS transistor P 201 , the NMOS transistor N 203 , the tri-state inverter circuits 24 , 26 , and the transfer gate 28 (i.e., a flip-flop circuit having an input switching function). In this flip-flop circuit, if the input signal VS is at a high level, the input signal Vin 1 is transmitted to the inverter circuit 27 , and the input signal Vin 2 is cut. If the input signal VS is at a low level, the input signal Vin 1 is cut, and the input signal Vin 2 is transmitted to the inverter circuit 27 . Here, the semiconductor integrated circuit shown in FIG. 13 may include not only the standard cell which functions as a flip-flop circuit, but also other standard cells.

Here, comparison between the combinational circuit 32 in FIG. 15 and the combinational circuit 21 in FIG. 10 shows that the combinational circuit 32 can be configured by replacing the PMOS transistor P 204 and the NMOS transistor N 204 of the combinational circuit 21 with the unit circuits 33 , 34 in FIG. 15 . In other words, it is possible to consider that the unit circuits 33 , 34 as a self-similar circuit of the combinational circuit 32 are hierarchically included in the combinational circuit 32 . Thus, the layout of the semiconductor integrated circuit can be easily designed by designing the unit circuits 33 , 34 , which are the smallest unit of the combinational circuit 32 , and thereafter designing the combinational circuit 32 which includes the unit circuits 33 , 34 (i.e., by developing the layout in a hierarchical order) at the time of the layout.

Further, the PMOS transistors P 301 , P 302 , . . . , P 304 and the NMOS transistors N 301 , N 302 , . . . , N 304 are arranged such that the PMOS transistor and the NMOS transistor which receive the same signal in the respective gates in the circuit configuration are opposed to each other. Such arrangement allows the linearly extending gate lines G 301 , G 302 , . . . , G 304 to be laid out. As described, the circuit included in the latch circuit described in the first embodiment is developed as a self-similar circuit in a flip-flop circuit, and thereby, can be applied to a flip-flop circuit having a complex circuit function. Therefore, as in the case of the semiconductor integrated circuit shown in FIG. 8 , it is possible to reduce variations in dimensions between transistors, and possible to reduce the size of the semiconductor integrated circuit.

(Other Embodiments)

In the above embodiments, the line paths of the lines (e.g., power supply lines, ground lines, input lines, and output lines) other than the gate lines are not limited to the line paths shown in FIG. 1 , FIG. 5 , FIG. 8 , and FIG. 13 . Further, the location of each circuit (e.g., the combinational circuit and the inverter circuit) is not limited to the location shown in FIG. 1 , FIG. 5 , FIG. 8 , and FIG. 13 .

<Line Width and Space Between Adjacent Lines>

Further, each of the plurality of gate lines and the plurality of dummy gate lines may have a constant width (a length along the X axis). The space between adjacent gate lines and adjacent dummy gate lines may be constant.

<Gate Width>

Further, each of the plurality of PMOS transistors may have a constant gate width, and each of the plurality of NMOS transistors may have a constant gate width.

As described above, according to the above-mentioned semiconductor integrated circuit, it is possible to reduce variations in dimensions between transistors and reduce the circuit size. Therefore, the above-mentioned semiconductor integrated circuit is useful as a semiconductor integrated circuit in which a standard cell, such as a latch circuit and a flip-flop circuit, is provided.

The foregoing embodiments are merely preferred examples in nature, and are not intended to limit the scope of the present invention, its applications, or use of the invention.