Semiconductor memory apparatus

The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2010-0028328, filed on Mar. 30, 2010, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

1. Technical Field

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus.

2. Related Art

In general, a semiconductor memory apparatus generates an internal voltage which has a voltage level necessary for an internal circuit, by using an external voltage. In order to allow the internal circuit to normally perform an operation, the semiconductor memory apparatus is designed such that the internal voltage level is stabilized to a target level within a preset time after the external voltage is initially applied to the semiconductor memory apparatus.

As a semiconductor memory apparatus is highly integrated, a gap between signal lines or power lines decreases, and thus, the parasitic capacitance between the lines increases. Accordingly, even through the internal voltage is generated to the target level in an internal voltage generation circuit of the semiconductor memory apparatus, the internal voltage of the target level is not transferred to the internal circuit due to the parasitic capacitance between the power lines for transferring the internal voltage to the internal circuit, whereby the misoperation of the semiconductor memory apparatus can be caused.

A semiconductor memory apparatus which can prevent misoperation of an internal circuit in an initial operation of a to semiconductor memory apparatus is described herein.

In one embodiment of the present invention, a semiconductor memory apparatus includes: a counting control circuit configured to generate a first counting start signal, a second counting start signal and a counting count signal in response to an auto-refresh signal, a voltage stabilization signal and a fuse control signal; and an address counting circuit for auto-refresh configured to count a plurality of count addresses in response to the first counting start signal, and count only specified count addresses among the plurality of count addresses in response to the second counting start signal and the counting control signal.

In another embodiment of the present invention, a semiconductor memory apparatus includes: an address counting circuit for auto-refresh configured to provide a plurality of count addresses which are counted in an auto-refresh operation; and a counting control circuit configured to control the address counting circuit for auto-refresh such that only specified upper bit count addresses among the plurality of count addresses are counted when activating the semiconductor memory apparatus.

Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:

FIG. 1 is a configurational view schematically illustrating a semiconductor memory apparatus in accordance with an embodiment of the present invention;

FIG. 2 is a configurational view of the counting control circuit shown in FIG. 1 ;

FIG. 3 is a configurational view of the counting control signal generation block shown in FIG. 2 ;

FIG. 4 is a configurational view of the enable control unit shown in FIG. 3 ;

FIG. 5 is a configurational view of the disable control unit shown in FIG. 3 ;

FIG. 6 is a configurational view of the first counting start signal generation block shown in FIG. 2 ;

FIG. 7 is a configurational view of the second counting start signal generation block shown in FIG. 2 ;

FIG. 8 is a configurational view of the address counting circuit for auto-refresh shown in FIG. 1 ;

FIG. 9 is a configurational view of the first counting block shown in FIG. 8 ; and

FIG. 10 is a configurational view of the second counting block shown in FIG. 8 .

Hereinafter, a semiconductor memory apparatus according to an embodiment of the present invention will be described below with reference to the accompanying drawings through an example embodiment.

Referring to FIG. 1 , a semiconductor memory apparatus in accordance with an embodiment of the present invention includes a counting control circuit 100 and an address counting circuit 200 for auto-refresh.

The counting control circuit 100 is configured to generate first and second counting start signals cnt_start 1 and cnt_start 2 , respectively, and a count control signal cnt_ctrl in response to an auto-refresh signal auto_ref, a voltage stabilization signal V_stable, a fuse control signal Fuse_ctrl, and specified count addresses (for example, tenth through thirteenth count addresses add_cnt<9:12>) of first through thirteenth count addresses add_cnt<0:12>.

For example, the counting control circuit 100 enables the counting control signal cnt_ctrl when both the voltage stabilization signal V_stable and the fuse control signal Fuse_ctrl are enabled, and enables the second counting start signal cnt_start 2 when a preset time elapses after the counting control signal cnt_ctrl is enabled. Also, the counting control circuit 100 enables the first counting start signal cnt_start 1 when the counting control signal cnt_ctrl is disabled and the auto-refresh signal auto_ref is enabled. The counting control circuit 100 disables the counting control signal cnt_ctrl when the counting value of the specified count addresses add_cnt<9:12> reaches a preset value. The fuse control signal Fuse_ctrl is the output signal of a general fuse circuit and is enabled or disabled depending upon fuse cutting. The voltage stabilization signal V_stable is a signal that is enabled when a preselected time elapses after a power-up signal (not shown) is enabled, such as, for example, in the case where an external voltage is applied to a deactivated semiconductor memory apparatus and the semiconductor memory apparatus is converted into an activated state.

The address counting circuit 200 for auto-refresh is configured to count the first through thirteenth count addresses add_cnt<0:12> in response to the first counting start signal cnt_start 1 and to count the specified count addresses add_cnt<9:12> among the first through thirteenth count addresses add_cnt<0:12> in response to the second counting start signal cnt_start 2 and the counting control signal cnt_ctrl. For example, the address counting circuit 200 for auto-refresh counts the first through thirteenth count addresses add_cnt<0:12> when the first counting start signal cnt_start 1 is enabled, and counts the specified count addresses add_cnt<9:12> when both the second counting start signal cnt_start 2 and the counting control signal cnt_ctrl are enabled.

Referring to FIG. 2 , the counting control circuit 100 includes a counting control signal generation block 110 , a first counting start signal generation block 120 , and a second counting start signal generation block 130 .

The counting control signal generation block 110 is configured to generate the counting control signal cnt_ctrl in response to the voltage stabilization signal V_stable, the fuse control signal Fuse_ctrl and the counting value of the specified count addresses add_cnt<9:12>. For example, the counting control signal generation block 110 enables the counting control signal cnt_ctrl when both the voltage stabilization signal V_stable and the fuse control signal Fuse_ctrl are enabled, and disables the counting control signal cnt_ctrl when the counting value of the specified count addresses add_cnt<9:12> corresponds to the preset value.

The first counting start signal generation block 120 is configured to generate the first counting start signal cnt_start 1 in response to the counting control signal cnt_ctrl and the auto-refresh signal auto_ref. For example, the first counting start signal generation block 120 enables the first counting start signal cnt_start 1 when the counting control signal cnt_ctrl is disabled and the auto-refresh signal auto_ref is enabled.

The second counting start signal generation block 130 is configured to generate the second counting start signal cnt_start 2 in response to the counting control signal cnt_ctrl. For example, the second counting start signal generation block 130 enables the second counting start signal cnt_start 2 when the counting control signal cnt_ctrl is enabled and the preset time elapses.

Referring to FIG. 3 , the counting control signal generation block 110 includes an enable control unit 111 and a disable control unit 112 .

The enable control unit 111 is configured to enable the counting control signal cnt_ctrl when both the voltage stabilization signal V_stable and the fuse control signal Fuse_ctrl are enabled, and to disable the counting control signal cnt_ctrl when a disable control signal dis_ctrl is enabled.

The disable control unit 112 is configured to enable the disable control signal dis_ctrl when the counting value of the specified count addresses add_cnt<9:12> reaches the preset value. For example, the disable control unit 112 enables the disable control signal dis_ctrl when the counting value of the specified count addresses add_cnt<9:12> reaches ‘1111’ (e.g., a maximum value).

Referring to FIG. 4 , the enable control unit 111 includes a first pulse generation section 111 - 1 and a signal level maintaining section 111 - 2 .

The first pulse generation section 111 - 1 is configured to generate a first pulse pulse 1 when both the voltage stabilization signal V_stable and the fuse control signal Fuse_ctrl are enabled.

The first pulse generation section 111 - 1 includes first and second NAND gates ND 11 and ND 12 , respectively; first, second, and third inverters IV 11 , IV 12 and IV 13 , respectively; and a first delay part delay 11 . The first NAND gate ND 11 receives the voltage stabilization signal V_stable and the fuse control signal Fuse_ctrl. The first inverter IV 11 receives the output signal of the first NAND gate ND 11 . The first delay part delay 11 receives the output signal of the first inverter IV 11 . The second inverter IV 12 receives the output signal of the first delay part delay 11 . The second NAND gate ND 12 receives the output signals of the first and second inverters IV 11 and IV 12 . The third inverter IV 13 receives the output signal of the second NAND gate ND 12 and outputs the first pulse pulse 1 based thereon.

The signal level maintaining section 111 - 2 is configured to enable the counting control signal cnt_ctrl when the first pulse pulse 1 is generated and maintain the enabled counting control signal cnt_ctrl until the disable control signal dis_ctrl is enabled.

The signal level maintaining section 111 - 2 includes first, second, third, and fourth transistors P 11 , P 12 , N 11 , and P 13 , respectively, and fourth, fifth, and sixth inverters IV 14 , IV 15 , and IV 16 , respectively. The first transistor P 11 has a gate which receives the fuse control signal Fuse_ctrl and a source which is applied with an external voltage VDD. The second transistor P 12 has a gate which receives the first pulse pulse 1 and a source to which the drain of the first transistor P 11 is coupled. The third transistor N 11 has a gate which receives the first pulse pulse 1 , a drain to which the drain of the second transistor P 12 is coupled, and a source to which a ground terminal VSS is coupled. The fourth inverter IV 14 receives the disable control signal dis_ctrl. The fourth transistor P 13 has a gate which receives the output signal of the fourth inverter IV 14 , a source which receives the external voltage VDD, and a drain to which a node where the second transistor P 12 and the third transistor N 11 are coupled is coupled. The fifth inverter IV 15 has an input terminal to which a node where the second through fourth transistors P 12 , N 11 and P 13 are coupled is coupled and an output terminal which outputs the counting control signal cnt_ctrl. The sixth inverter IV 16 has an input terminal to which the output terminal of the fifth inverter IV 15 is coupled and an output terminal which is coupled to the input terminal of the fifth inverter IV 15 .

Referring to FIG. 5 , the disable control unit 112 includes an end signal generation section 112 - 1 , a second pulse generation section 112 - 2 , and a latch section 112 - 3 .

The end signal generation section 112 - 1 is configured to output the counting control signal cnt_ctrl as an end signal ends when the counting value of the specified count addresses add_cnt<9:12> reaches the preset value, such as for example, a maximum value (e.g., ‘1111’).

The end signal generation section 112 - 1 includes third, fourth, and fifth NAND gates ND 21 , ND 22 , and ND 23 , respectively; first and second NOR gates NR 21 and NR 22 , respectively; seventh, eighth, ninth, and tenth inverters IV 21 , IV 22 , IV 23 , and IV 24 , respectively; and first, second, third, and fourth control inverters IVC 21 , IVC 22 , IVC 23 , and IVC 24 , respectively. The third NAND gate ND 21 receives the specified count addresses add_cnt<9> and add_cnt<10>. The fourth NAND gate ND 22 receives the specified count addresses add_cnt<11> and add_cnt<12>. The first NOR gate NR 21 receives the output signals of the third and fourth NAND gates ND 21 and ND 22 . The fifth NAND gate ND 23 receives the output signal of the first NOR gate NR 21 and a clock CLK. The seventh inverter IV 21 receives the output signal of the fifth NAND gate ND 23 . The eighth inverter IV 22 receives the output signal of the seventh inverter IV 21 . The first control inverter IVC 21 has a first control terminal which receives the output signal of the eighth inverter IV 22 , a second control terminal which receives the output signal of the seventh inverter IV 21 , and an input terminal which receives the counting control signal cnt_ctrl. The ninth inverter IV 23 receives the fuse control signal Fuse_ctrl. The second NOR gate NR 22 receives the output signal of the first control inverter IVC 21 and the output signal of the ninth inverter IV 23 . The second control inverter IVC 22 has a first control terminal which receives the output signal of the seventh inverter IV 21 , a second control terminal which receives the output signal of the eighth inverter IV 22 , an input terminal which receives the output signal of the second NOR gate NR 22 , and an output terminal to which a node where the first control inverter IVC 21 and the second NOR gate NR 22 are coupled. The third control inverter IVC 23 has a first control terminal which receives the output signal of the seventh inverter IV 21 , a second control terminal which receives the output signal of the eighth inverter IV 22 , and an input terminal which receives the output signal of the second NOR gate NR 22 . The tenth inverter IV 24 receives the output signal of the third control inverter IVC 23 and outputs the end signal end_s based thereon. The fourth control inverter IVC 24 has a first control terminal which receives the output signal of the eighth inverter IV 22 , a second control terminal which receives the output signal of the seventh inverter IV 21 , an input terminal which receives the output signal of the tenth inverter IV 24 , and an output terminal which is coupled to the input terminal of the tenth inverter IV 24 .

The second pulse generation section 112 - 2 is configured to generate a second pulse pulse 2 when the end signal ends is enabled.

The second pulse generation section 112 - 2 includes a second delay part delay 21 , an eleventh inverter IV 25 , and a sixth NAND gate ND 24 . The second delay part delay 21 receives the end signal end_s. The eleventh inverter IV 25 receives the output signal of the second delay part delay 21 . The sixth NAND gate ND 24 receives the end signal end_s and the output signal of the eleventh inverter IV 25 and outputs the second pulse pulse 2 based thereon.

The latch section 112 - 3 is configured to enable the disable control signal dis_ctrl in response to the second pulse pulse 2 and to maintain the enabled disable control signal dis_ctrl. The latch section 112 - 3 is initialized when a power-up signal pwrup is enabled and disables the disable control signal dis_ctrl in response thereto.

The latch section 112 - 3 includes seventh and eighth NAND gates ND 25 and ND 26 , respectively, twelfth and thirteenth inverters IV 26 and IV 27 , respectively, and a third NOR gate NR 23 . The seventh NAND gate ND 25 receives the second pulse pulse 2 and the output signal of the eighth NAND gate ND 26 . The twelfth inverter IV 26 receives the power-up signal pwrup. The eighth NAND gate ND 26 receives the output signal of the seventh NAND gate ND 25 and the output signal of the twelfth inverter IV 26 . The third NOR gate NR 23 receives the output signal of the seventh NAND gate ND 25 and the power-up signal pwrup. The thirteenth inverter IV 27 receives the output signal of the third NOR gate NR 23 and outputs the disable control signal dis_ctrl based thereon.

Referring to FIG. 6 , the first counting start signal generation block 120 includes fourteenth and fifteenth inverters IV 31 and IV 32 , respectively, and a ninth NAND gate ND 31 . The fourteenth inverter IV 31 receives the counting control signal cnt_ctrl. The ninth NAND gate ND 31 receives the auto-refresh signal auto_ref and the output signal of the fourteenth inverter IV 31 . The fifteenth inverter IV 32 receives the output signal of the ninth NAND gate ND 31 and outputs the first counting start signal cnt_start 1 based thereon.

Referring to FIG. 7 , the second counting start signal generation block 130 includes an oscillator 131 , a clock dividing unit 132 , and a shifting unit 133 .

The oscillator 131 is configured to generate an oscillator signal osc when the counting control signal cnt_ctrl is enabled.

The clock dividing unit 132 is configured to divide the oscillator signal osc and to generate a divided oscillator signal osc_div based thereon.

The shifting unit 133 is configured to shift the counting control signal cnt_ctrl by the cycle of the divided oscillator signal osc_div that corresponds to the preset time (i.e., the time from after the counting control signal cnt_ctrl is enabled to when the second counting start signal cnt_start 2 is enabled) and to generate the second counting start signal cnt_start 2 based thereon.

Referring to FIG. 8 , the address counting circuit 200 for auto-refresh shown in FIG. 1 includes a first counting block 210 , a multiplexer 220 , and a second counting block 230 .

The first counting block 210 is configured to count the first through ninth count addresses add_cnt<0:8> excluding the specified count addresses (i.e., the tenth through thirteenth count addresses add_cnt<9:12> of the first through thirteenth count addresses add_cnt<0:12>), when the first counting start signal cnt_start 1 is enabled.

The multiplexer 220 is configured to output the most significant bit count address (e.g., the ninth count address add_cnt<8> of the first through ninth count addresses add_cnt<0:8>) or the second counting start signal cnt_start 2 as a select signal select_s in response to the counting control signal cnt_ctrl. For example, the multiplexer 220 outputs the second counting start signal cnt_start 2 as the select signal select_s when the counting control signal cnt_ctrl is enabled, and outputs the ninth count address add_cnt<8> as the select signal select_s when the counting control signal cnt_ctrl is disabled.

The second counting block 230 is configured to count the specified count addresses (i.e., the tenth through thirteenth count addresses add_cnt<9:12>) in response to the select signal select_s.

Referring to FIG. 9 , the first counting block 210 includes first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth bit counters 211 , 212 , 213 , 214 , 215 , 216 , 217 , 218 , and 219 , respectively, which are coupled in series as shown. The first through ninth bit counters 211 , 212 , 213 , 214 , 215 , 216 , 217 , 218 , 219 output the first through ninth count addresses add_cnt<0:8>, respectively. The first counting block 210 up-counts the first through ninth count addresses add_cnt<0:8> when the first counting start signal cnt_start 1 is enabled. The first through ninth bit counters 211 , 212 , 213 , 214 , 215 , 216 , 217 , 217 , 219 are activated according to the first counting start signal cnt_start 1 .

Referring to FIG. 10 , the second counting block 230 includes tenth, eleventh, twelfth, and thirteenth bit counters 231 , 232 , 233 , and 234 , respectively, which are coupled in series as shown. The tenth through thirteenth bit counters 231 , 232 , 233 , 234 output the tenth through thirteenth count addresses add_cnt<9:12>, respectively. The second counting block 230 up-counts the tenth through thirteenth count addresses add_cnt<9:12> when the select signal select_s is enabled. The tenth through thirteenth bit counters 231 , 232 , 233 , 234 , which constitute the second counting block 230 , are configured to be activated when any one of the first and second counting start signals cnt_start 1 and cnt_start 2 are enabled. The second counting block 230 further includes a fourth NOR gate NR 31 and a fourteenth inverter IV 31 . The fourth NOR gate NR 31 receives the first and second counting start signals cnt_start 1 and cnt_start 2 . The fourteenth inverter IV 31 receives the output signal of the fourth NOR gate NR 31 and provides its output to the tenth through thirteenth bit counters 231 through 234 .

The semiconductor memory apparatus in accordance with an embodiment of the present invention, configured as mentioned above, operates as described below.

The deactivated semiconductor memory apparatus is activated by being applied with the external voltage VDD, when the fuse control signal Fuse_ctrl is in an enabled state. The counting control signal cnt_ctrl is enabled when the voltage stabilization signal V_stable is enabled. If the preset time elapses after the counting control signal cnt_ctrl is enabled, the second counting start signal cnt_start 2 is enabled.

The address counting circuit 200 counts the specified count addresses, that is, the ninth through thirteenth count addresses add_cnt<9:12> of the first through thirteenth count addresses add_cnt<0:12>. The first through eighth count addresses add_cnt<0:8>, which are not counted, maintain an initial value such as ‘000000000’ for example.

The counting control signal cnt_ctrl is disabled when the ninth through thirteenth count addresses add_cnt<9:12> reach the maximum value (e.g., ‘1111’).

If the counting control signal cnt_ctrl is disabled, the second counting start signal cnt_start 2 is also disabled, and the ninth through thirteenth count addresses add_cnt<9:12> have an initial value such as ‘0000’ for example.

If the semiconductor memory apparatus is activated and the ninth through thirteenth count addresses add_cnt<9:12> of the first through thirteenth count addresses add_cnt<0:12> are counted, reach the maximum value and then proceed to the initial value, both the counting control signal cnt_ctrl and the second counting start signal cnt_start 2 are disabled.

If the counting control signal cnt_ctrl and the second counting start signal cnt_start 2 are disabled, the semiconductor memory apparatus generates the first counting start signal cnt_start 1 in response to the auto-refresh signal auto_ref.

If the first counting start signal cnt_start 1 is enabled, all of the first through thirteenth count addresses add_cnt<0:12> are counted.

In the semiconductor memory apparatus, the tenth through thirteenth count addresses add_cnt<9:12> of the first through thirteenth count addresses add_cnt<0:12> are used as addresses for designating the positions of respective mats which constitute the data storage region of the semiconductor memory apparatus, and the first through ninth count addresses add_cnt<0:8> are used as addresses for designating the positions of the word lines of the respective mats, such that an auto-refresh operation can be performed.

As a result, in the case where a deactivated semiconductor memory apparatus is activated by initially receiving an external voltage, count addresses, which designate respective mats, are sequentially counted, and count addresses, which designate the positions of the word lines of the respective mats, are fixed to initial values, such that only the first word lines of the respective mats can be sequentially enabled. After only the first word lines of the respective mats are sequentially enabled, all count addresses which are used in an auto-refresh operation are counted in response to an auto-refresh signal, whereby the auto-refresh operation can be performed.

In the semiconductor memory apparatus in accordance with an embodiment of the present invention, the respective mats of the semiconductor memory apparatus are activated in the initial operation of the semiconductor memory apparatus, whereby initial misoperation of the semiconductor memory apparatus can be substantially prevented and the operation reliability of the semiconductor memory apparatus can be improved.

While a certain embodiment has been described above, it will be understood to those skilled in the art that the embodiment described is by way of example only. Accordingly, the semiconductor memory apparatus described herein should not be limited based on the described embodiment. Rather, the semiconductor memory apparatus described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.