Semiconductor storage device

This application is based upon and claims the benefit of priority from Japanese patent application No. 2009-074560, filed on Mar. 25, 2009, the disclosure of which is incorporated herein in its entirety by reference.

1. Field of the Invention

The present invention relates to a semiconductor storage device, in particular a semiconductor storage device including a flip-flop type memory cell.

2. Description of Related Art

FIG. 21 shows a configuration of a SRAM (Static Random Access Memory) disclosed in Japanese Unexamined Patent Application Publication No. 2008-262637 (Yamagami), and FIG. 22 shows a configuration of a memory cell used in this SRAM. The reading operation of this SRAM is explained with reference to FIG. 23 . FIG. 23 is a diagram for explaining a problem of the SRAM disclosed in Yamagami.

When a selected word line WL 1 changes to a High level and access transistors 18 and 19 are thereby turned on, a potential at a cell node (connection point between a load transistor 11 and a drive transistor 16 ) that has retained Low data by bit lines BL 1 and /BL 1 pre-charged to the power-supply potential VDD is pulled down to Vnd.

If Vnd is larger than the logic threshold voltage Vth 1 of the load transistor 11 and the drive transistor 16 that constitutes the cell inverter, the corruption of stored data could occur due to the inversion of the cell inverter, and thus leading to the malfunction of the SRAM (SNM (Static Noise Margin) failure).

Therefore, in Yamagami, pull-down circuits 30 A and 30 B that set the High level of the selected word line WL to a potential lower than the power-supply potential VDD are provided. In this way, the potential rise of the cell node retaining Low data is suppressed so that Vnd becomes smaller than the logic threshold voltage Vth 1 of the cell inverter, and therefore an improvement is made against the occurrence of the stored data corruption (SNM failure).

Japanese Unexamined Patent Application Publication Nos. 2008-210443 and 2008-176907 also disclose similar techniques to make an improvement against the SNM failure by setting the High level of word lines to a potential lower than the power-supply potential. However, in these SNM improving techniques, although the reading characteristic is improved by setting the High level of selected word lines WL to a potential lower than VDD, the writing characteristic to the cells becomes worse on the contrary.

Writing is performed by driving a bit line BL 1 to a Low level by a writing circuit so that the cell node that has been kept at a High level by the load transistor 11 is pulled down to a Low level through the access transistor 18 of the cell. However, since the potential of the selected word line WL 1 has been lowered, the on-resistance of the access transistor 18 increases, and thus making pulling down the cell node to the Low level very difficult. Consequently, the data writing characteristic to the cell deteriorates.

Accordingly, it is conceivable that the High level of the selected word line WL 1 should be set to the power-supply potential VDD only during the writing operation. However, when the word line WL 1 is selected but the bit lines BL 2 and /BL 2 are not selected, it creates such a situation that cell access is performed for a memory cell 10 C connected to the bit lines BL 2 and /BL 2 but stored data is not output (hereinafter called “pseudo-read state”). Therefore, the potential of the cell node at which a Low level is stored rises, and thus leading to the occurrence of the stored data corruption.

Further, Japanese Unexamined Patent Application Publication No. 4-205890 discloses a semiconductor storage device in which the driving capability of word line drivers during writing operation is reduced and delayed by a read/write signal (R/W signal) in order to eliminate the necessity of the write recovery time (address delay) that would be otherwise necessary when the semiconductor storage device changes from the write mode to the read mode.

The present inventors have found a following problem. That is, although the SNM improving techniques in related art can improve the reading characteristic, they have a problem that the writing characteristic becomes worse and they cannot, therefore, achieve both an excellent SRAM reading characteristic and writing characteristic simultaneously.

A first exemplary aspect of the present invention is a semiconductor storage device including: a plurality of word lines provided to correspond to the respective rows of the memory cells; a plurality of bit lines connected to a plurality of memory cells in respective columns of the memory cells; and a row selection circuit that, in a read operation, drives the word line to a set potential at a drive speed slower than a discharge speed of the bit line exhibited when the word line is raised roughly vertically to the set potential.

In this way, by adding a delay to the rising speed of the selected word line WL, an amount of data change retained in a memory cell can be suppressed, and therefor an improvement can be made against the SNM failure without deteriorating the writing characteristic.

The present invention, in an exemplary aspect, can provide a semiconductor storage device capable of achieving both an excellent reading operation and writing operation.

The above and other exemplary aspects, advantages and features will be more apparent from the following description of certain exemplary embodiments taken in conjunction with the accompanying drawings, in which:

FIG. 1 shows a configuration of a semiconductor storage device in accordance with a first exemplary embodiment of the present invention;

FIG. 2 shows a configuration of a memory cell of a semiconductor storage device in accordance with a first exemplary embodiment of the present invention;

FIG. 3 is a timing chart for explaining an operation of a semiconductor storage device in accordance with a first exemplary embodiment of the present invention;

FIG. 4 is a diagram for explaining an operation of a semiconductor storage device in accordance with a first exemplary embodiment of the present invention;

FIG. 5A is a diagram for explaining an operation of a semiconductor storage device in accordance with a first exemplary embodiment of the present invention;

FIG. 5B is a diagram for explaining an operation of a semiconductor storage device in accordance with a first exemplary embodiment of the present invention;

FIG. 6 shows a result of a simulation of an amount of potential change Vnd at a cell node NDB in a case where a delay is added to the rising of a selected word line WL;

FIG. 7 shows a configuration example of a row selection circuit of a semiconductor storage device in accordance with a first exemplary embodiment of the present invention;

FIG. 8 shows another configuration example of a row selection circuit of a semiconductor storage device in accordance with a first exemplary embodiment of the present invention;

FIG. 9 is a timing chart for explaining an operation of a semiconductor storage device in accordance with a second exemplary embodiment of the present invention;

FIG. 10 shows a configuration example of a row selection circuit of a semiconductor storage device in accordance with a second exemplary embodiment of the present invention;

FIG. 11 shows another configuration example of a row selection circuit of a semiconductor storage device in accordance with a second exemplary embodiment of the present invention;

FIG. 12 is a timing chart for explaining an operation of a semiconductor storage device in accordance with a third exemplary embodiment of the present invention;

FIG. 13 shows a configuration example of a row selection circuit of a semiconductor storage device in accordance with a third exemplary embodiment of the present invention;

FIG. 14 shows another configuration example of a row selection circuit of a semiconductor storage device in accordance with a third exemplary embodiment of the present invention;

FIG. 15 is a timing chart for explaining an operation of a semiconductor storage device in accordance with a forth exemplary embodiment of the present invention;

FIG. 16 shows a configuration example of a row selection circuit of a semiconductor storage device in accordance with a fourth exemplary embodiment of the present invention;

FIG. 17 shows a configuration example of a bit-line discharge signal generation circuit of a semiconductor storage device in accordance with a fourth exemplary embodiment of the present invention;

FIG. 18 shows another configuration example of a bit-line discharge signal generation circuit of a semiconductor storage device in accordance with a fourth exemplary embodiment of the present invention;

FIG. 19 is a timing chart for explaining an operation of a semiconductor storage device in accordance with a forth exemplary embodiment of the present invention;

FIG. 20 shows a configuration of a semiconductor storage device in accordance with a seventh exemplary embodiment of the present invention;

FIG. 21 shows a configuration of a semiconductor storage device disclosed in Yamagami;

FIG. 22 shows a memory cell of a semiconductor storage device shown in FIG. 22 ; and

FIG. 23 is a diagram for explaining a problem of a semiconductor storage device shown in FIG. 22 .

First Exemplary Embodiment

A configuration of a semiconductor storage device in accordance with a first exemplary embodiment of the present invention is explained hereinafter with reference to FIG. 1 . FIG. 1 shows a configuration of a semiconductor storage device 10 in accordance with this exemplary embodiment. As shown in FIG. 1 , the semiconductor storage device 10 includes a memory cell array 1 , a row selection circuit 2 , a column selection circuit 3 , a writing circuit 4 , and a reading circuit 5 .

The memory cell array 1 includes word lines WL 0 and WL 1 , bit lines (Bar bit lines: BLB 0 and BLB 1 , and True bit lines: BLT 0 and BLT 1 ), and memory cells MC 00 , MC 01 , MC 10 and MC 11 . For simplifying the explanation, an example in which two memory cells are connected to each of two pairs of bit lines (BLB 0 and BLT 0 , and BLB 1 and BLT 1 ) is explained hereinafter.

The word lines WL 0 and WL 1 extend in the horizontal direction in FIG. 1 , and arranged in parallel with each other. Further, the bit lines BLB 0 , BLB 1 , BLT 0 and BLT 1 extend in the vertical direction in FIG. 1 , and arranged in parallel with each other. The word lines WL 0 and WL 1 , and bit lines BLB 0 , BLB 1 , BLT 0 and BLT 1 are arranged so as to cross each other.

The memory cells MC 00 and MC 01 are connected to the bit lines BLB 0 and BLT 0 . The memory cells MC 10 and MC 11 are connected to the bit lines BLB 1 and BLT 1 . The memory cells MC 00 and MC 01 are connected to the word line WL 0 . The memory cells MC 01 and MC 11 are connected to the word line WL 1 .

The row selection circuit 2 selects one of the word lines WL 0 and WL 1 according to an externally-input address. The row selection circuit 2 drives the word line WL with a delay time that is longer than the delay time of the bit line BL exhibited when the word line WL is vertically raised. An operation and a configuration of the row selection circuit 2 are explained later in detail. The column selection circuit 3 selects one of the bit-line pairs (BLB 0 and BLT 0 , or BLB 1 and BLT 1 ) according to an externally-input address.

The writing circuit 4 writes data according to a write signal Di into one of the memory cells MC 00 , MC 01 , MC 10 and MC 11 . The reading circuit 5 outputs data stored in the memory cells MC 00 , MC 01 , MC 10 or MC 11 as a read signal Do.

A configuration of each memory cell MC is explained hereinafter with reference to FIG. 2 . FIG. 2 shows a configuration of each memory cell MC. As shown in FIG. 2 , the memory cell includes load transistors MCP 0 and MCP 1 each composed of a PMOS, drive transistors MCN 0 and MCN 1 each composed of an NMOS, and access transistors MCN 2 and MCN 3 each composed of an NMOS.

The load transistor MCP 0 and the drive transistor MCN 0 constitute an inverter, and the load transistor MCP 1 and the drive transistor MCN 1 constitute another inverter.

The gate of the load transistor MCP 0 is connected to the gate of the drive transistor MCN 0 . The drain of the load transistor MCP 0 is connected to the source of the drive transistor MCN 0 . The connection point between the load transistor MCP 0 and the drive transistor MCN 0 is defined as a node NDB.

The gate of the load transistor MCP 1 is connected to the gate of the drive transistor MCN 1 . The drain of the load transistor MCP 1 is connected to the source of the drive transistor MCN 1 . The connection point between the load transistor MCP 1 and the drive transistor MCN 1 is defined as a node NDT.

The node NDB is connected to the gates of the load transistor MCP 1 and drive transistor MCN 1 . The node NDT is connected to the gates of the load transistor MCP 0 and drive transistor MCN 0 . In this way, a flip-flop is formed. This flip-flop retains data.

The source of the access transistors MCN 2 is connected to the Bar bit line BLB and the drain is connected to the node NDB. Further, the gate of the access transistors MCN 2 is connected to the word line WL. The source of the access transistors MCN 3 is connected to the True bit line BLT and the drain is connected to the node NDT. Further, the gate of the access transistors MCN 3 is connected to the word line WL.

Next, an operation of the semiconductor storage device 10 is explained hereinafter with reference to FIG. 3 . FIG. 3 is a timing chart for explaining an operation of the semiconductor storage device 10 .

(1) Pre-Charge Period

Firstly, all the bit-line pairs (BLB 0 and BLT 0 , and BLB 1 and BLT 1 ) are pre-charged to the power-supply potential VDD, and one of the bit-line pairs is selected by the column selection circuit 3 according to an address. In this example, assume that the bit-line pair (BLB 0 and BLT 0 ) is selected, and that the bit-line pair (BLB 1 and BLT 1 ) is not selected.

(2) Write Period

After the pre-charge, a write signal Di is applied and the word line WL 0 is thereby brought to a High level. Therefore, memory cells MC 00 and MC 10 are selected. In this way, the memory cell MC 00 is connected to the bit-line pair (BLB 0 and BLT 0 ), and the memory cell MC 10 is connected to the bit-line pair (BLB 1 and BLT 1 ).

The writing circuit 4 discharges the bit line BLB 0 to a Low level according to the write signal Di (which is “1” in this case), and maintains the bit line BLT 0 in the pre-charged state. As a result, data “1” is written into the memory cell MC 00 .

Note that since the non-selected bit-line pair (BLB 1 and BLT 1 ) is in the pre-charged state, the bit line BLT 1 is discharged to a Low level and bit line BLB 1 is maintained at the VDD level in the pre-charged state according to the data stored in the memory cell MC 10 (which is “0” in this case). That is, the memory cell MC 10 is brought into the pseudo-read state, in which although the cell-access is carried out, the stored data is not output.

Further, since the non-selected word line WL 1 is at the Low level, the non-selected memory cells MC 01 and MC 11 are disconnected from the bit-line pairs (BLB 0 and BLT 0 , and BLB 1 and BLT 1 ) Therefore, the non-selected memory cells MC 01 and MC 11 are not brought into a pseudo-read state, and needless to say, no data is written into those non-selected memory cells.

(3) Pre-Charge Period

After that, in the next pre-charge period, all the bit-line pairs (BLB 0 and BLT 0 , and BLB 1 and BLT 1 ) are pre-charged to the power-supply potential VDD again.

(4) Read Period

Then, one of the word lines WL is selected by the row selection circuit 2 . In this example, the word line WL 0 becomes a High level; the memory cells MC 00 and MC 10 are selected; the memory cell MC 00 is connected to the bit-line pair (BLB 0 and BLT 0 ); and the memory cell MC 10 is connected to the bit-line pair (BLB 1 and BLT 1 ).

Since data “1” is stored in the memory cell MC 00 , which is connected to the bit-line pair (BLB 0 and BLT 0 ) selected by the column selection circuit 3 , the bit line BLB 1 is discharged to a Low level and the bit line BLT 0 is maintained at the VDD level in the pre-charged state. Then, Do=“1” is output from the reading circuit 5 .

In this exemplary embodiment of the present invention, the row selection circuit 2 drives, in the read operation, a word line to the set potential at a drive speed slower than the discharge speed of the bit line exhibited when the word line is raised roughly vertically to the set potential.

Note that since it is at the VDD level in the pre-charged state, the bit line BLT 1 is discharged to a Low level and bit line BLB 1 is maintained at the VDD level in the pre-charged state according to the data stored in the memory cell MC 10 (which is “0” in this case). That is, the memory cell MC 10 is brought into the pseudo-read state.

Further, since the non-selected word line WL 1 is at the Low level, the non-selected memory cells MC 01 and MC 11 are disconnected from the bit-line pairs (BLB 0 and BLT 0 , and BLB 1 and BLT 1 ). Therefore, the non-selected memory cells MC 01 and MC 11 are not brought into a pseudo-read state, and needless to say, no data is written into those non-selected memory cells.

(5) Pre-Charge Period

After that, all the bit-line pairs (BLB 0 and BLT 0 , and BLB 1 and BLT 1 ) are pre-charged to VDD again. In the manner described above, data writing to and data reading from the SRAM are performed.

Driving of a selected word line WL is explained hereinafter with reference to FIG. 4 . FIG. 4 is a diagram for explaining an operation of the semiconductor storage device 10 during a read operation.

In the semiconductor storage device 10 shown in FIG. 2 , when a world line WL at a Low level in a non-selected state is selected and changed to a High level, the access transistors MCN 2 and MCN 3 are turned on and the cell nodes NDB and NDT are electrically connected to the bit lines BLB and BLT, respectively, which have been pre-charged to VDD. In this way, the potential at the node NDB that has retained a Low level rises.

Each of the access transistors MCN 2 and MCN 3 is composed of an NMOS. Letting VWL and Vta stand for the word line voltage and the threshold voltage of the access transistors MCN 2 respectively, a high voltage equal to or higher than VWL-Vta is never applied to the cell node NDB retaining a Low level. As shown in FIG. 4 , by adding a delay to the rising speed of the selected word line WL, the potential rising speed of the cell node NDB is delayed.

In this way, the amount of potential change (Vnd) at the cell node NDB becomes a smaller value (lower voltage) in comparison to the case where the rise of the selected word line WL is not delayed. Therefore, it becomes possible to make Vnd smaller than the logic threshold voltage Vth 1 of the cell inverters (MCP 1 and MCN 1 ), and thereby to prevent the corruption of stored data (SNM failure) due to the inversion of the cell inverters.

FIG. 5A shows potential changes of the bit line BL and the node ND retaining the data of the memory cell MC in a case where the rising speed of the word line WL involves no delay and the word line WL is thereby raised roughly vertically. FIG. 5B shows potential changes of the bit line BL and the node ND in the case where a delay is added to the rising speed of the word line WL.

As shown in FIG. 5A , the delay time in the discharging of the bit line BL in the case where the word line WL is raised roughly vertically is represented by tdBL 0 . Further, the amount of potential change at the node ND retaining the data of the memory cell in this case is represented by Vnd 0 . As shown in FIG. 5B , the rising delay time of the word line WL in the case where a delay is added to the rising of the word line is represented by tdWL. Further, the amount of potential change at the node ND retaining the data of the memory cell in this case is represented by Vnd.

FIG. 6 shows a result of a simulation of the amount of potential change Vnd at the cell node NDB in the case where a delay is added to the rising of the selected word line WL. In FIG. 6 , the horizontal axis represents rising delays (tdWL) of the word line WL normalized by the discharge delay (tdBL 0 ) of the bit line BL. Further, the vertical axis represents amounts of potential change Vnd at the cell node normalized by the cell node Vnd 0 in the case where the delay in the word line WL is not introduced.

As shown in FIG. 6 , the amount of potential change at the cell node (Vnd/Vnd 0 ) decreases as the delay in the rising of the word line WL (tdW 1 /tdBL 0 ) increases. From this, it is obvious that the operation margin increases. In this manner, by adding a delay to the rising speed of the selected word line WL, the SNM can be improved (increased SNM).

Note that it is preferable to add a delay that is at least three times the discharging delay of the bit line BL to the rising of the selected word line WL as shown in FIG. 6 . In this way, a large SNM is achieved, and therefore it is very effective to make an improvement against the SNM failure.

FIGS. 7 and 8 show configuration examples of a row selection circuit 2 used in the semiconductor storage device 10 in accordance with this exemplary embodiment. The circuit shown in FIG. 7 includes a row selection circuit 2 , an NOR circuit 21 , an inverter 22 , a PMOS (P 11 ), an NMOS (N 11 ). The NOR circuit 21 decodes an input address. The signal output from the NOR circuit 21 is input to the inverter 22 .

The signal output from the inverter 22 is input to the PMOS (P 11 ) and the NMOS (N 11 ). A power-supply potential VDD is supplied to the source of the PMOS (P 11 ). The drain of the PMOS (P 11 ) is connected to the source of the NMOS (N 11 ). A word line WL is connected to the connection point between the PMOS (P 11 ) and the NMOS (N 11 ).

The PMOS (P 11 ) is designed such that its driving capability becomes lower than that of the NMOS (N 11 ). That is, the width W of the PMOS (P 11 ) is narrower than the width that would be designed so that the driving capabilities of the PMOS (P 11 ) and the NMOS (N 11 ) are roughly equal to each other. In this way, the rising speed of the selected word line WL can be controlled.

The row selection circuit 2 shown in FIG. 8 includes a row selection circuit 2 , an NOR circuit 21 , an inverter 22 , PMOSs (P 21 and P 22 ), an NMOS (N 21 ). The signal output from the inverter 22 is input to the PMOS (P 22 ) and the NMOS (N 21 ). The drain of the PMOS (P 22 ) is connected to the source of the NMOS (N 11 ). A word line WL is connected to the connection point between the PMOS (P 11 ) and the NMOS (N 11 ).

The source of the PMOS (P 22 ) is connected to the drain of the PMOS (P 21 ). A power-supply potential VDD is supplied to the source of the PMOS (P 21 ). The gate of the PMOS (P 21 ) is connected to a VRP voltage generation circuit 6 . The VRP voltage generation circuit 6 generates a gate potential VRP of the PMOS (P 21 ). By setting the gate potential VRP, which is generated by the VRP voltage generation circuit 6 , to an arbitrary intermediate potential, the rising speed of the selected word line WL can be set.

Second Exemplary Embodiment

Another exemplary embodiment will be described hereinafter. An operation of a semiconductor storage device in accordance with a second exemplary embodiment of the present invention is explained hereinafter with reference to FIG. 9 . FIG. 9 is a timing chart for explaining an operation of a semiconductor storage device in accordance with this exemplary embodiment. In the semiconductor storage device in accordance with this exemplary embodiment, a test to increase the operation margin in the normal operating state is carried out. Note that in FIG. 9 , test signals TESTB and TEST input to the row selection circuit 2 , which are described later with reference FIGS. 10 and 11 , are collectively represented.

Further, in this exemplary embodiment, the word line WL is driven while adding a delay to the rising speed of the word line WL so that the SNM failure can be avoided as in the case of the first exemplary embodiment. Carrying out a normal reading/writing operation is defined as a normal operation.

In this exemplary embodiment, the delay of the rising speed of the selected word line WL during a test (period in which the test signal TEST: High, and the test signal TESTB: Low) is smaller than that of the normal operating state (during a normal reading/writing operation). In FIG. 9 , the rising of the selected word line WL during the normal operation is represented by a broken line, and the rising of the selected word line WL during a test is represented by a solid line.

As can be seen from FIG. 9 , in a test in which the rising speed of the selected word line WL during the test is set to a small value, the amount of potential change Vnd at the cell node NDB becomes larger to the high-voltage side in comparison to the normal operating state. Therefore, during the test, the semiconductor storage device can be operated in a state where the operation margin of the memory cell MC (logic threshold voltage: Vth 1 -Vnd of the cell inverters (MCP 1 and MCN 1 )) is smaller than that of the normal operating state.

For a semiconductor storage device which operates properly in this test, i.e., for which Vnd is smaller than the logic threshold voltage: Vth 1 of the cell inverters (MCP 1 and MCN 1 ), proper operations with a margin is ensured. Note that the margin that can be ensured by this test is a shift amount (shift voltage) of Vnd in the test state.

By constructing the row selection circuit 2 from, for example, a circuit shown in FIG. 10 or 11 , the delay of the rising speed of the selected word line WL during a test can be set to a smaller value than that of the normal operating state. FIGS. 10 and 11 show configuration examples of the row selection circuit 2 used in a semiconductor storage device in accordance with this exemplary embodiment.

The circuit shown in FIG. 10 is formed by adding PMOSs (P 32 and P 33 ) to the circuit shown in FIG. 7 . The gate of the PMOS (P 33 ) is connected to the output of the inverter 22 . The drain of the PMOS (P 33 ) is connected to the word line WL, and the source is connected to the drain of the PMOS (P 32 ). A power-supply potential is supplied to the source of the PMOS (P 32 ), and a test signal TESTB is input to the gate of the PMOS (P 32 ).

During the normal operation, the PMOSs (P 32 and P 33 ), which are connected in series, and the PMOS 11 simultaneously drive the word line WL. During the test, the test signal TESTB becomes a Low level, and therefore the PMOS (P 32 and P 33 ) do not operate. In this way, the delay of the rising speed of the selected word line WL can be set to a smaller value than that of the normal operating state.

Further, the circuit shown in FIG. 11 has a similar structure to that of the circuit shown in FIG. 8 . A test signal TEST is input to the VRP voltage generation circuit 6 . During a test (period in which the input test signal TEST is at a High level), the gate voltage VRP is set to a lower voltage than that of the normal operating state. As a result, it is possible to set the driving capability of the PMOS (P 21 ) during a test to a larger quantity than that of the normal operating state, and thereby to set the delay of the rising speed of the selected word line WL to a smaller value than that of the normal operating state.

As described above, in accordance with this exemplary embodiment of the present invention, it is possible to ensure proper operations with a margin during the normal operation (normal reading/writing operation), and thereby to provide a semiconductor storage device with higher quality.

Third Exemplary Embodiment

Another exemplary embodiment will be described hereinafter. An operation of a semiconductor storage device in accordance with a third exemplary embodiment of the present invention is explained hereinafter with reference to FIG. 12 . FIG. 12 is a timing chart for explaining an operation of a semiconductor storage device in accordance with this exemplary embodiment. In this exemplary embodiment, as shown in FIG. 12 , the selected word line WL is first raised sharply and roughly vertically to the threshold voltage: Vtna of the access transistor, and then the selected word line WL is driven with a delay added to its rising speed.

The access transistors MCN 2 and MCN 3 of the memory cell MC shown in FIG. 3 is not turned on until the word line voltage reaches the threshold voltage: Vtna of the access transistor, and therefore the malfunction that would otherwise occur when the Low level at the cell node is pulled up is prevented. In accordance with this exemplary embodiment, the delay time until the selected word line WL reaches to Vtna can be reduced without compromising the SNM improvement effect, and thus enabling the operating speed of the SRAM to become higher.

By forming the row selection circuit 2 from, for example, a circuit shown in FIG. 13 , the selected word line WL can be first raised sharply to the threshold voltage: Vtna of the access transistor, and then the rising speed of the selected word line WL can be delayed after that. FIG. 13 shows a configuration example of the row selection circuit 2 used in a semiconductor storage device in accordance with this exemplary embodiment.

The circuit shown in FIG. 13 is formed by adding NMOSs (N 42 and N 43 ) and a VRN voltage generation circuit 7 to the circuit shown in FIG. 7 . The gate of the NOMS (N 43 ) is connected to the output of the NOR circuit 21 . The drain of the NMOS (N 43 ) is connected to the word line WL, and the source is connected to the drain of the NMOS (N 42 ). A power-supply potential VDD is supplied to the source of the NMOS (N 42 ), and the gate of the NMOS (N 42 ) is connected to the VRN voltage generation circuit 7 .

FIG. 14 shows an example of a configuration of a VRN voltage generation circuit 7 . As shown in FIG. 14 , the VRN voltage generation circuit 7 includes a resistor R 51 and NMOSs (N 51 and N 52 ). A power-supply potential VDD is supplied to one end of the resistor 51 . The other end of the resistor 51 is connected to the source of the NMOS (N 51 ). The drain of the NMOS (N 51 ) is connected to the source of the NMOS (N 52 ).

The gate of the NMOS (N 52 ) is connected to the connection point between the drain of the NMOS (N 51 ) and the source of the NMOS (N 52 ). The gate of the NMOS (N 51 ) is connected to the connection point between the resistor 51 and the source of the NMOS (N 51 ). A voltage VRN is output from the connection point between the resistor 51 and the source of the NMOS (N 51 ).

In the example shown in FIG. 14 , the sum of the threshold voltage of the NMOS (N 52 ): Vtn 52 and the threshold voltage of the NMOS (N 51 ): Vtn 51 is output as a voltage VRN. Note that by configuring such that the threshold voltage of the NMOS (N 51 ): Vtn 51 becomes equal to the threshold voltage of the NMOS (N 42 ): Vtn 42 , a voltage equal to the threshold voltage of the NMOS (N 52 ): Vtn 52 is output to the source of the NMOS (N 42 ).

In the case where the circuit shown in FIG. 13 is adopted as the row selection circuit 2 , when a High level is applied to the gate of the NMOS (N 43 ), the NMOS (N 43 ) is turned on and the potential of Vtn 52 can be thereby applied to the word line WL.

Note that by forming the NMOS (N 52 ) from a transistor having the same threshold voltage as that of the access transistors MCN 2 and MCN 3 of the memory cell MC, the potential of Vtna can be applied to the word line WL. In this manner, after the word line WL is raised sharply to Vtna, the word line WL can be driven to VDD while delaying its rising speed by using the PMOS (P 11 ) having a small driving capability as described above.

Fourth Exemplary Embodiment

Another exemplary embodiment will be described hereinafter. An operation of a semiconductor storage device in accordance with a fourth exemplary embodiment of the present invention is explained hereinafter with reference to FIG. 15 . FIG. 15 is a timing chart for explaining an operation of a semiconductor storage device in accordance with this exemplary embodiment. In this exemplary embodiment, as shown in FIG. 15 , a delay is added to the rising speed of the selected word line, and after the discharging of the bit line has been completed, the word line is raised sharply and roughly vertically to VDD.

As long as the discharging of the bit line BL has been completed, even if the word line WL is raised sharply, it does not lead to a malfunction. In accordance with this exemplary embodiment, after the discharging of the bit line has been completed, the word line WL is pulled up sharply to VDD so that the read period can be shortened. In addition, since the period in which the level of the word line WL is at VDD and the margin of a write operation is thereby larger can be shifted forward, a faster SRAM operation becomes possible.

By constructing the row selection circuit 2 from, for example, a circuit shown in FIG. 16 , the word line WL can be raised sharply to VDD after the discharging of the bit line BL has been completed. FIG. 16 shows a configuration example of the row selection circuit 2 used in a semiconductor storage device in accordance with this exemplary embodiment.

The circuit shown in FIG. 16 is formed by adding a bit-line discharge signal generation circuit 8 to the circuit shown in FIG. 10 . The gate of the PMOS (P 32 ) is connected to the bit-line discharge signal generation circuit 8 . The bit-line discharge signal generation circuit 8 generates a bit-line discharge signal BDS that is used to raise the word line WL roughly vertically to a set potential VDD after the bit line BL is discharged. For example, a bit-line discharge signal BDS that becomes a Low level after the discharging of the bit line has been completed is output.

FIGS. 17 and 18 show configuration examples of a bit-line discharge signal generation circuit 8 . The circuit shown in FIG. 17 includes a PMOS (P 61 ), NMOSs (N 61 and N 62 ) constituting a dummy cell 81 , a dummy capacitance 82 , and inverters 83 and 84 . Transistors having a similar structure to that of the access transistor and the driver transistor of the memory cell MC are used for the NMOSs (N 61 and N 62 ) constituting the dummy cell 81 .

The PMOS (P 61 ) and the NMOS (N 61 ) constitute an inverter. A power-supply potential VDD is supplied to the source of the PMOS (P 61 ). The drain of the NMOS (N 61 ) is connected to the source of the NMOS (N 62 ). The gates of the NMOS (N 61 ) and PMOS (P 61 ) are connected together, and a PRB signal is input to these gates. A power-supply potential VDD is supplied to the gate of the NMOS (N 62 ). A dummy bit line DBL is connected to the connection point between the PMOS (P 61 ) and the NMOS (N 61 ). Two inverters 83 and 84 are also connected to the dummy bit line DBL.

A dummy capacitance 82 is disposed between the connection point of the PMOS (P 61 ) and the NMOS (N 61 ), and the inverter 83 . Further, one end of the dummy capacitance 82 is connected to the dummy bit line DBL. The capacitance value of the dummy capacitance 82 is set to a larger value than that of the bit line BL. In this exemplary embodiment, two dummy cells are provided. With the structure like this, it is possible to generate a bit-line discharge signal that is delayed by an amount equivalent to the time necessary to discharge the bit line.

The circuit shown in FIG. 18 is formed by adding a delay circuit 85 between the inverters 83 and 84 in the circuit shown in FIG. 17 . Note that FIG. 18 shows an example where one capacitor is provided as the dummy capacitance 82 .

In this bit-line discharge signal generation circuit 8 , the potential of the dummy bit line DBL is detected by the inverter composed of the PMOS (P 61 ) and NMOS (N 61 ), and after the discharging of the bit line BL has been completed (the bit line BL becomes 0 V), it is inverted at earlier timing. In this exemplary embodiment, the bit-line discharge signal can be generated, by the delay circuit 85 , after the bit line BL is discharged.

FIG. 19 shows a timing chart for explaining an operation of a semiconductor storage device in the case where a bit-line discharge signal generation circuit shown in FIG. 17 or 18 is adopted. FIG. 19 collectively shows the potential change of the dummy bit line DBL of the bit-line discharge signal generation circuit 8 shown in FIG. 17 and the potential change of the dummy bit line DBL of the bit-line discharge signal generation circuit 8 shown in FIG. 18 .

As shown in FIG. 19 , regardless of which of the bit-line discharge signal generation circuits 8 shown in FIGS. 17 and 18 is used, the potential of a dummy bit line DBL falls when a PRB signal becomes a High level. After that, when the bit line BL is discharged, a bit-line discharge signal BDS changes from a High level to a Low level. In response to this, the word line WL can be raised roughly vertically as shown in FIG. 15 .

Fifth Exemplary Embodiment

Another exemplary embodiment will be described hereinafter. A configuration of a semiconductor storage device in accordance with a fifth exemplary embodiment of the present invention is explained hereinafter with reference to FIG. 20 . FIG. 20 shows a configuration of a semiconductor storage device in accordance with this exemplary embodiment. As shown in FIG. 20 , a semiconductor storage device in accordance with this exemplary embodiment includes a memory cell array 1 , a row selection circuit 2 , a column selection circuit 3 , a writing circuit 4 , and a reading circuit 5 .

In this exemplary embodiment, the memory cell array 1 includes sub sense amplifiers (sub SA 0 , sub SA 1 , sub SA 2 , and sub SA 3 ). Bit-line pairs (BLB 0 and BLT 0 , BLB 1 and BLT 1 , BLB 2 and BLT 2 , and BLB 3 and BLT 3 ) are connected to the respective sub sense amplifiers (sub SA 0 , sub SA 1 , sub SA 2 , and sub SA 3 ). That is, the bit-line pairs are divided for each of the sub sense amplifiers. In this way, the delay in the discharging of the bit line can be reduced.

In the semiconductor storage device 10 including a memory array 1 capable of reducing the discharge delay of the bit line like this, by using the previously-described circuit capable of controlling the rising speed of the selected word line WL by adding a delay (e.g., FIGS. 7 , 8 , 10 and 11 ) as a row selection circuit 2 , the operation of the semiconductor storage device can be made faster without compromising the SNM improvement effect.

As shown in FIG. 6 , by adding a delay, which is at least three times of the discharge delay of the bit line exhibited when no WL delay is set and the word line WL is thereby raised roughly vertically, to the rising of the selected word line WL, a significant improvement effect against the SNM failure can be achieved. However, in accordance with this exemplary embodiment, by making the bit-line discharge delay smaller, a similar improvement effect against the SNM failure can be achieved even when the delay of the rising speed of the selected word line WL is made smaller.

Since an improvement can be made against the SNM failure without deteriorating the writing characteristic, both an excellent reading operation and writing operation of the SRAM can be achieved. Therefore, it is possible to provide an SRAM that operates with stability. Further, without compromising the above-mentioned advantageous effect, improvements of the SRAM quality by an SNM test and speed-up of the SRAM can be also realized.

As has been explained so far, in accordance with this exemplary embodiment of the present invention, by adding a delay to the rising speed of the selected word line WL, the rise of the Low level retained by the cell node of the memory cell can be reduced. Therefore, both excellent reading/writing operations can be achieved.

Note that the present invention is not limited to the above-described exemplary embodiments, and various modifications can be made as appropriate without departing from the spirit and scope of the present invention.

The first to fifth exemplary embodiments can be combined as desirable by one of ordinary skill in the art.

While the invention has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with various modifications within the spirit and scope of the appended claims and the invention is not limited to the examples described above.

Further, the scope of the claims is not limited by the exemplary embodiments described above.

Furthermore, it is noted that, Applicant's intent is to encompass equivalents of all claim elements, even if amended later during prosecution.