Integrated circuits including an equalizer and operating methods thereof

The present disclosure relates generally to the field of semiconductor circuits, and more particularly, to integrated circuits including an equalizer and operating methods thereof.

Universal Serial Bus (USB) is a standard that is established for communication between devices, such as a personal computer and a portable hard disk. The communication of the devices is through a cable. After passing through the cable, signals may decay during a high frequency operation. To compensate the signal decay, equalizers have been disposed at a receiver of each device to boost the signals during the high frequency operation.

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the numbers and dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic drawing illustrating an exemplary integrated circuit including a differential amplifier and a circuit that is configured to provide a negative impedance to the differential amplifier.

FIG. 2 is a schematic drawing illustrating another exemplary integrated circuit including a differential amplifier coupled with a pair of cross-coupled transistors.

FIG. 3A is a schematic drawing showing a relationship between a signal frequency and a ratio V out /V in .

FIG. 3B is a schematic drawing showing a relationship between the signal frequency and the ratio V out /V in if the current of the current source I CC is decreased.

FIG. 3C is a schematic drawing showing a relationship between the signal frequency and the ratio V out /V in if the current of the current source I CC is increased.

FIG. 4 is a schematic drawing illustrating a system including an exemplary integrated circuit disposed over a substrate board.

Conventionally, an equalizer has first resistors and first capacitors coupled to output ends of the equalizer. Each first resistor has a resistance R L and each first capacitor has a capacitance C L . The equalizer further has NMOS transistors. Drains of the NMOS transistors are coupled to the output ends of the equalizer. Each source of the NMOS transistors is coupled to a current source. Gates of the NMOS transistors are coupled to input ends of the equalizer. A second resistor and a second capacitor are disposed in parallel between the NMOS transistors. The second resistor has a resistance R S and the second capacitor has a capacitance C S .

The equalizer receives an input signal having an amplitude V in for outputting an output signal having an amplitude V out . An equalization transfer function can be expressed as below:

V out V in = g m ⁢ ⁢ 1 ⁢ R L 1 + g m ⁢ ⁢ 1 ⁢ R S 2 · 1 + R s ⁢ C s ⁢ s ( 1 + R s ⁢ C s ⁢ s 1 + g m ⁢ ⁢ 1 ⁢ R s 2 ) ⁢ ( 1 + R L ⁢ C L ⁢ s )

wherein g m1 represents a transconductance of one of the NMOS transistors and s represents a radial frequency. A zero w z1 is equal to 1/R S C S . A real pole w p1 is equal to

( 1 + g m ⁢ ⁢ 1 ⁢ R s 2 ) / R s ⁢ C s

and another real pole w p2 is equal to 1/R L C L .

Generally, currents of the current sources are adjusted to control the operation of the equalizer. It is found that the direct current (DC) gain

( g m ⁢ ⁢ 1 ⁢ R L 1 + g m ⁢ ⁢ 1 ⁢ R s 2 )

of the equalizer is substantially independent from the change of the currents. It is also found that adjusting the currents of the current sources can only change the real pole w p1 .

It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features.

Embodiments of the present disclosure are directed to integrated circuits including a differential amplifier coupled with a circuit. The circuit does not include a resistor-capacitor (RC) network. The circuit can provide a negative impedance to the differential amplifier. By adjusting the negative impedance, a direct current (DC) gain of the integrated circuit can be changed. Other embodiments of the disclosure are directed to methods of operating the integrated circuit.

FIG. 1 is a schematic drawing illustrating an exemplary integrated circuit including a differential amplifier and a circuit that is configured to provide a negative impedance to the differential amplifier. In FIG. 1 , an integrated circuit 100 can include a differential amplifier 110 coupled with a circuit 120 . In some embodiments, the integrated circuit 100 can include an equalizer, such as a continuous-time equalizer. The integrated circuit 100 can compensate a loss of an input signal during a high-frequency operation.

Referring to FIG. 1 , the differential amplifier 110 can include at least one input end, e.g., input ends 110 a and 110 b , and at least one output end, e.g., output ends 110 c and 110 d . The input ends 110 a and 110 b can receive an input signal that has an amplitude V in . The output end 110 c and 110 d can output an output signal that has an amplitude V out . The integrated circuit 100 can output the output signal corresponding to the input signal.

The circuit 120 can be coupled with the differential amplifier 110 . In some embodiments, the circuit 120 can be coupled with the output ends 110 c and 110 d of the differential amplifier 110 . As noted, the circuit 120 does not include a resistor-capacitor (RC) network. Without any RC network in the circuit 120 , the size of the circuit 120 can be desirably reduced. It is also noted that the circuit 120 can provide a negative impedance to the differential amplifier 110 for adjusting a DC gain of the integrated circuit 100 . By adjusting the DC gain, the input signal can be desirably boosted during a high-frequency operation.

In some embodiments, the differential amplifier 110 can include resistors R 1 and R 2 coupled with the output ends 110 c and 110 d , respectively. The resistors R 1 and R 2 can also be coupled with a voltage source, e.g., a voltage source V DD . In some embodiments, the resistors R 1 and R 2 can be adjustable resistors. In other embodiments, the resistors R 1 and R 2 can have the same resistance. Each of the resistors R 1 and R 2 can have a resistance R L .

The differential amplifier 110 can include capacitors C 1 and C 2 coupled with the output ends 110 c and 110 d , respectively. The capacitors C 1 and C 2 can also be coupled with a voltage source, e.g., voltage source V SS or ground. In some embodiments, the capacitors C 1 and C 2 can have the same capacitance. Each of the capacitors C 1 and C 2 can have a capacitance C L .

The differential amplifier 110 can include transistors M 1 and M 2 coupled with the output ends 110 c and 110 d , respectively. In some embodiments, the transistors M 1 and M 2 can be, for example, NMOS transistors. Drain sides of the transistors M 1 and M 2 can be coupled with the output ends 110 c and 110 d , respectively. Gates of the transistors M 1 and M 2 can be coupled with the input ends 110 a and 110 b , respectively. In some embodiments, the transistors M 1 and M 2 can have the same transconductance. Each of the transistors M 1 and M 2 can have a transconductance g m1 . It is noted that the type of the transistors M 1 and M 2 described above in conjunction with FIG. 1 are merely exemplary. For example, the transistors M 1 and M 2 can be PMOS transistors.

The differential amplifier 110 can include a resistor R 3 and a capacitor C 3 coupled between the transistors M 1 and M 2 . The resistor R 3 can be disposed in parallel with the capacitor C 3 . In some embodiments, the resistor R 3 can be an adjustable resistor. The resistor R 3 can have a resistance R S and the capacitor C 3 can have a capacitance C S .

Referring again to FIG. 1 , the differential amplifier 110 can include at least one current source, e.g., current sources I S1 and I S2 . The current sources I S1 and I S2 can be coupled with the transistors M 1 and M 2 , respectively. By adjusting currents of the current sources I S1 and I S2 , the transconductance g m1 of the transistor M 1 or M 2 can be changed. It is noted that the differential amplifier 110 described above in conjunction with FIG. 1 is merely exemplary. Any suitable amplifier or other type differential amplifier can be used to replace the differential amplifier 110 . It is also noted that the number and dispositions of the resistors, capacitors, and transistors of the differential amplifier 110 are merely exemplary. The scope of this application is not limited thereto.

FIG. 2 is a schematic drawing illustrating another exemplary integrated circuit including a differential amplifier coupled with a pair of cross-coupled transistors. Items of FIG. 2 that are the same or similar items in FIG. 1 are indicated by the same reference numerals, increased by 100. In FIG. 2 , an integrated circuit 200 can include a differential amplifier 210 coupled with a circuit 220 . In this embodiment, the circuit 220 can include a pair of cross-coupled transistors or any circuit that can provide a negative impedance to the differential amplifier 210 . The pair of cross-coupled transistors can include transistors M 3 and M 4 . In some embodiments, the transistors M 3 and M 4 can be NMOS transistors. Source ends of the transistors M 3 and M 4 are free from being coupled to an RC network. The transistors M 3 and M 4 can have the same transconductance g m2 . The transistors M 3 and M 4 can be disposed in parallel with the resistors R 1 and R 2 , respectively. The transistors M 3 and M 4 can be coupled with output ends 210 c and 210 d of the differential amplifier 210 , respectively. It is noted that the type of the transistors M 3 and M 4 are merely exemplary. For example, the transistors M 3 and M 4 can be PMOS transistors.

Referring again to FIG. 2 , the transistors M 3 and M 4 can be coupled with only a current source I CC . As noted, the circuit 220 does not include a resistor-capacitor (RC) network. In some embodiments, the circuit 220 essentially consists of the cross-coupled transistors and the current source I CC . The source ends of the transistors M 3 and M 4 are directly coupled to the current source I CC . By adjusting the current of the current source I CC , the transconductance g m2 of the transistors M 3 and M 4 can be adjusted. The negative impedance (−1/g m2 ) of the circuit 220 applied to the differential amplifier 210 can be adjusted.

As noted, the input ends 210 a and 210 b can receive the input signal having the amplitude V in . By applying the negative impedance (−1/g m2 ) from the circuit 220 to the differential amplifier 210 , the output ends 210 c and 210 d can output the output signal having the amplitude V out . By adjusting the negative impedance, the DC gain of the integrated circuit 200 can be changed.

It is found that the amplitudes V in and V out of the input and output signals, respectively, can have a ratio (V out /V in ) that can be described below in formula (1). The formula (I) can be referred to as an equalization transfer function.

Wherein, g m1 represents the transconductance of the transistor M 1 or M 2 , g m2 represents the transconductance of the transistor M 3 or M 4 , R L represents the resistance of the resistor R 1 or R 2 , R S represents the resistance of the resistor R 3 , C L represents the capacitance of the capacitor C 1 or C 2 , C S represents the resistance of the capacitor C 3 , and s represents a radial frequency.

FIG. 3A is a schematic drawing showing a relationship between a signal frequency and the ratio V out /V in . In FIG. 3A , if the signal frequency is 0, the DC gain (A 1 ) of the integrated circuit 200 can be substantially equal to

g m ⁢ ⁢ 1 ⁢ R L 1 - g m ⁢ ⁢ 2 ⁢ R L 1 + g m ⁢ ⁢ 1 ⁢ R s 2 .

The equalization transfer function has only one zero and two real poles. The equalization transfer function of the circuit 200 does not include any complex pole. The zero w z1 can be substantially equal to 1/R S C S . A real pole w p1 can be substantially equal to

1 + g m ⁢ ⁢ 1 ⁢ R s 2 R s ⁢ C s

and the other real pole w p2 can be substantially equal to

1 - g m ⁢ ⁢ 2 ⁢ R L R L ⁢ C L .

As shown in FIG. 3A , the ratio V out /V in can rise after the zero w z1 , flatten after the real pole w p1 , and decay after the real pole w p2 .

FIG. 3B is a schematic drawing showing a relationship between the signal frequency and the ratio V out /V in if the current of the current source I CC is decreased. As noted, the decrease of the current of the current source I CC can decrease the transconductance g m2 of the transistors M 3 and M 4 . The decrease of the transconductance g m2 can increase the absolute value of the negative impedance (|−1/g m2 |). For example, if the transconductance of the transistors M 3 and M 4 is decreased from g m2 to g m2′ , the negative impedance provided from the circuit 210 (shown in FIG. 2 ) can be increased from |−1/g m2 | to |−1/g m2′ |.

Since the transconductance of the transistors M 3 and M 4 is decreased from g m2 to g m2′ , the DC gain of the integrated circuit 200 can be decreased from

g m ⁢ ⁢ 1 ⁢ R L 1 - g m ⁢ ⁢ 2 ⁢ R L 1 + g m ⁢ ⁢ 1 ⁢ R s 2 ⁢ ( A 1 ) ⁢ ⁢ to ⁢ ⁢ g m ⁢ ⁢ 1 ⁢ R L 1 - g m ⁢ ⁢ 2 ′ ⁢ R L 1 + g m ⁢ ⁢ 1 ⁢ R s 2 ⁢ ( A 2 ) .

The zero w z1 and the real pole w p1 are not changed since they are independent from the transconductance g m2 . The real pole w p2′ , can shift to a frequency

1 - g m ⁢ ⁢ 2 ′ ⁢ R L R L ⁢ C L

that is higher than that of the real pole w p2 .

FIG. 3C is a schematic drawing showing a relationship between the signal frequency and the ratio V out /V in if the current of the current source I CC is increased. The increase of the current of the current source I CC can increase the transconductance g m2 of the transistors M 3 and M 4 . The increase of the transconductance g m2 can decrease the absolute value of the negative impedance (|−1/g m2 |). For example, if the transconductance of the transistors M 3 and M 4 is increased from g m2 to g m2″ , the absolute value of the negative impedance provided from the circuit 210 can be decreased from |−1/g m2 | to |−1/g m2″ |.

Since the transconductance of the transistors M 3 and M 4 is increased from g m2 to g m2″ , the DC gain is increased from

g m ⁢ ⁢ 1 ⁢ R L 1 - g m ⁢ ⁢ 2 ⁢ R L 1 + g m ⁢ ⁢ 1 ⁢ R s 2 ⁢ ( A 1 ) ⁢ ⁢ to ⁢ ⁢ g m ⁢ ⁢ 1 ⁢ R L 1 - g m ⁢ ⁢ 2 ″ ⁢ R L 1 + g m ⁢ ⁢ 1 ⁢ R s 2 ⁢ ( A 3 ) .

The zero w z1 and the real pole w p1 are not changed since they are independent from the transconductance g m2 . The real pole w p2″ can shift to a frequency

1 - g m ⁢ ⁢ 2 ″ ⁢ R L R L ⁢ C L

that is lower than that of the real pole w p2 .

As noted, the DC gain of the integrated circuit 200 can be adjustable by merely changing the negative impedance provided from the circuit 210 . The input signal received on the input ends 210 a and 210 b can be desirably boosted during a high-frequency operation. It is found that the frequency of the real pole w p2 can be changed by adjusting the current of the current source I CC . It is also found the frequency of the real pole w p1 can be changed by adjusting the currents of the current sources I S1 and I S2 . By changing the real poles w p1 and w p2 , the bandwidth of the integrated circuit 200 can be desirably achieved.

FIG. 4 is a schematic drawing illustrating a system including an exemplary integrated circuit disposed over a substrate board. In FIG. 4 , a system 400 can include an integrated circuit 402 disposed over a substrate board 401 . The substrate board 401 can include a printed circuit board (PCB), a printed wiring board and/or other carrier that is capable of carrying an integrated circuit. The integrated circuit 402 can be similar to the integrated circuit 100 or 200 described above in conjunction with FIGS. 1 and 2 . The integrated circuit 402 can be electrically and/or thermally coupled with the substrate board 401 through bumps 405 . The system 400 can be part of an electronic system such as a computer, a display, a portable device, a cell phone, an auto vehicle, an entertainment device, or the like. In some embodiments, the system 400 including the integrated circuit 402 can provide an entire system in one IC, so-called system on a chip (SOC) or system on integrated circuit (SOIC) devices.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.