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Inventor

Tien-Chun Yang

Inventor
San Jose, CA, US

Overview

73→
Patents
2002–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 73 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores33%
H03KPulse technique15%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems9%
G05FSystems for regulating electric or magnetic variables8%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses7%
G01RMeasuring electric variables5%
G01CMeasuring distances, levels or bearings2%
H05KPrinted circuits2%
H10BElectronic memory devices2%
PatentTitleYear
10,778,203Clock generation circuit and charge pumping system202010,553,288Dynamic reference current sensing using multiple reference cells202010,483,954Clock generation circuit and charge pumping system201910,367,491Delay line circuit and method of operating the same201910,355,682Clock generation circuit and charge pumping system201910,277,118Charge pump circuit and method of operating same201910,020,064Dynamic reference current sensing using multiple reference cells20189,998,103Delay line circuit20189,966,935Latch circuit and method of operating the latch circuit20189,923,457'Regulated power converter and method of operating the same'20189,831,860Clock generation circuit20179,787,176'Charge pump'2017RE046556'Regulators regulating charge pump and memory circuits thereof'20179,666,246'Dynamic reference current sensing'2017RE046336'Phase-lock assistant circuitry'20179,584,107'Delay line circuit'20179,502,098'Method of operating a voltage regulator to reduce contention current'20169,489,989'Voltage regulators, memory circuits, and operating methods thereof'20169,455,666'Multiple frequency LC voltage controlled oscillator scheme'20169,442,506'Voltage reference circuit with temperature compensation'20169,437,257'Sensing circuit, memory device and data detecting method'2016RE046107'Integrated circuits including a charge pump circuit and operating methods thereof'20169,275,719'Voltage regulator'20169,071,242'Level shifters, methods for making the level shifters and methods of using integrated circuits'20159,054,577'Charge pump and method of biasing deep N-well in charge pump'20159,047,956'Concurrent operation of plural flash memories'20158,929,137'Operating method of memory having redundancy circuitry'20158,908,434'Operating methods of flash memory and decoding circuits thereof'20148,797,091'Integrated circuits with bi-directional charge pumps'20148,736,351'Negative charge pump'20148,710,908'Charge pump and method of biasing deep N-well in charge pump'20148,670,282'Redundancy circuits and operating methods thereof'20148,629,704'Level shifters, integrated circuits, systems, and methods for operating the level shifters'20148,575,998'Voltage reference circuit with temperature compensation'20138,575,966'Method of operating phase-lock assistant circuitry'20138,565,023'Concurrent operation of plural flash memories'20138,456,942'Regulators regulating charge pump and memory circuits thereof'20138,427,229'Integrated circuits with bi-directional charge pumps'20138,354,862'Phase-lock assistant circuitry'20138,324,960'Charge pump doubler'20128,238,178'Redundancy circuits and operating methods thereof'20128,223,576'Regulators regulating charge pump and memory circuits thereof'20128,183,913'Integrated circuits including a charge pump circuit and operating methods thereof'20128,179,162'Phase-lock assistant circuitry'20128,115,545'Automatic level control'20128,068,576'Counters and exemplary applications'20118,004,354'Automatic level control'20117,961,050'Integrated circuits including an equalizer and operating methods thereof'20117,948,820'Circuit pre-charge to sense a memory line'20117,746,706'Methods and systems for memory devices'20107,724,075'Method to provide a higher reference voltage at a lower power supply in flash memory devices'20107,505,298'Transfer of non-associated information on flash memory devices'20097,460,415'Drain voltage regulator'20087,142,454'System and method for Y-decoding in a flash memory device'20067,026,843'Flexible cascode amplifier circuit with high gain for flash memory cells'20066,944,057'Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference'20056,884,638'METHOD OF FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE BY DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING AN OVERDRIVE CURRENT MEASUREMENT TECHNIQUE AND A DEVICE THEREBY FABRICATED'20056,859,393'Ground structure for page read and page write for flash memory'20056,859,748'Test structure for measuring effect of trench isolation on oxide in a memory device'20056,856,160'Maximum VCC calculation method for hot carrier qualification'20056,825,083'Method for reducing shallow trench isolation edge thinning on thin gate oxides to improve peripheral transistor reliability and performance for high performance flash memory devices'20046,825,684'Hot carrier oxide qualification method'20046,818,462'METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A C-V MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND A DEVICE THEREBY FORMED'20046,784,682'Method of detecting shallow trench isolation corner thinning by electrical trapping'20046,759,295'METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A GATE CURRENT MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND DEVICE THEREBY FORMED'20046,756,806'Method of determining location of gate oxide breakdown of MOSFET by measuring currents'20046,734,028'Method of detecting shallow trench isolation corner thinning by electrical stress'20046,734,080'Semiconductor isolation material deposition system and method'20046,731,130'Method of determining gate oxide thickness of an operational MOSFET'20046,728,160'Path gate driver circuit'20046,593,590'Test structure apparatus for measuring standby current in flash memory devices'20036,486,682'Determination of dielectric constants of thin dielectric materials in a MOS (metal oxide semiconductor) stack'20026,472,236'Determination of effective oxide thickness of a plurality of dielectric materials in a MOS stack'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2005Patents assigned to ADVANCED MICRO DEVICES INC (16)· patent assignee history
2002–2020Based in San Jose, CA, US· patent location history
2011–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (25)· patent assignee history
2011–2016Patents assigned to YANG TIEN-CHUN (17)· patent assignee history
2012–2016Patents assigned to HUANG MING-CHIEH (11)· patent assignee history
2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (23)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG252011–2016
TAIWAN SEMICONDUCTOR MFG CO LTD232015–2020
YANG TIEN-CHUNself172011–2016
ADVANCED MICRO DEVICES INC162002–2005
HUANG MING-CHIEH112012–2016
Locations
LocationPatentsSpan
San Jose, California, US732002–2020