Method and structure of wafer level encapsulation of integrated circuits with cavity

This application is a continuation of U.S. patent application Ser. No. 12/499,029 filed Jul. 7, 2009 which claims priority to U.S. Provisional Application No. 61/079,115 filed Jul. 8, 2008, commonly assigned and incorporated by reference in its entirety for all purposes herein.

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REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAM LISTING APPENDIX SUBMITTED ON A COMPACT DISK

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The present invention is related encapsulating integrated devices. More particularly, the present invention provides a method and device using CMOS fabrication techniques for encapsulating integrated circuits with cavity. Merely by way of example, the encapsulation can be applied to RF integrated circuits, timing circuits, analog circuits, power circuits, SAW, FBAR, or any other semiconductor devices that are sensitive to ambient interference and changes.

High frequency integrated circuits such as RF and timing circuits are widely used in electronic applications to provide stable frequency selection or referencing. The stability of these circuits, however, is susceptible to EM interference, noise, moisture, corrosion, and gas from the environment.

Thus, it is desirable to improve the stability of timing circuits, RF circuits, and the like.

The present invention is related encapsulating integrated devices. More particularly, the present invention provides a method and device using CMOS fabrication techniques for encapsulating integrated circuits with cavity.

First, the integrated circuits are completed using standard IC processes. A wafer-level hermetic encapsulation is applied to form a cavity above the sensitive portion of the circuits using IC-foundry compatible processes. The encapsulation and cavity provide a hermetic inert environment that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the outside environment.

FIG. 1 is a simplified process flow of a wafer-level encapsulation of Integration Circuits according to one embodiment of the present invention;

FIG. 2 is a simplified process flow of a wafer-level encapsulation of Integration Circuits according to one embodiment of the present invention;

FIG. 3 is a simplified process flow of a wafer-level encapsulation of Integration Circuits according to one embodiment of the present invention;

FIG. 4 is a simplified process flow of a wafer-level encapsulation of Integration Circuits according to one embodiment of the present invention;

FIG. 5 is a simplified cross section of a wafer-level encapsulation of Integration Circuits according to one embodiment of the present invention; and

FIG. 6 is a simplified cross section of a wafer-level encapsulation of Integration Circuits according to one embodiment of the present invention.

FIG. 1 is a simplified process flow of a wafer-level encapsulation of Integration Circuits according to one embodiment of the present invention. As depicted, an organic sacrificial material is deposited and patterned to cover the sensitive portion of the integrated circuits. In a specific embodiment, the sacrificial material is a photo resist that is spin coated on the wafer and patterned using standard lithography methods. A thin layer of metal or amorphous silicon is then conformally deposited using a PVD process covering the surface of the wafer. A etch step is followed to form release holes in the 1st layer. Lastly, the organic sacrificial material is then removed through the release holes by a dry O2 plasma ashing step. As depicted, the removal of the sacrificial material forms a cavity and a shell of the encapsulation.

FIG. 2 is a simplified process flow of a wafer-level encapsulation of Integration Circuits according to one embodiment of the present invention. As depicted, a 2nd layer of the encapsulation is deposited onto the 1st layer. The hermetic sealing methods include PVD, spin-on, or spray-on techniques. The sealing materials include metal such as Ti, TiN, amorphous silicon, spin-on-glass, spray-on-glass, or a combination of the above. The ambient during sealing is optimized and controlled to a desired spec that defines the sensor device ambient after sealing. A getter material such as Ti can be deposited as the 1st layer of the encapsulation and activated later to achieve high vacuum and cleanness of the sensitive circuit ambient environment. After sealing the holes, an optional CVD dielectric material such as oxide or nitride can be added onto the encapsulation. Finally, a etch step opens the bond pad region and expose the bond pads for wire bonding or optional wafer bumping processes. The encapsulation and the cavity form a hermetic inert environment that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the outside environment.

FIG. 3 is a simplified process flow of a wafer-level encapsulation of Integration Circuits according to one embodiment of the present invention. For applications that require thick encapsulation layer, it is desirable to form bond pads on top of the encapsulation layer instead of etching down to open the bond pads on the IC layer. As depicted, after depositing the 2nd layer of the encapsulation, a etch step opens a region of bond pad area and expose the bond pads for a subsequent metalization step. The metal is then patterned to form bond pads for wire bonding or optional wafer bumping processes.

FIG. 4 is a simplified process flow of a wafer-level encapsulation of Integration Circuits according to one embodiment of the present invention. As depicted, an organic sacrificial material is deposited and patterned to cover the sensitive portion of the integrated circuits. The patterning also forms holes or openings in the remaining organic materials. In a specific embodiment, the sacrificial material is a photo resist that is spin coated on the wafer and patterned using standard lithography methods. A thin layer of metal or amorphous silicon is then deposited using a PVD process covering the surface of the wafer. The deposition recipe is optimized for non-conforming purpose, which has little step coverage of the sidewall of the exposed photoresist trenches. After removing the organic sacrificial material, a 2nd layer is then deposited to form the cavity and the encapsulation by steps aforementioned. This flow uses only one mask and save process steps.

FIG. 5 is a simplified cross section of a wafer-level encapsulation of Integration Circuits according to one embodiment of the present invention. As depicted, bond pad area is kept clear from encapsulation depositions by a lift-off method or using shadow mask. This eliminates the need of etching thru the encapsulation layers to expose the bond pads.

FIG. 6 is a simplified cross section of a wafer-level encapsulation of Integration Circuits according to one embodiment of the present invention. As depicted, a seal ring is formed in IC layers and encircles the sensitive portion of the integrated circuits. The 1st layer of the encapsulation is a conductive material and is electrically connected with the seal ring. As a result, the seal ring and the encapsulation form a metal cage that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the environment.

It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.