Fan out build up substrate stackable package and method

1. Field of the Invention

The present application relates to the field of electronics, and more particularly, to methods of forming electronic component packages and related structures.

2. Description of the Related Art

To reduce the size of electronic devices such as cell phones, it is desirable to minimize the thickness of electronic component packages used within the electronic devices as well as the mounting area required to mount the electronic component packages. Often, electronic component packages are stacked one upon another to reduce the mounting area required for the electronic component packages as compared to mounting the electronic component packages in a side by side arrangement. Unfortunately, stacking the electronic component packages results in an undesirable increased thickness as compared to mounting the electronic component packages in a side by side arrangement.

A fan out build up substrate stackable package includes an electronic component having an active surface including a bond pad. A package body encloses the electronic component, the package body having a first surface coplanar with the active surface of the electronic component. A buildup dielectric layer is applied to the active surface of the electronic component and the first surface of the package body. A circuit pattern is formed within the first buildup dielectric layer and electrically connected to the bond pad, the first circuit pattern including via capture pads. Via capture pad apertures extend through the package body and expose the via capture pads.

In this manner, direct connection to the first circuit pattern, i.e., the first metal layer, of the fan out build up substrate stackable package is facilitated. Further, the fan out build up substrate stackable package is extremely thin resulting in extremely thin stacked assemblies.

These and other features of the present invention will be more readily apparent from the detailed description set forth below taken in conjunction with the accompanying drawings.

FIG. 1 is a cross-sectional view of a fan out build up substrate stackable package during fabrication in accordance with one embodiment;

FIGS. 2 , 3 , 4 , 5 , 6 , 7 are cross-sectional views of the fan out build up substrate stackable package of FIG. 1 at later stages during fabrication in accordance with various embodiments;

FIGS. 8 , 9 , 10 are cross-sectional views of the fan out build up substrate stackable package of FIG. 7 at later stages during fabrication in accordance with various embodiments;

FIG. 11 is an enlarged cross-sectional view of the region XI of the fan out build up substrate stackable package of FIG. 10 in accordance with one embodiment;

FIG. 12 is an enlarged cross-sectional view of the region XI of the fan out build up substrate stackable package of FIG. 10 in accordance with another embodiment;

FIG. 13 is a cross-sectional view of a fan out build up substrate stackable package during fabrication in accordance with another embodiment;

FIGS. 14 , 15 , 16 , 17 are cross-sectional views of the fan out build up substrate stackable package of FIG. 13 at later stages during fabrication in accordance with various embodiments;

FIG. 18 is a cross-sectional view of a fan out build up substrate stackable package during fabrication in accordance with yet another embodiment;

FIGS. 19 , 20 , 21 , 22 , 23 , 24 are cross-sectional views of the fan out build up substrate stackable package of FIG. 18 at later stages during fabrication in accordance with various embodiments;

FIG. 25 is a cross-sectional view of a fan out build up substrate stackable package in accordance with another embodiment; and

FIG. 26 is a cross-sectional view of a fan out build up substrate stackable package in accordance with one embodiment.

In the following description, the same or similar elements are labeled with the same or similar reference numbers.

FIG. 1 is a cross-sectional view of a fan out build up substrate stackable package 100 during fabrication in accordance with one embodiment. Referring now to FIG. 1 , an electronic component 102 is mounted to a carrier 104 .

In one embodiment, electronic component 102 is an integrated circuit chip, e.g., an active component. However, in other embodiments, electronic component 102 is a passive component such as a capacitor, resistor, or inductor.

In accordance with this embodiment, electronic component 102 includes an active surface 106 and an opposite inactive surface 108 . Electronic component 102 further includes bond pads 110 formed on active surface 106 and sides 112 extending between active surface 106 and inactive surface 108 .

In one embodiment, carrier 104 includes an adhesive on an upper, e.g., first, surface 104 U of carrier 104 . Active surface 106 of electronic component 102 is pressed into upper surface 104 U of carrier 104 and thus sticks to carrier 104 . However, in other embodiments, an adhesive is applied to active surface 106 of electronic component 102 , and this adhesive is pressed into carrier 104 to stick electronic component 102 to carrier 104 .

FIG. 2 is a cross-sectional view of fan out build up substrate stackable package 100 of FIG. 1 at a later stage during fabrication in accordance with one embodiment. Referring now to FIG. 2 , electronic component 102 is encapsulated in a dielectric package body 214 .

Illustratively, electronic component 102 and carrier 104 are placed into a mold and mold compound is injected into the mold and around electronic component 102 . This mold compound hardens to form package body 214 . Thus, in accordance with this embodiment, package body 214 is formed of mold compound. However, in other embodiments, package body 214 is formed of other dielectric materials such as hardened liquid encapsulant.

Package body 214 includes a lower, e.g., first, surface 214 L attached to upper surface 104 U of carrier 104 and an upper, e.g., second, surface 214 U. Package body 214 completely encloses electronic component 102 including inactive surface 108 and sides 112 and the exposed portion of upper surface 104 U of carrier 104 .

Package body 214 is thicker having a thickness T1 greater than a thickness T2 of electronic component 102 . More particularly, upper surface 214 U is above and spaced apart from inactive surface 108 .

FIG. 3 is a cross-sectional view of fan out build up substrate stackable package 100 of FIG. 2 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 2 and 3 together, package body 214 is ground down from upper surface 214 U to expose inactive surface 108 of electronic component 102 . In one embodiment, inactive surface 108 is also ground down thus thinning both package body 214 and electronic component 102 . After thinning, upper surface 214 U of package body 214 and inactive surface 108 of electronic component 102 are parallel and coplanar. Although various features may be described as being parallel, coplanar, perpendicular, or having other relationships, in light of this disclosure, those of skill in the art will understand that the features may not be exactly parallel, coplanar, perpendicular, but only substantially parallel, coplanar, perpendicular to within accepted manufacturing tolerances.

Further, after grinding, package body 214 and electronic component 102 have an equal thickness T3 less than thicknesses T1, T2 prior to grinding. Thinning package body 214 and electronic component 102 minimizes the overall thickness of fan out build up substrate stackable package 100 . Generally, fan out build up substrate stackable package 100 is extremely thin resulting in extremely thin stacked assemblies. Grinding of package body 214 and electronic component 102 is optional, and in one embodiment, is not performed.

Referring now to FIGS. 2 and 3 together, package body 214 is a relatively rigid material allowing carrier 104 ( FIG. 2 ) to be removed as illustrated in FIG. 3 . In various embodiments, carrier 104 is removed by peeling, etching, grinding, or other removal technique.

Referring now to FIG. 3 , a first buildup dielectric layer 316 is applied to lower surface 214 L of package body 214 and active surface 106 of electronic component 102 including bond pads 110 . More particularly, an upper, e.g., first, surface 316 U is applied to lower surface 214 L of package body 214 and active surface 106 of electronic component 102 . First buildup dielectric layer 316 further includes a lower, e.g., second, surface 316 L.

Optionally, a dielectric backside warpage control layer 318 is applied to upper surface 214 U of package body 214 . In the case where inactive surface 108 of electronic component 102 is exposed, backside warpage control layer 318 is also applied to inactive surface 108 .

Backside warpage control layer 318 has a thermal coefficient of expansion similar or identical to first buildup dielectric layer 316 . More particularly, backside warpage control layer 318 expands and contracts at various temperatures in a similar manner to first buildup dielectric layer 316 . Accordingly, backside warpage control layer 318 offsets stress and associated warpage generated by thermal expansion and contraction of first buildup dielectric layer 316 . In this manner, backside warpage control layer 318 prevents warpage of fan out build up substrate stackable package 100 . However, formation of backside warpage control layer 318 is optional, and in one embodiment, backside warpage control layer 318 is not formed.

FIG. 4 is a cross-sectional view of fan out build up substrate stackable package 100 of FIG. 3 at a later stage during fabrication in accordance with one embodiment. Referring now to FIG. 4 , a circuit pattern artifact 420 is formed in first buildup dielectric layer 316 . Circuit pattern artifact 420 is formed using laser ablation, selective etching, or other technique.

Circuit pattern artifact 420 is a positive image of the circuit pattern to be formed in first buildup dielectric layer 316 . Circuit pattern artifact 420 includes bond pad via apertures 422 extending entirely through first buildup dielectric layer 316 and exposing bond pads 110 . Circuit pattern artifact 420 further includes trace channels 424 and via capture pad openings 426 .

FIG. 5 is a cross-sectional view of fan out build up substrate stackable package 100 of FIG. 4 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 4 and 5 together, a circuit pattern 528 , sometimes called a first circuit pattern, is formed within circuit pattern artifact 420 . In one embodiment, circuit pattern 528 , sometimes called a first metal layer, is formed by plating an electrically conductive material such as copper within circuit pattern artifact 420 . Generally, circuit pattern 528 is formed within first buildup dielectric layer 316 .

In one embodiment, circuit pattern 528 includes one or more metal layers. For example, initially a solder wettable layer such as gold is plated in circuit pattern artifact 420 to partially fill circuit pattern artifact 420 . Circuit pattern artifact 420 is then completely filled with a second metal such as copper. In this manner, the exposed surfaces of via capture pads of circuit pattern 528 are solder wettable as discussed in greater detail below.

Circuit pattern 528 includes electrically conductive bond pad vias 530 formed in bond pad via apertures 422 and electrically connected to bond pads 110 . Circuit pattern 528 further includes electrically conductive traces 532 formed within trace channels 424 and electrically conductive via capture pads 534 formed within via capture pad openings 426 . Although circuit pattern 528 is set forth as containing particular features, e.g., bond pad vias 530 , traces 532 , and via capture pads 534 , in light of this disclosure, those of skill in the art will understand that a circuit pattern can be formed with other and/or different features depending on the particular signal routing desired. Further, instead of being embedded inside of first buildup dielectric layer 316 , in another embodiment, traces 532 are formed on lower surface 316 L of first buildup dielectric layer 316 .

FIG. 6 is a cross-sectional view of fan out build up substrate stackable package 100 of FIG. 5 at a later stage during fabrication in accordance with one embodiment. Referring now to FIG. 6 , an upper, e.g., first, surface 636 U of a second buildup dielectric layer 636 is applied to lower surface 316 L of first buildup dielectric layer 316 and to circuit pattern 528 .

A circuit pattern artifact 638 is formed in a lower, e.g., second, surface 636 L of second buildup dielectric layer 636 . Circuit pattern artifact 638 is formed using laser ablation, selective etching, or other technique.

Circuit pattern artifact 638 is a positive image of the circuit pattern to be formed in second buildup dielectric layer 636 . Circuit pattern artifact 638 includes blind via apertures 640 extending entirely through second buildup dielectric layer 636 and exposing circuit pattern 528 . Circuit pattern artifact 638 further includes trace channels 642 and land openings 644 .

FIG. 7 is a cross-sectional view of fan out build up substrate stackable package 100 of FIG. 6 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 6 and 7 together, a circuit pattern 746 is formed within circuit pattern artifact 638 . In one embodiment, circuit pattern 746 is formed by plating an electrically conductive material such as copper within circuit pattern artifact 638 . In another embodiment, circuit pattern 746 includes one or more metal layers. Generally, circuit pattern 746 , sometimes called a second circuit pattern, is formed within second buildup dielectric layer 636 .

Circuit pattern 746 includes electrically conductive circuit pattern vias 748 formed in blind via apertures 640 and electrically connected to circuit pattern 528 . Circuit pattern 746 further includes electrically conductive traces 750 formed in trace channels 642 and electrically conductive lands 752 formed in land openings 644 . Although circuit pattern 746 is set forth as containing particular features, e.g., circuit pattern vias 748 , traces 750 , and lands 752 , in light of this disclosure, those of skill in the art will understand that a circuit pattern can be formed with other and/or different features depending on the particular signal routing desired. Further, instead of being embedded inside of second buildup dielectric layer 636 , in another embodiment, traces 750 and lands 752 are formed on lower surface 636 L of second buildup dielectric layer 636 .

FIG. 8 is a cross-sectional view of fan out build up substrate stackable package 100 of FIG. 7 at a later stage during fabrication in accordance with one embodiment. Referring now to FIG. 8 , a dielectric solder mask 854 is applied to lower surface 636 L of second buildup dielectric layer 636 and patterned to expose lands 752 of circuit pattern 746 .

Interconnection balls 856 , e.g., solder, are formed on lands 752 . Interconnection balls 856 are distributed in a ball grid array (BGA) in one embodiment. Interconnection balls 856 are reflowed, i.e., heated to a melt and re-solidified, to mount fan out build up substrate stackable package 100 to another structure such as a printed circuit motherboard. The formation of interconnection balls 856 is optional, and in one embodiment, interconnection balls 856 are not formed.

Further, via capture pad apertures 858 are formed, e.g., using laser ablation, through package body 214 and backside warpage control layer 318 if backside warpage control layer 318 is formed. Via capture pad apertures 858 extend through package body 214 from upper surface 214 U to lower surface 214 L and expose via capture pads 534 of circuit pattern 528 .

As set forth above, in one embodiment, the exposed surfaces of via capture pads 534 exposed through via capture pad apertures 858 include a solder wettable layer. In another embodiment, after formation of via capture pad apertures 858 , a solder wettable layer, e.g., nickel, gold, organic solderability protectant (OSP), is formed on via capture pads 534 through via capture pad apertures 858 .

As illustrated in FIG. 8 , via capture pad apertures 858 expose via capture pads 534 of circuit pattern 528 . This facilitates direct connection to circuit pattern 528 , i.e., the first metal layer, of fan out build up substrate stackable package 100 . As discussed further below, additional stacked structures such as integrated circuit dies, other active components, passive components, and/or stacked electronic component packages, are mounted to (stacked) on fan out build up substrate stackable package 100 by placing solder balls of the additional structures within via capture pad apertures 858 . The solder balls of the stacked structures are reflowed thus physically and electrically connecting the solder balls and thus the stacked structures to via capture pads 534 of circuit pattern 528 .

As illustrated in FIG. 8 , in accordance with this embodiment, backside warpage control layer 318 remains and covers the entire upper surface 214 U of package body 214 . In one embodiment, the thickness of backside warpage control layer 318 is approximately equal to the typical gap between upper surface 214 U of package body 214 and the lower surface of the stacked structure stacked upon fan out build up substrate stackable package 100 . To enhance the mounting between the stacked structure and fan out build up substrate stackable package 100 , in one embodiment, backside warpage control layer 318 includes a B-stage epoxy. This B-stage epoxy is cured during reflow mounting of the stacked structure thus bonding the stacked structure to upper surface 214 U and inactive surface 108 of electronic component 102 .

FIG. 9 is a cross-sectional view of fan out build up substrate stackable package 100 of FIG. 7 at a later stage during fabrication in accordance with another embodiment. Referring now to FIG. 9 , solder mask 854 , optional interconnection balls 856 , and via capture pad apertures 858 are formed as discussed above in reference to FIG. 8 . In accordance with this embodiment, backside warpage control layer 318 is removed from the outer periphery of upper surface 214 U of package body 214 . More particularly, backside warpage control layer 318 remains only on and covers the central region of upper surface 214 U of package body 214 inwards of via capture pad apertures 858 .

FIG. 10 is a cross-sectional view of fan out build up substrate stackable package 100 of FIG. 7 at a later stage during fabrication in accordance with yet another embodiment. Referring now to FIG. 10 , solder mask 854 , optional interconnection balls 856 , and via capture pad apertures 858 are formed as discussed above in reference to FIG. 8 . In accordance with this embodiment, backside warpage control layer 318 (see FIG. 7 ) is completely removed as illustrated in FIG. 10 .

FIG. 11 is an enlarged cross-sectional view of the region XI of fan out build up substrate stackable package 100 of FIG. 10 in accordance with one embodiment.

Referring now to FIG. 11 , as discussed above, circuit pattern 528 includes bond pad via 530 , trace 532 , and via capture pad 534 . Bond pad via 530 is electrically connected to via capture pad 534 by trace 532 .

In accordance with this embodiment, via capture pad 534 extends entirely through first buildup dielectric layer 316 but does not extend into package body 214 . Accordingly, an upper, first, surface 534 U of via capture pad 534 is parallel to and coplanar with lower surface 214 L of package body 214 and active surface 106 of electronic component 102 . Active surface 106 of electronic component 102 and lower surface 214 L of package body 214 are also parallel to and coplanar with one another.

In accordance with one embodiment, referring now to FIGS. 4 and 11 together, during formation of circuit pattern artifact 420 , via capture pad pin apertures 1160 are formed in package body 214 (via capture pad pin apertures 1160 are not illustrated in the embodiment of FIG. 4 , see FIG. 11 for example). In one embodiment, via capture pad pin apertures 1160 are cylindrical openings formed by laser ablating into package body 214 through via capture pad openings 426 . Via capture pad pin apertures 1160 extend from respective via capture pad openings 426 and into package body 214 .

Referring now to FIGS. 5 and 11 together, during formation of circuit pattern 528 , via capture pad pin apertures 1160 are filled with the electrically conductive material of circuit pattern 528 to form via capture pad pins 1162 (via capture pad pins 1162 are not illustrated in the embodiment of FIG. 5 , see FIG. 11 for example). Via capture pad pins 1162 protrude upwards from upper surfaces 534 U of via capture pads 534 and into package body 214 prior to formation of via capture pad apertures 858 . Via capture pad pins 1162 have a smaller diameter than via capture pads 534 .

Referring now to FIG. 11 , after formation of via capture pad apertures 858 , via capture pad pins 1162 protrude upwards from upper surfaces 534 U of via capture pads 534 and into via capture pad apertures 858 . During mounting of a stacked structure to fan out build up substrate stackable package 100 , via capture pad pins 1162 provide controlled collapse of the stacked structure solder balls, e.g., BGA balls. In this manner, via capture pad pins 1162 minimized the possibility of open solder joints, i.e., a failed solder connection, between the stacked structure and via capture pads 534 .

FIG. 12 is an enlarged cross-sectional view of the region XI of fan out build up substrate stackable package 100 of FIG. 10 in accordance with another embodiment. Referring now to FIG. 12 , as discussed above, circuit pattern 528 includes bond pad via 530 , trace 532 , and via capture pad 534 . Bond pad via 530 is electrically connected to via capture pad 534 by trace 532 .

In accordance with this embodiment, via capture pad 534 extends entirely through first buildup dielectric layer 316 and extends into package body 214 . Accordingly, upper surface 534 U of via capture pad 534 is parallel to but elevated above lower surface 214 L of package body 214 and active surface 106 of electronic component 102 . More particularly, upper surface 534 U of via capture pad 534 is between lower surface 214 L and upper surface 214 U of package body 214 . Via capture pad 534 is embedded into package body 214 .

In accordance with one embodiment, referring now to FIGS. 4 and 12 together, during formation of circuit pattern artifact 420 , via capture pad openings 426 are formed entirely through first buildup dielectric layer 316 and into package body 214 (via capture pad openings 426 do not extend into package body 214 in the embodiment illustrated in FIG. 4 , see FIG. 12 for example). In one embodiment, via capture pad openings 426 are formed by laser ablating into package body 214 .

Referring now to FIGS. 5 and 12 together, during formation of circuit pattern 528 , via capture pad openings 426 are filled to form via capture pads 534 . Via capture pads 534 protrude upwards and extend into package body 214 (via capture pads 534 do not protrude into package body 214 in the embodiment illustrated in FIG. 5 , see FIG. 12 for example).

Referring now to FIG. 12 , during mounting of a stacked structure to fan out build up substrate stackable package 100 , increased thickness via capture pads 534 reduce the distance into which the solder balls of the stacked structure must extend into via capture pad apertures 858 to contact capture pads 534 . In this manner, increased thickness via capture pads 534 minimized the possibility of open solder joints, i.e., a failed solder connection, between the stacked structure and via capture pads 534 . Further, increased thickness via capture pads 534 adjust the seating plane of the stacked structure to optimize the gap between fan out build up substrate stackable package 100 and the stacked structure.

Referring again to FIG. 10 , fan out build up substrate stackable package 100 includes first buildup dielectric layer 316 and second buildup dielectric layer 636 , i.e., two buildup dielectric layers. In accordance with the embodiments illustrated in FIGS. 13 , 14 , 15 , 16 , 17 , a fan out build up substrate stackable package 1300 is fabricated using only a single buildup dielectric layer and thus minimizing the overall thickness of fan out build up substrate stackable package 1300 .

FIG. 13 is a cross-sectional view of a fan out build up substrate stackable package 1300 during fabrication in accordance with another embodiment.

Referring now to FIG. 13 , an upper, e.g., first, surface 1302 U of a dielectric film 1302 is applied to active surface 106 including bond pads 110 of electronic component 102 . In one embodiment, a sheet of dielectric film 1302 is applied to a wafer comprising a plurality of electronic components 102 prior to dicing (cutting) of the wafer to form singulated electronic components 102 . This sheet of dielectric film 1302 is applied after formation of the Under Bump Metallization (UBM) and prior to wafer dicing. The wafer including sheet of dielectric film 1302 is diced to form singulated electronic components 102 each having a dielectric film 1302 attached.

As illustrated in FIG. 13 , a lower, e.g., second, surface 1302 L of dielectric film 1302 is mounted to upper surface 104 U of carrier 104 . Dielectric film 1302 further includes sides 1304 extending between upper surface 1302 U and lower surface 1302 L of dielectric film 1302 . Sides 1304 are coplanar with sides 112 of electronic component 102 .

FIG. 14 is a cross-sectional view of fan out build up substrate stackable package 1300 of FIG. 13 at a later stage during fabrication in accordance with one embodiment. Referring now to FIG. 14 , electronic component 102 and dielectric film 1302 are encapsulated in package body 214 .

Illustratively, electronic component 102 , dielectric film 1302 , and carrier 104 are placed into a mold and mold compound is injected into the mold and around electronic component 102 and dielectric film 1302 . This mold compound hardens to form package body 214 .

Package body 214 completely encloses electronic component 102 , dielectric film 1302 , and the exposed portion of upper surface 104 U of carrier 104 . More particularly, package body 214 completely encloses inactive surface 108 and sides 112 of electronic component 102 . Further, package body 214 completely encloses sides 1304 of dielectric film 1302 .

Package body 214 is thicker having a thickness T1 greater than a thickness T4 of electronic component 102 and dielectric film 1302 . More particularly, upper surface 214 U is above and spaced apart from inactive surface 108 .

FIG. 15 is a cross-sectional view of fan out build up substrate stackable package 1300 of FIG. 14 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 14 and 15 together, package body 214 is ground down from upper surface 214 U to expose inactive surface 108 of electronic component 102 . In one embodiment, inactive surface 108 is also ground down thus thinning both package body 214 and electronic component 102 .

Accordingly, after grinding, package body 214 and electronic component 102 have an equal thickness T5 less than thicknesses T1, T4 prior to grinding. Thinning package body 214 and electronic component 102 minimizes the overall thickness of fan out build up substrate stackable package 1300 . Grinding of package body 214 and electronic component 102 is optional, and in one embodiment, is not performed.

Package body 214 is a relatively rigid material allowing carrier 104 ( FIG. 14 ) to be removed as illustrated in FIG. 15 . In various embodiments, carrier 104 is removed by peeling, etching, grinding, or other removal technique.

Referring now to FIG. 15 , optionally, a backside warpage control layer 318 is applied to upper surface 214 U of package body 214 . In the case where inactive surface 108 of electronic component 102 is exposed, backside warpage control layer 318 is also applied to inactive surface 108 .

FIG. 16 is a cross-sectional view of fan out build up substrate stackable package 1300 of FIG. 15 at a later stage during fabrication in accordance with one embodiment. Referring now to FIG. 16 , a circuit pattern artifact 1620 is formed in dielectric film 1302 and package body 214 . Circuit pattern artifact 1620 is formed using laser ablation in one embodiment. Circuit pattern artifact 1620 is similar or identical to circuit pattern artifact 420 of FIG. 4 except that circuit pattern artifact 1620 is formed within dielectric film 1302 and package body 214 whereas circuit pattern artifact 420 of FIG. 4 is formed in first buildup dielectric layer 316 .

Circuit pattern artifact 1620 is a positive image of the circuit pattern to be formed in dielectric film 1302 and package body 214 . Circuit pattern artifact 1620 includes bond pad via apertures 1622 extending entirely through dielectric film 1302 and exposing bond pads 110 . Circuit pattern artifact 420 further includes trace channels 1624 and via capture pad openings 1626 .

Via capture pad openings 1626 are formed within package body 214 . Trace channels 1624 are formed within both dielectric film 1302 and package body 214 . Trace channels 1624 extend between bond pad via apertures 1622 and via capture pad openings 1626 .

FIG. 17 is a cross-sectional view of fan out build up substrate stackable package 1300 of FIG. 16 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 16 and 17 together, a circuit pattern 1728 is formed within circuit pattern artifact 1620 . In one embodiment, circuit pattern 1728 , sometimes called a first metal layer, is formed by plating an electrically conductive material such as copper within circuit pattern artifact 1620 . Circuit pattern 1728 is similar or identical to circuit pattern 528 of FIG. 5 except that circuit pattern 1728 is formed within dielectric film 1302 and package body 214 whereas circuit pattern 528 of FIG. 5 is formed in first buildup dielectric layer 316 .

In one embodiment, circuit pattern 1728 includes one or more metal layers. For example, initially a solder wettable layer such as nickel and/or gold is plated in circuit pattern artifact 1620 to partially fill circuit pattern artifact 1620 . Circuit pattern artifact 1620 is then completely filled with a second metal such as copper. In this manner, the exposed surfaces of via capture pads of circuit pattern 1728 are solder wettable as discussed in greater detail below.

Circuit pattern 1728 includes electrically conductive bond pad vias 1730 formed in bond pad via apertures 1622 and electrically connected to bond pads 110 . Bond pad vias 1730 are formed within dielectric film 1302 .

Circuit pattern 1728 further includes electrically conductive traces 1732 formed within trace channels 1624 and electrically conductive via capture pads 1734 formed within via capture pad openings 1626 . Traces 1732 are formed within both dielectric film 1302 and package body 214 . Via capture pads 1734 are formed within package body 214 .

Although circuit pattern 1728 is set forth as containing particular features, e.g., bond pad vias 1730 , traces 1732 , and via capture pads 1734 , in light of this disclosure, those of skill in the art will understand that a circuit pattern can be formed with other and/or different features depending on the particular signal routing desired. Further, instead of being embedded inside of dielectric film 1302 and package body 214 , in another embodiment, traces 1732 are formed on lower surfaces 1302 L, 214 L of dielectric film 1302 and package body 214 , respectively.

After formation of circuit pattern 1728 , an upper, e.g., first, surface 636 U of a buildup dielectric layer 636 is applied to lower surfaces 214 L, 1302 L of package body 214 and dielectric film 1302 , respectively, and to circuit pattern 1728 .

A circuit pattern artifact 638 is formed in a lower, e.g., second, surface 636 L of buildup dielectric layer 636 . Circuit pattern artifact 638 is formed using laser ablation, selective etching, or other technique.

Buildup dielectric layer 636 and circuit pattern artifact 638 of FIG. 17 are similar or identical to second buildup dielectric layer 636 and circuit pattern artifact 638 as described above in reference to FIG. 6 . However, in accordance with this embodiment, buildup dielectric layer 636 is applied directly to lower surfaces 214 L, 1302 L of package body 214 and dielectric film 1302 , respectively, and to circuit pattern 1728 thus avoiding application of first buildup dielectric layer 316 as also illustrated in FIG. 6 .

Circuit pattern artifact 638 is a positive image of the circuit pattern to be formed in buildup dielectric layer 636 . Circuit pattern artifact 638 includes blind via apertures 640 extending entirely through buildup dielectric layer 636 and exposing circuit pattern 1728 . Circuit pattern artifact 638 further includes trace channels 642 and land openings 644 .

Fan out build up substrate stackable package 1300 of FIG. 17 is further processed as set forth above in reference to the embodiment of FIGS. 7 , 8 , 9 , 10 , 11 , 12 and so these fabrication operations are not repeated. A notable exception is that via capture pad apertures 858 of FIG. 8 extend to and expose via capture pads 1734 of circuit pattern 1728 of FIG. 17 instead of via capture pads 534 of FIG. 8 .

FIG. 18 is a cross-sectional view of a fan out build up substrate stackable package 1800 during fabrication in accordance with yet another embodiment. Referring now to FIG. 18 , in accordance with this embodiment, via capture pads 1802 are formed on an upper, e.g., first, surface 1804 U of a carrier 1804 .

In one embodiment, carrier 1804 is an electrically conductive material such as copper. Via capture pads 1802 are plated on carrier 1804 using carrier 1804 as a plating electrode.

In one embodiment, via capture pads 1802 include an etch stop layer 1808 and a solder wettable layer 1810 . Carrier 1804 , e.g., copper, is selectively etchable compared to etch stop layer 1808 , e.g., nickel. Solder wettable layer 1810 , e.g., gold, is wettable by solder. Optionally, solder 1812 , sometimes called a Solder On Pad (SOP), is applied to via capture pads 1802 . Application of solder 1812 is optional, and in one embodiment, solder 1812 is not applied.

Further, active surface 106 of electronic component 102 is mounted to upper surface 1804 U of carrier 1804 by an adhesive 1806 , e.g., a die attach material. In one embodiment, adhesive 1806 is a strong adhesive thus avoiding undesirable movement of electronic component 102 on carrier 1804 during molding.

FIG. 19 is a cross-sectional view of fan out build up substrate stackable package 1800 of FIG. 18 at a later stage during fabrication in accordance with one embodiment. Referring now to FIG. 19 , electronic component 102 , via capture pads 1802 , and solder 1812 are encapsulated in a dielectric package body 214 .

Illustratively, electronic component 102 , via capture pads 1802 , solder 1812 and carrier 1804 are placed into a mold and mold compound is injected into the mold and around electronic component 102 , via capture pads 1802 , and solder 1812 to form package body 214 .

Package body 214 includes a lower, e.g., first, surface 214 L attached to upper surface 1804 U of carrier 1804 and an upper, e.g., second, surface 214 U. Package body 214 completely encloses electronic component 102 including inactive surface 108 and sides 112 and the exposed portion of upper surface 1804 U of carrier 1804 . Further, package body 214 completely encloses via capture pads 1802 and solder 1812 .

Package body 214 is thicker having a thickness T1 greater than a thickness T2 of electronic component 102 including adhesive 1806 . The thickness of adhesive 1806 is generally negligible so electronic component 102 shall be referred to as having thickness T2. More particularly, upper surface 214 U is above and spaced apart from inactive surface 108 .

FIG. 20 is a cross-sectional view of fan out build up substrate stackable package 1800 of FIG. 19 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 19 and 20 together, package body 214 is ground down from upper surface 214 U to expose inactive surface 108 of electronic component 102 . In one embodiment, inactive surface 108 is also ground down thus thinning both package body 214 and electronic component 102 .

Accordingly, after grinding, package body 214 and electronic component 102 have an equal thickness T3 less than thicknesses T1, T2 prior to grinding. Thinning package body 214 and electronic component 102 minimizes the overall thickness of fan out build up substrate stackable package 1800 . Grinding of package body 214 and electronic component 102 is optional, and in one embodiment, is not performed.

FIG. 21 is a cross-sectional view of fan out build up substrate stackable package 1800 of FIG. 20 at a later stage during fabrication in accordance with one embodiment. Referring now to FIG. 21 , optionally, a backside warpage control layer 318 is applied to upper surface 214 U of package body 214 . In the case where inactive surface 108 of electronic component 102 is exposed, backside warpage control layer 318 is also applied to inactive surface 108 .

As a further option, backside warpage control layer 318 is applied to a carrier 2114 , e.g., stainless steel. Carrier 2114 adds rigidity and support to fan out build up substrate stackable package 1800 during fabrication as set forth below. Application of backside warpage control layer 318 and/or carrier 2114 is optional, and in one embodiment, only backside warpage control layer 318 is applied. In another embodiment, neither backside warpage control layer 318 nor carrier 2114 are applied.

FIG. 22 is a cross-sectional view of fan out build up substrate stackable package 1800 of FIG. 21 at a later stage during fabrication in accordance with one embodiment. Referring now to FIG. 22 , carrier 1804 is removed. In one embodiment, carrier 1804 is copper and is removed by etching. Recall that etch stop layer 1808 is selectively etchable compared to carrier 1804 and thus provides an etch stop. In one embodiment, backside warpage control layer 318 and adhesive 1806 protect electronic component 102 during the etching process. In another embodiment, carrier 1804 is stainless steel and is removed by peeling.

FIG. 23 is a cross-sectional view of fan out build up substrate stackable package 1800 of FIG. 22 at a later stage during fabrication in accordance with one embodiment. Referring now to FIG. 23 , a first buildup dielectric layer 316 is applied to lower surface 214 L of package body 214 , via capture pads 1802 , and adhesive 1806 . A circuit pattern artifact 420 is formed in first buildup dielectric layer 316 . Circuit pattern artifact 420 is formed using laser ablation, selective etching, or other technique.

Circuit pattern artifact 420 is a positive image of the circuit pattern to be formed in first buildup dielectric layer 316 . Circuit pattern artifact 420 includes bond pad via apertures 422 extending entirely through first buildup dielectric layer 316 , adhesive 1806 and exposing bond pads 110 . Circuit pattern artifact 420 further includes trace channels 424 and capture pad via apertures 2316 . In accordance with this embodiment, capture pad via apertures 2316 are openings extending through first buildup dielectric layer 316 and exposing via capture pads 1802 .

A circuit pattern 528 is formed within circuit pattern artifact 420 . In one embodiment, circuit pattern 528 is formed by plating an electrically conductive material such as copper within circuit pattern artifact 420 .

Circuit pattern 528 includes electrically conductive bond pad vias 530 formed in bond pad via apertures 422 and electrically connected to bond pads 110 . Circuit pattern 528 further includes electrically conductive traces 532 formed within trace channels 424 and electrically conductive capture pad vias 2318 formed within capture pad via apertures 2316 . Capture pad vias 2318 extend through first buildup dielectric layer 316 and are electrically connected to via capture pads 1802 .

Although circuit pattern 528 is set forth as containing particular features, e.g., bond pad vias 530 , traces 532 , and capture pad vias 2318 , in light of this disclosure, those of skill in the art will understand that a circuit pattern can be formed with other and/or different features depending on the particular signal routing desired.

Further, a second buildup dielectric layer 636 is applied to first buildup dielectric layer 316 and to circuit pattern 528 .

A circuit pattern artifact 638 is formed in second buildup dielectric layer 636 . Circuit pattern artifact 638 is formed using laser ablation, selective etching, or other technique.

Circuit pattern artifact 638 is a positive image of the circuit pattern to be formed in second buildup dielectric layer 636 . Circuit pattern artifact 638 includes blind via apertures 640 extending entirely through second buildup dielectric layer 636 and exposing circuit pattern 528 . Circuit pattern artifact 638 further includes trace channels 642 and land openings 644 .

A circuit pattern 746 is formed within circuit pattern artifact 638 . In one embodiment, circuit pattern 746 is formed by plating an electrically conductive material such as copper within circuit pattern artifact 638 . In another embodiment, circuit pattern 746 includes one or more metal layers.

Circuit pattern 746 includes electrically conductive circuit pattern vias 748 formed in blind via apertures 640 and electrically connected to circuit pattern 528 . Circuit pattern 746 further includes electrically conductive traces 750 formed in trace channels 642 and electrically conductive lands 752 formed in land openings 644 . Although circuit pattern 746 is set forth as containing particular features, e.g., circuit pattern vias 748 , traces 750 , and lands 752 , in light of this disclosure, those of skill in the art will understand that a circuit pattern can be formed with other and/or different features depending on the particular signal routing desired.

A dielectric solder mask 854 is applied to second buildup dielectric layer 636 and patterned to expose lands 752 of circuit pattern 746 .

Interconnection balls 856 , e.g., solder, are formed on lands 752 . Interconnection balls 856 are distributed in a ball grid array (BGA) in one embodiment. The formation of interconnection balls 856 is optional, and in one embodiment, interconnection balls 856 are not formed.

FIG. 24 is a cross-sectional view of fan out build up substrate stackable package 1800 of FIG. 23 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 23 and 24 , carrier 2114 ( FIG. 23 ) is peeled away leaving backside warpage control layer 318 exposed as illustrated in FIG. 24 .

Referring now to FIG. 24 , via capture pad apertures 2420 are formed, e.g., using laser ablation, through package body 214 and backside warpage control layer 318 if backside warpage control layer 318 is formed. Via capture pad apertures 2420 expose via capture pads 1802 or solder 1812 if solder 1812 is formed. Generally, via capture pad apertures 2420 are aligned with respective via capture pads 1802 .

FIG. 25 is a cross-sectional view of a fan out build up substrate stackable package 2500 in accordance with another embodiment. Fan out build up substrate stackable package 2500 of FIG. 25 is similar to fan out build up substrate stackable package 1800 of FIG. 18 and only the significant differences are discussed below. Referring now to FIG. 25 , in accordance with this embodiment, electrically conductive through vias 2502 are formed through electronic component 102 .

More particularly, through vias 2502 extend between active surface 106 and inactive surface 108 . The ends of through vias 2502 at active surface 106 define active surface through via terminals 2504 . Further, the ends of through vias 2502 at inactive surface 108 define inactive surface through via terminals 2506 . Active surface through via terminals 2504 are electrically connected to inactive surface through via terminals 2506 by through vias 2502 .

A stacked flip chip electronic component 2508 , e.g., an active components such as an integrated circuit die, a passive component, and/or electronic component package, is mounted to electronic component 102 .

More particularly, stacked flip chip electronic component 2508 includes an active surface 2510 having bond pads 2512 thereon. Stacked flip chip electronic component 2508 further includes an inactive surface 2514 and sides 2516 extending between active surface 2510 and inactive surface 2514 .

Bond pads 2512 are physically and electrically mounted to inactive surface through via terminals 2506 by flip chip bumps 2518 , e.g., solder. Optionally, an underfill 2520 is applied between active surface 2510 of stacked flip chip electronic component 2508 and inactive surface 108 of electronic component 102 and around flip chip bumps 2518 .

Fan out build up substrate stackable package 2500 of FIG. 25 is further process as set forth above in reference to the embodiment of FIGS. 19 , 20 , 21 , 22 , 23 , 24 and so these fabrication operations are not repeated.

Notable exceptions are that both stacked flip chip electronic component 2508 and electronic component 102 are encapsulated within package body 214 . In contrast, recall that in FIG. 19 , only electronic component 102 is encapsulated within package body 214 .

Further, package body 214 is not ground down or, if ground down, is ground down to expose inactive surface 2514 of stacked flip chip electronic component 2508 . In contrast, recall that in FIG. 20 , package body 214 is ground down to expose inactive surface 108 of electronic component 102 .

Further, bond pad vias 530 of circuit pattern 528 extend entirely through first buildup dielectric layer 316 , adhesive 1806 and are electrically connected to both bond pads 110 and active surface through via terminals 2504 . In contrast, recall that in FIG. 23 , bond pad vias 530 are electrically connected to only bond pads 110 .

FIG. 26 is a cross-sectional view of a fan out build up substrate stackable package 2600 in accordance with one embodiment. Fan out build up substrate stackable package 2600 of FIG. 26 is similar to fan out build up substrate stackable package 1800 of FIG. 18 and only the significant differences are discussed below.

Referring now to FIG. 26 , in accordance with this embodiment, a stacked wirebond electronic component 2602 , e.g., an active components such as integrated circuit die, a passive component, and/or electronic component package, is mounted to electronic component 102 .

More particularly, stacked wirebond electronic component 2602 includes an active surface 2604 having bond pads 2606 thereon. Stacked wirebond electronic component 2602 further includes an inactive surface 2608 and sides 2610 extending between active surface 2604 and inactive surface 2608 .

Inactive surface 2608 of stacked wirebond electronic component 2602 is mounted to inactive surface 108 of electronic component 102 with an adhesive 2612 . Bond pads 2606 of stacked wirebond electronic component 2602 are electrically connected to via capture pads 1802 with bond wires 2614 . In one embodiment, the via capture pads 1802 electrically connected to bond wires 2614 are formed without solder 1812 as illustrated in FIG. 26 .

Fan out build up substrate stackable package 2600 of FIG. 26 is further process as set forth above in reference to the embodiment of FIGS. 19 , 20 , 21 , 22 , 23 , 24 and so these fabrication operations are not repeated.

Notable exceptions are that both stacked wirebond electronic component 2602 , electronic component 102 , and bond wires 2614 are encapsulated within package body 214 . In contrast, recall that in FIG. 19 , only electronic component 102 is encapsulated within package body 214 .

Further, package body 214 is not ground down or, if ground down, is only ground down such that a sufficient amount of package body 214 remains to enclose bond wires 2614 . In contrast, recall that in FIG. 20 , package body 214 is ground down to expose inactive surface 108 of electronic component 102 .

Although formation of individual packages is described above, in other embodiments, a plurality of packages are formed simultaneously in an array using the methods as described above. The array is singulated to singulate the individual packages from one another.

The drawings and the forgoing description gave examples of the present invention. The scope of the present invention, however, is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of the invention is at least as broad as given by the following claims.