Method of producing capacitor structure in a semiconductor device

This application is a divisional application (and claims the benefit of priority under 35 USC 120) of U.S. application Ser. No. 11/474,246, filed Jun. 23, 2006, now U.S. Pat. No. 7,578,858, which is a divisional application of (and claims the benefit of priority under 35 USC 120) of U.S. application Ser. No. 11/179,133, filed Jul. 11, 2005, now U.S. Pat. No. 7,116,544, which is a continuation application (and claims the benefit of priority under 35 USC 120) of U.S. application Ser. No. 10/870,579, filed Jun. 16, 2004, now U.S. Pat. No. 6,980,414. The disclosure of the prior applications is considered part of (and is incorporated by reference in) the disclosure of this application. This application is related to commonly owned, copending U.S. application Ser. No. 10/601,286, filed Jun. 20, 2003, which is a continuation of U.S. application Ser. No. 09/765,200, filed Jan. 18, 2001, now U.S. Pat. No. 6,625,006, the entire contents of which are incorporated by reference herein.

The present application is also related to commonly owned, copending U.S. application Ser. No. 10/372,617, filed on Feb. 21, 2003 (which is a divisional of the '006 patent), the entire contents of which are incorporated by reference herein.

The following disclosure relates to semiconductor devices.

In integrated circuit design there are many applications that include high performance, on-chip capacitors. These applications include, for example, voltage control oscillators, phase-lock loops, operational amplifiers, and switching capacitors. On-chip capacitors can be used, e.g., to isolate digital and analog integrated circuits from noise created within an integrated circuit system or to store charge within an integrated circuit system.

Conventional on-chip capacitors can be configured as Metal-Oxide-Metal capacitors (MOMs). Referring to FIG. 1 , the construction of a conventional MOM capacitor 100 is illustrated. MOM capacitor 100 includes two nodes 102 and 104 that are formed on conductor layers 106 and 108 , respectively. A substrate 110 forms a base for MOM capacitor 100 . Conductor layers 106 and 108 are separated by a dielectric 112 (e.g., silicon dioxide). Substrate 110 and conductor layer 108 can also be separated by a dielectric (not shown). In addition to a device (parallel plate) capacitance (Cpp) that is formed between nodes 102 and 104 , an undesirable parasitic capacitance (Cs) may also be formed between substrate 110 and node 104 in a conventional MOM structure.

In general, in one aspect, this specification describes a capacitor structure. The capacitor structure includes a substrate, a first group of conducting strips, a second group of conducting strips, a third group of conducting strips, and a fourth group of conducting strips.

The first group of conducting strips are arranged substantially parallel to each other within a first layer disposed on the substrate. The first group of conducting strips are also connected to a first node and are in electrical communication with each other. The second group of conducting strips are arranged substantially parallel to each other and alternate with the first group of conducting strips within the first layer. The second group of conducting strips are connected to a second node and are in electrical communication with each other. The third group of conducting strips are arranged substantially parallel to each other within a second layer that at least partially overlies the first layer. The third group of conducting strips are in electrical communication with each other and with the first group of conducting strips. The third group of conducting strips are further substantially perpendicular to the first group of conducting strips and the second group of conducting strips. The fourth group of conducting strips are arranged substantially parallel to each other and alternate with the third group of conducting strips within the second layer. The fourth group of conducting strips are in electrical communication with each other and with the second group of conducting strips. The fourth group of conducting strips are further substantially perpendicular to the first group of conducting strips and the second group of conducting strips.

Particular implementations can include one or more of the following. The capacitor structure can further include a dielectric interposed between the first and second layers. The dielectric can be a layer of silicon dioxide. The capacitor structure can further include a guardband spaced from the first and second nodes. The guardband can be comprised of a conductive material—e.g., aluminum, polysilicon, or copper. The guardband can be spaced approximately a predetermined distance (dg) from the first and second nodes, in which adjacent conducting strips of the first and second layers are spaced apart approximately a predetermined distance (dh), and the distance (dg) is selected to be substantially twice the distance (dh). The guardband can be located on a single layer or distributed over multiple layers. The guardband can encircle the first and second layers of conducting strips. At least one of the first, second, third and fourth groups of conducting strips can be connected by a corresponding base strip. The first group of conducting strips can be connected to the third group of conducting strips by vertical vias. The second group of conducting strips can be connected to the fourth group of conducting strips by vertical vias. The second layer can substantially overlie the first layer.

In general, in another aspect, this specification describes a capacitor structure that includes a substrate, a first group of conducting strips, a second group of conducting strips, a third group of conducting strips, a fourth group of conducting strips, a first set of vertical vias, a second set of vertical vias, a third set of vertical vias, and a fourth set of vertical vias.

The first group of conducting strips are arranged substantially parallel to each other within a first layer disposed on the substrate. The first group of conducting strips are connected to a first node and are connected to a first base strip. The second group of conducting strips are arranged substantially parallel to each other and alternate with the first group of conducting strips within the first layer. The second group of conducting strips are connected to a second node and are connected to a second base strip. The third group of conducting strips are arranged substantially parallel to each other within a second layer that at least partially overlies the first layer. The third group of conducting strips are connected to the first node and are connected to a third base strip. The third group of conducting strips are substantially parallel to and substantially overlie the first group of conducting strips. The fourth group of conducting strips are arranged substantially parallel to each other and alternate with the third group of conducting strips within the second layer. The fourth group of conducting strips are connected to the second node and are connected to a fourth base strip. The fourth group of conducting strips are also substantially parallel to and substantially overlie the second group of conducting strips. The first set of vertical vias interconnect the first group of conducting strips to the third group of conducting strips. The second set of vertical vias interconnect the second group of conducting strips to the fourth group of conducting strips. The third set of vertical vias interconnect the first base strip to the third base strip. The fourth set of vertical vias interconnect the second base strip to the fourth base strip.

Particular implementations can include one or more of the following. The third set and fourth set of vertical vias can be each placed at locations along a respective base strip substantially adjacent to vertical vias of an opposite node that are located on one or more of the first, second, third or fourth groups of conducting strips.

Implementations can include one or more of the following advantages. On-chip capacitance structures are provided that are highly immune to noise fluctuations that may be present on a substrate. In addition, the on-chip capacitance structures provide a high capacitance-per-volume. In one implementation, vertical vias are used within a base strip to form base strip via capacitances that further increase the overall capacitance-per-volume of the capacitance structure. On-chip capacitance structures are provided that also have an efficient use of space.

The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims.

FIG. 1 illustrates a conventional on-chip capacitor structure.

FIG. 2 is a perspective view of an on-chip capacitor structure.

FIG. 3 is a side view of the A-A cross-section of the on-chip capacitor structure in FIG. 2 , showing associated capacitances.

FIG. 4 is a top view of the on-chip capacitor structure of FIG. 2 .

FIG. 5 is a side view of the on-chip capacitor structure of FIG. 2 , including guard bands.

FIG. 6 is a top view of an on-chip capacitor structure.

FIG. 7A is a side view of an on-chip capacitor structure, including vertical vias.

FIG. 7B is a perspective view of the on-chip capacitor structure of FIG. 7A .

FIG. 7C is a top view of the on-chip capacitor structure of FIG. 7A .

FIG. 8 is a side view of the on-chip capacitor structure of FIG. 7A , including guardbands.

FIG. 9 is a perspective view of a split-capacitor configuration.

FIG. 10 is a top view of another on-chip capacitor structure.

Like reference symbols in the various drawings indicate like elements.

FIG. 2 illustrates one implementation of an on-chip capacitor 200 . On-chip capacitor 200 includes two layers 201 , 203 of conducting strips formed upon a substrate 202 . Substrate 202 can be a p-type substrate or an n-type substrate. A first layer 201 is formed by two sets of conducting strips 204 A and 204 B. Conducting strips 204 A and 204 B are arranged alternately and substantially in parallel to each other (i.e., a conducting strip 204 A is next to a conducting strip 204 B, which, in turn, is located next to a second conducting strip 204 A, and so on). A second layer 203 is formed by two sets of conducting strips 206 A and 206 B. Second layer 203 can be separated from first layer 201 by an insulating layer (not shown). The insulating layer can be a silicon dioxide layer. Second layer 203 at least partially overlies first layer 201 —e.g., at least one conducting strip of the second layer overlies at least a portion of a conducting strip in the first layer. Conducting strips 206 A and 206 B are also arranged alternately and substantially in parallel to each other. In one implementation, conducting strips 206 A and 206 B overlie and are substantially perpendicular to conducting strips 204 A and 204 B.

Conducting strips 204 A of first layer 201 and conducting strips 206 A of second layer 203 are connected to form a first common node. In one implementation, conducting strips 204 A and conducting strips 206 A are connected by vertical vias. Likewise, conducting strips 204 B of first layer 201 and conducting strips 206 B of second layer 203 are connected to form a second common node. The first common node and the second common node form opposing nodes of on-chip capacitor 200 . Each conducting strip 204 A connected to the first common node has one or more overlying conducting strips 206 B and one or more overlying conducting strips 206 A. Likewise, each conducting strip 204 B connected to the second common node has one or more overlying conducting strips 206 A and one or more overlying conducting strips 206 A. In one implementation, the number of “A” and “B” conducting strips are equal within each layer.

FIG. 3 . shows a cross-section of on-chip capacitor 200 ( FIG. 2 ). A parallel plate capacitance (Cpp) is present between each conducting strip 204 B and conducting strip 206 A. Furthermore, a sidewall capacitance (Csw) is present between each adjacent pair of conducting strips (e.g., conducting strips 204 A and 204 B) within each layer. In addition, a substrate capacitance (Cb) is formed between conducting strips in first layer 201 (e.g., conducting strips 204 A and 204 B) and substrate 202 . As shown in FIG. 3 , substrate 202 can be at ground (or a low voltage potential).

FIG. 4 illustrates a top view of how conducting strips 204 A and 204 B of first (lower) layer 201 and conducting strips 206 A and 206 B of second (upper) layer 203 are laid out in one implementation. Conducting strips 204 A and 204 B of the lower layer are shown in solid lines. In one implementation, conducting strips 204 A are connected by a base strip 208 A and conducting strips 204 B are connected by a base strip 208 B. Alternatively, each of conducting strips 204 A and conducting strips 204 B can be respectively connected by vertical vias (not shown). Base strips 208 A and 208 B are located at opposing ends of conducting strips 204 A and 204 B so that conducting strips 204 A and 204 B are interdigitated. In one implementation, base strips 208 A and 208 B are sized to be narrow—e.g., as wide as conducting strips 204 A and 204 B—to minimize space occupied by on-chip capacitor 200 .

Conducting strips 206 A and 206 B of the upper layer are shown by dotted lines and are displaced to distinguish the upper layer conducting strips 206 A and 206 B from the lower layer conducting strips 204 A and 204 B. In general, conducting strips 206 A and 206 B substantially lie perpendicularly directly over conducting strips 204 A and 2043 . In one implementation, conducting strips 206 A are connected by a base strip 210 A and conducting strips 206 B are connected by a base strip 210 B. Alternatively, each of conducting strips 206 A and conducting strips 2063 can be respectively connected by vertical vias (not shown). As shown in FIG. 4 , base strips 210 A and 210 B are at opposing ends of conducting strips 206 A and 206 B. In one implementation, the second layer pattern of interdigitated conducting strips 206 A and 206 B is substantially perpendicular to the first layer pattern.

The interconnections between the “A” conducting strips—i.e., conducting strips 204 A and 206 A, and the “B” conducting strips—i.e., conducting strips 204 B and 206 B, are not shown. In one implementation, the interconnections are made by vertical vias (not shown) through the insulating layer between first layer 201 and second layer 203 of on-chip capacitor 200 .

FIG. 5 . shows a cross-section of one implementation of on-chip capacitor 200 ( FIG. 2 ). As shown in FIG. 5 , on-chip capacitor 200 includes a guardband 500 for attenuating coupling between on-chip capacitor 200 and external electromagnetic fields. Guardband 500 can be formed from a conductive material, for example, polysilicon, aluminum, and copper. In one implementation, guardband 500 is provided on each of first layer 201 and second layer 203 and substantially encircles the first and second common nodes of on-chip capacitor 200 . Guardband 500 can encircle less than all of first layer 201 and second layer 203 . Guardband 500 can only run along one side of on-chip capacitor 200 . In addition, guardband 500 can be included on other layers either above or below first layer 201 and second layer 203 of on-chip capacitor 200 . In one implementation, guardband 500 is spaced from the conducting strips a distance (dg) that is approximately twice the distance (dh) between adjacent conducting strips. Distance (dg) can be selected to minimize the parasitic fringing capacitance that is formed between guardband 500 and an adjacent conducting strip or base strip, while at the same time maintaining a volumetrically efficient on-chip capacitor 200 .

In one implementation, to maintain a predetermined ratio between the capacitance of on-chip capacitor 200 and the parasitic capacitance formed from guardband 500 , distance (dg) is increased when there are fewer conducting layers or conducting strips, and distance (dg) is decreased when there are more conducting layers or conducting strips. In one implementation, a line width of guardband 500 is selected to be the same as a line width of a conducting strip—e.g., conducting strip 206 A or 206 B. However, other line widths can be selected. In one implementation, guardband 500 is coupled through a low impedance (not shown) to a voltage potential such as ground. In one implementation, guardband 500 floats with respect to system voltage potentials.

FIG. 6 illustrates a top view of one implementation of a path configuration for an on-chip capacitor 600 . On-chip capacitor 600 contains conducting strips that are laid out a path configuration that is substantially spiral. In particular, on-chip capacitor 600 includes lower layer conducting strips 602 A and 602 B and upper layer conducting strips 604 A and 604 B. Conducting strips 602 A and 602 B of the lower layer are shown in solid lines and conducting strips 604 A and 604 B of the upper layer are shown in dotted lines. Conducting strips 604 A and 604 B of the upper layer are displaced to distinguish the upper layer conducting strips 604 A and 604 B from the lower layer conducting strips 602 A and 602 B. In one implementation, conducting strips 604 A and 604 B respectively lie substantially directly over conducting strips 602 B and 602 A. Other path configurations can be implemented, e.g., L-shaped paths and S-shaped paths. For example, FIG. 10 illustrates a top view of one implementation of an S shaped path configuration for an on-chip capacitor 1000 .

FIG. 7A . shows a cross-section B-B ( FIG. 7B ) of an on-chip capacitor 700 . On-chip capacitor 700 includes two layers 701 , 703 of conducting strips formed upon a substrate 702 . A first layer 701 is formed by two sets of conducting strips 704 A and 704 B. Conducting strips 704 A and 704 B are arranged alternately and substantially in parallel to each other so that a conducting strip 704 A is located next to a conducting strip 704 B, as shown in FIG. 7B .

Referring to FIGS. 7A and 7B , a second layer 703 is formed by two sets of conducting strips 706 A and 706 B. Conducting strips 706 A and 706 B are also arranged alternately and substantially in parallel to each other so that a conducting strip 706 A is located next to a conducting strip 706 B. Conducting strips 706 A and 706 B respectively overlie and are substantially parallel to conducting strips 704 A and 704 B, such that conducting strips of a same polarity overlie one another. For example, conducting strip 706 A—shown as having a “+” polarity—substantially overlies conducting strip 704 A—also shown as having a “+” polarity. On-chip capacitor 700 further includes vertical vias 708 A that interconnect conducting strips 706 A and 704 A, and vertical vias 708 B that interconnect conducting strips 706 B and 704 B.

A parallel plate capacitance (Cpp) is present between each adjacent pair of conducting strips (e.g., conducting strips 706 A and 706 B) within each layer. Furthermore, a via capacitance (Cv) is present between each adjacent pair of vertical vias (e.g., vertical vias 708 A and 7083 ).

FIG. 7C shows a top view of on-chip capacitor 700 . In one implementation, conducting strips 706 A are connected by a base strip 710 A and conducting strips 706 B are connected by a base strip 710 B. Base strips 710 A and 710 B are located at opposing ends of conducting strips 706 A and 706 B so that conducting strips 706 A and 7063 are interdigitated. In one implementation, base strips 710 A and 710 B are sized as wide as conducting strips 706 A and 706 B.

In one implementation, base strips 710 A and 710 B include vertical vias 712 A and 712 B, respectively. Vertical vias 712 A and 712 B interconnect with corresponding base strips (not shown) underlying base strips 710 A and 710 B. Vertical vias 712 A can be placed along base strip 710 A at locations substantially adjacent to one or more vertical vias 708 B that are located on conducting strips 706 B. Likewise, vertical vias 712 B can be placed along base strip 710 B at locations substantially adjacent to one or more vertical vias 708 A that are located on conducting strips 706 A.

In addition to the parallel plate capacitance (Cpp) ( FIG. 7A ), and the via capacitance (Cv) ( FIG. 7A ), a base strip via capacitance (Cvb) is present between each adjacent pair of base strip vertical via and conducting strip vertical via (e.g., vertical vias 712 A and 708 B).

FIG. 8 . shows a cross-section of one implementation of on-chip capacitor 700 ( FIG. 7A ). As shown in FIG. 8 , on-chip capacitor 700 includes a guardband 800 for attenuating coupling between on-chip capacitor 700 and external electromagnetic fields. In one implementation, guardband 800 is provided on each of first layer 701 and second layer 703 and substantially encircles the first and second common nodes of on-chip capacitor 700 . Guardband 700 can encircle less than all of first layer 701 and second layer 703 . Guardband 800 can only run along one side of on-chip capacitor 700 . In addition, guardband 800 can be included on other layers either above or below first layer 701 and second layer 703 of on-chip capacitor 700 .

A number of implementations have been described. Nevertheless, various modifications to the implementations may be made. For example, an on-chip capacitor can be formed in a split-capacitor configuration 900 as shown in FIG. 9 . Split-capacitor configuration 900 includes a first on-chip capacitor 902 and a second on-chip capacitor 904 formed upon a substrate 906 . Each of first on-chip capacitor 902 and second on-chip capacitor 904 can have any one of the capacitor structures described in the implementations above. In addition, each of the capacitor structures described above can have any number of conducting layers, e.g. more than two layers. Accordingly, other implementations are within the scope of the following claims.