Inventor
Pantas Sutardja
Inventor
Los Gatos, CA, US
Overview
Patents· 364 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Bprimary
G11BInformation storage based on relative movement between record carrier and transducer26%
G11CStatic stores15%
G06FElectric digital data processing13%
H04LTransmission of digital information, e.g. telegraphic communication6%
H03MCoding5%
H03KPulse technique3%
H10BElectronic memory devices3%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%
H10NElectric solid-state devices not otherwise provided for2%
H05BElectric heating2%
PatentTitleYear
10,893,104Implementing a storage system using a personal user device and a data distribution device202110,412,168Implementing a storage system using a personal user device and a data distribution device201910,198,310Providing error correcting code (ECC) capability for memory201910,067,866Method and apparatus for mapping logical addresses between memories of a solid-state disk based on write frequency rankings201810,027,515Apparatus and method for introducing gain and phase offset via a second filter due to constraint of coefficients of a first filter20189,887,543'Method and apparatus for wave detection'20189,804,736'Modifiable contextual help content provided in-line within an application'20179,727,455'Method and apparatus for mapping a logical address between memories of a storage drive based on write frequency rankings'20179,705,985'Systems and methods for cross protocol automatic sub-operation scheduling'20179,699,853'Method and apparatus for dimmable LED driver'20179,641,359'Apparatus and method for accounting for gain and phase error introduced by a first filter by adjusting coefficients of a second filter'20179,632,932'Backup-power-free cache memory system'20179,614,386'Method and apparatus for power switching'20179,594,630'System and method for writing pilot data interspersed with user data for estimating disturbance experienced by user data'20179,576,606'Long latency interface protocol'20179,521,715'Current shaping for dimmable LED'20169,490,427'Resistive random access memory cell structure'20169,485,816'Method and apparatus for dimmable LED driver'20169,480,112'Current shaping for dimmable LED'20169,445,475'Buck regulator for LED lighting color mixing and/or current compensation'20169,396,146'Timing-budget-based quality-of-service control for a system-on-chip'20169,319,024'Apparatus and method for accounting for gain and timing phase error, not accounted for by coefficients of a first filter, via coefficients of a second filter'20169,320,097'Multi-string dimmable LED driver'20169,275,731'Systems and methods for increasing the read sensitivity of a resistive random access memory (RRAM)'20169,245,632'Write pre-compensation for nonvolatile memory'20169,245,961'Reducing source contact to gate spacing to decrease transistor pitch'20169,224,419'Data detector for detecting data in presence of control signals'20159,220,136'Method and apparatus for controlling a lighting device'20159,214,230'Resistive random access memory cell structure with reduced programming voltage'20159,189,329'Generating error correcting code (ECC) data using an ECC corresponding to an identified ECC protection level'20159,185,755'Regulator for LED lighting color mixing'20159,165,599'Method for correcting DC characteristics in a magnetic recording system'20159,153,337'Fatigue management system and method for hybrid nonvolatile solid state memory system'20159,147,837'Resistive memory cell and method for forming a resistive memory cell'20159,144,137'Diode emulator circuit'20159,129,678'Method and apparatus for reforming a memory cell of a memory'20159,112,133'Resistive random access memory and method for controlling manufacturing of corresponding sub-resolution features of conductive and resistive elements'20159,101,018'Apparatuses for bleeding current from a transformer of a solid-state light emitting diode'20159,075,745'System and method for adding a drive to a storage system having multiple drives'20159,053,051'Multi-level memory controller with probability-distribution-based encoding'20159,047,945'Systems and methods for reading resistive random access memory (RRAM) cells'20159,042,159'Configuring resistive random access memory (RRAM) array for write operations'20159,017,427'Method of creating capacitor structure in a semiconductor device'20158,999,786'Reducing source contact to gate spacing to decrease transistor pitch'20158,993,398'Method for creating ultra-high-density holes and metallization'20158,994,407'Method and system for removing a pulse having a different pulse width relative to that of other pulses in a clock signal of an analog to digital converter'20158,959,417'Providing low-latency error correcting code capability for memory'20158,957,602'Correlated color temperature control methods and devices'20158,947,808'Preamp circuit including a loopback mode for data storage devices'20158,947,909'System and method for creating a bipolar resistive RAM (RRAM)'20158,937,457'Power management circuit of rechargeable battery stack'20158,937,511'Frequency scaling of variable speed systems for fast response and power reduction'20158,934,285'Method and apparatus for forming a contact in a cell of a resistive random access memory to reduce a voltage required to program the cell'20158,935,591'System and method to correct errors in data read from a source supplying streaming data'20158,891,330'Method and apparatus for simultaneously accessing a plurality of memory cells in a memory array to perform a read operation and/or a write operation'20148,885,388'Apparatus and method for reforming resistive memory cells'20148,887,005'Caching system with removable memory card'20148,873,309'Apparatus and method for repairing resistive memories and increasing overall read sensitivity of sense amplifiers'20148,874,874'Method and storage drive for writing portions of blocks of data in respective arrays of memory cells of corresponding integrated circuits'20148,868,804'Unified I/O adapter'20148,862,931'Apparatus and method for storing and assigning error checking and correcting processing of data to storage arrays'20148,856,622'Apparatus and method for encoding data for storage in multi-level nonvolatile memory'20148,856,423'Dual-purpose nonvolatile memory for code and data storage'20148,847,517'TRIAC dimming systems for solid-state loads'20148,826,047'Self governing power management architecture that allows independent management of devices based on clock signals and a plurality of control signals written to control registers'20148,817,414'Data detector for detecting data in presence of control signals'20148,811,134'Circuits, architectures, apparatuses, systems, algorithms and methods and software for optimum power calibration for optical disc recording'20148,812,905'Self-repairable semiconductor and method thereof'20148,803,438'Method and apparatus for current control with LED driver'20148,799,568'Storage device cache'20148,799,724'Methods and systems for storing data in memory using zoning'20148,775,854'Clock turn-on strategy for power management'20148,773,786'System for correcting DC characteristics of a magnetic recording system'20148,760,791'Magnetic storage systems with transistors and limiting circuits for limiting voltages across terminals of read and write devices'20148,751,786'Method and integrated circuit for loading and executing firmware based on programing of one-time programmable memory'20148,745,453'Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions'20148,743,616'Write pre-compensation for nonvolatile memory'20148,736,231'Power management circuit for rechargeable battery stack'20148,732,432'Pilot placement for non-volatile memory'20148,717,824'Threshold voltage digitizer for array of programmable threshold transistors'20148,698,537'Method and apparatus for reducing jitter in a transmitter'20148,693,300'Write PLL for optical disc labeling applications'20148,681,553'System and method for memory array decoding'20148,677,215'Method and system for error correction in flash memory'20148,665,550'Method and system for reducing a disturbance associated with repeatable runout of a removable disc loaded into a storage system'20148,667,370'Systems and methods for arbitrating use of processor memory'20148,654,469'Preamp circuit including a loopback mode for data storage devices'20148,644,080'Incremental memory refresh'20148,638,619'High speed interface for multi-level memory'20148,618,764'Calibrating spindle motor controllers'20138,614,592'High data rate envelope detector for high speed optical storage application'20138,609,528'High-density patterning'20138,599,975'System and method for controlling gain and timing phase in a presence of a first least mean square filter using a second adaptive filter'20138,593,755'Flying height measurement'20138,583,991'High density multi-level memory'20138,576,678'System and method for tracking position of a laser beam on a storage device'20138,566,664'System and method for correcting errors in non-volatile memory using products codes'20138,566,499'Long latency interface protocol'20138,559,284'Circuits, architectures, apparatuses, systems, algorithms and methods and software for optimum power calibration for optical disc recording'20138,558,580'Data channel circuit with reference clock signal free of glitches'20138,539,216'System-on-a-chip (SoC) security using one-time programmable memories'20138,537,524'Capacitor structure in a semiconductor device'20138,539,195'Non-volatile memory device with non-evenly distributable data access'20138,525,478'Power management circuit of rechargeable battery stack'20138,514,510'Self-servo-write using ramp-tracks'20138,514,508'Preamp circuit including a loopback mode for data storage devices'20138,509,045'Flexible optical write strategy'20138,493,028'Power management circuit for rechargeable battery stack'20138,495,416'File server for redundant array of independent disks (RAID) system'20138,495,442'Circuits, architectures, apparatuses, systems, algorithms, software and firmware for using reserved cells to indicate defect positions'20138,488,398'Threshold voltage digitizer for array of programmable threshold transistors'20138,472,277'System and method for memory array decoding'20138,473,812'Method and system for error correction in flash memory'20138,462,457'Electrostatic discharge protection circuit for magneto-resistive read elements'20138,448,001'System having a first device and second device in which the main power management module is configured to selectively supply a power and clock signal to change the power state of each device independently of the other device'20138,432,753'High speed interface for multi-level memory'20138,424,190'Method of providing electrostatic discharge protection for a read element in a magnetic storage system'20138,407,559'Monitoring memory'20138,395,341'Repetitive error correction method for disk-drive spindle motor control systems'20138,392,799'Systems and methods for arbitrating use of processor memory'20138,386,889'Drive replacement techniques for RAID systems'20138,379,341'Preamp circuit including a loopback mode for data storage devices'20138,369,041'Method and apparatus for reducing repeatable runout in storage systems'20138,359,498'Encoding and decoding apparatus and method with hamming weight enhancement'20138,358,541'Write pre-compensation for nonvolatile memory'20138,358,479'Method and apparatus to limit DC-level in coded data'20138,345,522'Flexible optical write strategy'20138,341,503'Methods and systems for storing data in memory using zoning'20128,335,138'Track counting system and method for recordable optical media'20128,319,524'Deglitch circuit removing glitches from input clock signal'20128,320,860'Clean spot detection for FM transmission'20128,315,007'Flying height measurement'20128,315,106'Incremental memory refresh'20128,316,206'Pilot placement for non-volatile memory'20128,294,503'Method and apparatus for reducing jitter in a transmitter'20128,285,980'System-on-a-chip (SoC) security using one-time programmable memories'20128,279,984'System and method for controlling gain and timing phase in a presence of a first least mean square filter using a second adaptive filter'20128,266,484'Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions'20128,219,775'Nonvolatile memory system'20128,219,886'High density multi-level memory'20128,203,902'System and method for memory array decoding'20128,184,393'Self-servo-write using ramp-tracks'20128,180,946'Long latency interface protocol'20128,176,386'Systems and methods for processing streaming data'20128,169,735'Zone servo writing using self servo writing'20128,166,271'Memory controller for setting page length and memory cell density for semiconductor memory'20128,166,370'Efficient RAID ECC controller for RAID systems'20128,154,902'Bit line decoder architecture for NOR-type memory array'20128,149,531'Electrostatic discharge protection circuit for magneto-resistive read elements'20128,149,626'Threshold voltage digitizer for array of programmable threshold transistors'20128,125,870'Flexible optical write strategy'20128,120,871'Method and apparatus for reducing repeatable runout in storage systems'20128,117,510'Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions'20128,116,110'Array architecture including mirrored segments for nonvolatile memory device'20128,098,447'Method and apparatus to limit DC-level in coded data'20128,098,452'Flying height measurement'20128,094,404'Propagation self servo write system and method for storage devices employing sector-servo scheme'20128,094,405'Repetitive error correction method for disk-drive servo control systems'20128,081,720'System and method for controlling gain and timing phase in a presence of a first least mean square filter using a second adaptive filter'20118,077,415'Preamp circuit including a loopback mode for data storage devices'20118,074,151'Correcting errors in disk drive read back signals by iterating with the reed-solomon decoder'20118,054,715'Track counting system and method for recordable optical media'20118,055,979'Flash memory with coding and signal processing'20118,046,629'File server for redundant array of independent disks (RAID) system'20118,046,660'System and method for correcting errors in non-volatile memory using product codes'20118,046,571'System-on-a-chip (SoC) security using one-time programmable memories'20118,031,531'Incremental memory refresh'20118,030,215'Method for creating ultra-high-density holes and metallization'20118,031,526'Write pre-compensation for nonvolatile memory'20118,030,128'Method to form high density phase change memory (PCM) top contact every two bits'20118,031,424'Method and apparatus for testing electronics of a storage system'20118,027,117'Zone servo writing using self servo writing'20118,026,742'Phase detector'20118,022,646'Method and apparatus for spindle motor control'20118,019,959'Nonvolatile memory system'20118,014,206'Threshold voltage digitizer for array of programmable threshold transistors'20118,009,068'Filter driven DC-free code'20118,004,926'System and method for memory array decoding'20118,006,127'File server for redundant array of independent disks (RAID) system'20117,999,500'Calibrating spindle motor controllers'20117,994,052'High-density patterning'20117,990,089'Repetitive error correction method for disk-drive spindle motor control systems'20117,990,643'Read channel configuration based on polarity determined in accordance with multiple framings of signal samples'20117,988,744'Method of producing capacitor structure in a semiconductor device'20117,985,616'Methods to form wide heater trenches and to form memory cells to engage heaters'20117,982,998'Communications channel with programmable coupling'20117,978,575'Automatic write strategy calibration method for optical drive'20117,978,541'High speed interface for multi-level memory'20117,958,433'Methods and systems for storing data in memory using zoning'20117,958,301'Memory controller and method for memory pages with dynamically configurable bits per cell'20117,953,382'Clean spot detection for FM transmission'20117,944,313'Calibrating control loops'20117,945,728'Storage device cache'20117,939,414'Ion implantation and process sequence to form smaller base pick-up'20117,940,489'Method and apparatus for repeatable run-out compensation'20117,939,445'High density via and metal interconnect structures, and methods of forming the same'20117,937,526'Storage device cache with phase change memory'20117,936,581'Bit line decoder architecture for nor-type memory array'20117,903,521'Write splice for optical recording channels'20117,888,166'Method to form high efficiency GST cell using a double heater cut'20117,881,172'Flexible optical write strategy'20117,881,003'Write driver system for data storage systems'20117,881,126'Memory structure with word line buffers'20117,872,828'Flying height measurement'20117,869,246'Bit line decoder architecture for NOR-type memory array'20117,869,247'Bit line decoder architecture for NOR-type memory array'20117,869,248'Bit line decoder architecture for NOR-type memory array'20117,865,802'Data coding for enforcing constraints on ones and zeros in a communications channel'20117,863,709'Low base resistance bipolar junction transistor array'20117,864,895'Viterbi detection using a correlation metric'20117,855,909'Calibrating page borders in a phase-change memory'20107,852,598'Self-servo-write using sloped tracks written using a calibrated current profile'20107,852,585'Preamp circuit including a loopback mode for data storage devices'20107,852,591'Electrostatic discharge protection circuit for magneto-resistive read elements'20107,844,879'Method and system for error correction in flash memory'20107,839,906'Laser power control in an optical disc drive'20107,839,739'Circuits, architectures, apparatuses, systems, algorithms and methods and software for optimum power calibration for optical disc recording'20107,835,105'Propagation self servo write system and method for storage devices employing sector-servo scheme'20107,836,364'Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions'20107,835,425'Architectures, circuits, systems and methods for reducing latency in data communications'20107,827,474'Marking unreliable symbols in a hard disk drive read back signal'20107,821,731'Timing recovery for data storage channels with buffered sectors'20107,808,834'Incremental memory refresh'2010RE041792'Controllable integrator'20107,807,539'Ion implantation and process sequence to form smaller base pick-up'20107,800,951'Threshold voltage digitizer for array of programmable threshold transistors'20107,802,151'Encoding and decoding apparatus and method with hamming weight enhancement'20107,795,910'Field-programmable gate array using charge-based nonvolatile memory'20107,793,028'Long latency interface protocol'20107,791,832'Self-servo write stitching system'20107,791,378'Phase detector'20107,782,726'Write splice for optical recording channels'20107,783,937'Encoding and decoding apparatus and method with hamming weight enhancement'20107,773,479'Flexible optical write strategy'20107,773,328'Synchronous repeatable run out field detection with high efficiency field format'20107,773,329'Correcting errors in a disk drive read back signals by iterating with the Reed-Solomon decoder'20107,773,325'Timing recovery for data storage channels with buffered sectors'20107,764,458'Up-sampled filtering for servo demodulation'20107,760,459'Framing selection and waveform polarity determination for an encoded repeating pattern'20107,751,144'Self-servo-write using ramp-tracks'20107,751,138'Correcting errors in disk drive read back signals by iterating with the Reed-Solomon decoder'20107,745,809'Ultra high density phase change memory having improved emitter contacts, improved GST cell reliability and highly matched UHD GST cells using column mirco-trench strips'20107,737,731'High data rate envelope detector for high speed optical storage application'20107,737,793'Calibrating control loops'20107,730,349'Self-reparable semiconductor and method thereof'20107,724,596'Auto-zero current sensing amplifier'20107,715,134'Demodulation compensation for spiral servo tracks in hard disk drives'20107,715,135'Methods, circuits, apparatus, and systems for read channel synchronization and/or fly height measurement'20107,710,679'Communications channel with programmable coupling'20107,709,835'Method to form high efficiency GST cell using a double heater cut'20107,701,660'Shock cancellation system'20107,698,672'Methods of minimizing leakage current'20107,679,953'Calibration system for writing and reading multiple states into phase change memory'20107,675,826'Automatic write strategy calibration method for optical drive'20107,661,058'Efficient raid ECC controller for raid systems'20107,656,605'Method for repeatable run-out compensation'20107,657,784'Self-reparable semiconductor and method thereof'20107,657,823'Efficient RAID ECC controller for RAID systems'20107,646,555'Testing storage system electronics using loopback'20107,646,559'Self-servo write stitching system'20107,634,686'File server for redundant array of independent disks (RAID) system'20097,622,731'Cross-point memory array'20097,623,048'DC-free codes'20097,619,919'Multi-level memory'20097,583,469'Up-sampled filtering for servo demodulation'20097,583,456'Method and apparatus to limit DC-level in coded data'20097,580,216'Disk servo pattern writing'20097,578,858'Making capacitor structure in a semiconductor device'20097,573,214'Method and apparatus for spindle motor control'20097,568,144'Data coding for enforcing constraints on ones and zeros in a communications channel'20097,535,955'Methods, algorithms, software, architectures, systems and circuitry for adaptive filtering and/or minimizing a sequence detector error rate'20097,529,057'Servo loop employing correction vector from a secondary disturbance sensor to minimize correlation between servo loop error and disturbance sensor output'20097,522,370'Self-servo-write using ramp-tracks'20097,522,369'Circuits, architectures, apparatus, systems, and methods for maintaining constant spacing in a read/write apparatus for data storage'20097,515,368'Precompensation circuit for magnetic recording'20097,505,537'System and method for controlling gain and timing phase in a presence of a first least mean square filter using a second adaptive filter'20097,490,285'Marking unreliable symbols in a hard disk drive read back signal'20097,486,718'Architectures, circuits, systems and methods for reducing latency in data communications'20097,487,268'Long latency interface protocol'20097,479,904'Filter driven DC-free code'20097,480,121'Electrostatic discharge protection circuit for preamps connected to magneto-resistive read elements'20097,477,467'Preamp circuit including a loopback mode for data storage'20097,463,437'Demodulation compensation for spiral servo tracks in hard disk drives'20087,460,326'Propagation self servo write system and method for storage devices employing sector-servo scheme'20087,451,413'Methods of minimizing leakage current by analyzing post layout information and associated threshold voltage and leakage current'20087,440,209'Communications channel with programmable coupling'20087,423,901'Calibration system for writing and reading multiple states into phase change memory'20087,423,833'Servo loop employing correction vector from a secondary disturbance sensor to minimize correlation between servo loop error and disturbance sensor output'20087,411,755'Write driver system for data storage systems'20087,378,810'Method and apparatus for spindle motor control'20087,372,652'Correcting errors in disk drive read back signals by iterating with the Reed-Solomon decoder'20087,373,547'Self-reparable semiconductor and method thereof'20087,340,644'Self-reparable semiconductor and method thereof'20087,330,320'Method and apparatus to limit DC-level in coded data'20087,312,642'Continuous, wide-range frequency synthesis and phase tracking methods and apparatus'20077,313,723'Self-reparable semiconductor and method thereof'20077,307,806'Demodulation compensation for spiral servo tracks in hard disk drives'20077,307,807'Disk servo pattern writing'20077,304,545'High latency timing circuit'20077,298,294'Filter driven DC-free codes'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–1999Patents assigned to IBM (8)· patent assignee history
1994–2018Based in San Jose, CA, US· patent location history
2001–2019Patents assigned to MARVELL INT LTD (247)· patent assignee history
2006–2021Based in Los Gatos, CA, US· patent location history
2007–2018Patents assigned to MARVELL WORLD TRADE LTD (97)· patent assignee history
2010Based in Los Altos, CA, US· patent location history
2011–2016Patents assigned to SUTARDJA PANTAS (79)· patent assignee history
2011–2013Patents assigned to WU ZINING (15)· patent assignee history
2014Based in Los Angeles, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MARVELL INT LTD | 247 | 2001–2019 |
| MARVELL WORLD TRADE LTD | 97 | 2007–2018 |
| SUTARDJA PANTASself | 79 | 2011–2016 |
| WU ZINING | 15 | 2011–2013 |
| IBM | 8 | 1994–1999 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Gatos, California, US | 250 | 2006–2021 |
| San Jose, California, US | 112 | 1994–2018 |
| Los Angeles, California, US | 1 | 2014 |
| Los Altos, California, US | 1 | 2010 |