Semiconductor device

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-199453, filed on Aug. 1, 2008; the entire contents of which are incorporated herein by reference.

In semiconductor integrated circuit devices, high performance and high logic gate density integration of field-effect transistors are achieved by miniaturization of a gate length following the scaling rule and decreasing a thickness of a gate dielectric film. However, if a gate length of a field-effect transistor becomes equal to or smaller than 30 nanometers, the influence of a short-channel effect should be large, and a cutoff characteristic should be degraded. Therefore, to obtain a favorable cutoff characteristic, there has been proposed a double-gate transistor having fins formed on a silicon-on-insulator (SOI) substrate or on a bulk substrate, having a gate electrode manufactured to cross the fins, and having channels formed at both sides of each fin.

According to such a double-gate transistor, the variation of a threshold voltage is small, the output resistance can be large. If double gate transistors can be installed for the application of a base-band (low frequency) analog devices together with a digital devices, its fabrication cost can be reduced because they are fabricated by almost the same process on the same wafer.

For example, Japanese Patent Application Laid-open No. 2006-269975 discloses a method of reducing a parasitic resistance of fin portions of a fin field-effect transistor (FinFET) and suppressing the variation of the resistance between a source and a channel and between a drain and a channel of the FinFET, by crystal epi-growth of a semiconductor layer connecting between the fin portions, on an upper surface and side surfaces of the fin portions positioned at both sides of a gate electrode.

However, the double-gate transistor has a very small width of fins, has a large parasitic resistance, and has variation of the fin width. Therefore, if a base-band analog circuit is formed with a double-gate transistor with larger parasitic resistance by using a similar design method for a bulk transistor formed on a bulk substrate, sufficient gain cannot be achieved or the characteristic variation of the analog circuit should be degraded.

A semiconductor device according to an embodiment of the present invention comprises: N (N is an integer equal to or larger than 2) fins made of a semiconductor material aligned in parallel with each other; a gate electrode formed on both side surfaces of each of the N fins to cross the fins; source/drain layers formed in each of the N fins by sandwiching the gate electrode; a first wiring connected to one of the source/drain layers via a first contact formed in each of M fins (M is an integer equal to or larger than 2 and equal to or smaller than N); and a second wiring connected to the other one of the source/drain layers via a second contact formed in each of K fins (K is an integer smaller than M).

A semiconductor device according to an embodiment of the present invention comprises: N (N is an integer equal to or larger than 2) fins made of a semiconductor material aligned in parallel with each other; a first gate electrode formed on both side surfaces of each of the N fins to cross the fins; and a second gate electrode formed in parallel with the first gate electrode on both side surfaces of the N fins to cross the fins, wherein a gate length of the second gate electrode is larger than a gate length of the first gate electrode, and a constant current source is configured by a transistor having the second gate electrode.

A semiconductor device according to an embodiment of the present invention comprises: N (N is an integer equal to or larger than 2) fins made of a semiconductor material aligned in parallel with each other; a first gate electrode formed on both side surfaces of each of the N fins to cross the fins; and a second gate electrode formed in parallel with the first gate electrode on both side surfaces of the N fins to cross the fins, and having a larger gate length than a gate length of the first gate electrode, wherein the number of fins formed with contacts of source/drain layers of first field-effect transistors having the first gate electrode is larger than the number of fins formed with contacts of source/drain layers of second field-effect transistors having the second gate electrode.

FIG. 1 is a plan view of a layout configuration of a semiconductor device according to a first embodiment;

FIG. 2 is a perspective view of a schematic configuration of a portion B in FIG. 1 ;

FIG. 3 depicts an equivalent circuit of the semiconductor device shown in FIG. 1 ;

FIG. 4 is a plan view of a layout configuration of a semiconductor device according to a second embodiment;

FIG. 5 depicts an equivalent circuit of the semiconductor device shown in FIG. 4 ;

FIG. 6A is a plan view of a method of manufacturing a fin structure according to a third embodiment;

FIG. 6B is a cross-sectional view of FIG. 6A cut along a line A 1 -A 1 ′;

FIG. 7A is a plan view of the method of manufacturing a fin structure according to the third embodiment;

FIG. 7B is a cross-sectional view of FIG. 7A cut along a line A 2 -A 2 ′;

FIG. 8A is a plan view of the method of manufacturing a fin structure according to the third embodiment;

FIG. 8B is a cross-sectional view of FIG. 8A cut along a line A 3 -A 3 ′;

FIG. 9A is a plan view of the method of manufacturing a fin structure according to the third embodiment; and

FIG. 9B is a cross-sectional view of FIG. 9A cut along a line A 4 -A 4 ′.

Exemplary embodiments of a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments.

FIG. 1 is a plan view of a layout configuration of a semiconductor device according to a first embodiment.

In FIG. 1 , plural fins f 11 to f 19 and f 21 to f 29 are aligned in parallel with each other. Preferably, the width of each of the fins f 11 to f 19 and f 21 to f 29 is equal to each other, and the interval between fins of the fins f 11 to f 19 and f 21 to f 29 is equal to each other. Preferably, the total number of the fins f 11 to f 19 and the total number of the fins f 21 to f 29 are even numbers. A semiconductor material can be used for the material of the fins f 11 to f 19 and f 21 to f 29 . For examples, the material can be selected from Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, and GaInAsP.

For the fins f 13 to f 18 , gate electrodes G 11 are formed on both side surfaces of the fins f 13 to f 18 to cross the fins f 13 to f 18 . For the fins f 23 to f 28 , gate electrodes G 12 are formed on both side surfaces of the fins f 23 to f 28 to cross the fins f 23 to f 28 .

For the gate electrodes G 11 and G 12 , gate electrodes G 13 and G 14 are aligned in parallel at a predetermined interval, respectively. For the fins f 13 to f 18 , the gate electrodes G 13 are formed on both side surfaces of the fins f 13 to f 18 to cross the fins f 13 to f 18 . For the fins f 23 to f 28 , the gate electrodes G 14 are formed on both side surfaces of the fins f 23 to f 28 to cross the fins f 23 to f 28 .

Further, for the gate electrodes G 13 and G 14 , gate electrodes G 15 are aligned at a predetermined interval. For the fins f 13 to f 18 and f 23 to f 28 , the gate electrodes G 15 are formed on both side surfaces of the fins f 13 to f 18 and f 23 to f 28 to cross the fins f 13 to f 18 and f 23 to f 28 .

Preferably, the gate electrodes G 11 , G 12 , and G 15 can have a larger gate length than that of the gate electrodes G 13 and G 14 . Preferably, a drain resistance in a saturation region of transistors having the gate electrodes G 11 , G 12 , and G 15 is set to be assumed that it is substantially infinite (dI d /dV d =1/R d to 0). Preferably, a gate length of the gate electrodes G 13 and G 14 is set as small as possible to increase mutual conductance and to increase gain, and can be set equal to or smaller than 30 nanometers, for example.

Source/drain layers are formed in the fins f 13 to f 18 and f 23 to f 28 at both sides of the gate electrodes G 11 to G 15 , respectively. The source/drain layers formed in the fins f 13 to f 18 between the gate electrode G 11 and the gate electrode G 13 are shared by the gate electrodes G 11 and G 13 . The source/drain layers formed in the fins f 23 to f 28 between the gate electrode G 12 and the gate electrode G 14 are shared by the gate electrodes G 12 and G 14 . The source/drain layers formed in the fins f 13 to f 18 between the gate electrode G 13 and the gate electrode G 15 are shared by the gate electrodes G 13 and G 15 . The source/drain layers formed in the fins f 23 to f 28 between the gate electrode G 14 and the gate electrode G 15 are shared by the gate electrodes G 14 and G 15 .

The fins f 13 and f 15 at a drain side at the side of the gate electrodes G 11 are connected to a wiring H 11 via contacts C 11 , respectively. The fins f 23 and f 25 at a drain side at the side of the gate electrodes G 12 are connected to the wiring H 11 via contacts C 12 , respectively. The fins f 13 to f 18 at a source side at the side of the gate electrodes G 11 are connected to a wiring H 12 via contacts C 13 , respectively. The fins f 23 to f 28 at a source side at the side of the gate electrodes G 12 are connected to a wiring H 13 via contacts C 14 , respectively.

The fins f 13 to f 18 and f 23 to f 28 at a drain side at the side of the gate electrodes G 15 are connected to a wiring H 14 via contacts C 15 and C 16 , respectively. The fins f 14 to f 16 and f 24 to f 26 at a source side at the side of the gate electrodes G 15 are connected to a wiring H 15 via contacts C 17 and C 18 , respectively. Metals such as Al and Cu can be used for the material of the wirings H 11 to H 15 .

Preferably, the contacts C 1 to C 15 are symmetrically placed, respectively. Preferably, the gate electrodes G 11 and G 12 are aligned symmetrically with each other. Preferably, the gate electrodes G 13 and G 14 are aligned symmetrically with each other. Preferably, the wirings H 12 and H 13 are aligned symmetrically with each other. Embedded wirings formed on the fins f 13 to f 18 and f 23 to f 28 can be used for the contacts C 11 to C 15 .

Out of the fins f 11 to f 19 and f 21 to f 29 , the fins (f 11 & f 12 ) and (f 21 & f 22 ) can be used as dummy fins; They can not be used as a part of field-effect transistors.

FIG. 2 is a perspective view of a schematic configuration of a portion B in FIG. 1 .

In FIG. 2 , an isolation layer 12 is formed on a semiconductor substrate 11 , and the fins f 26 to f 28 are aligned in parallel on the isolation layer 12 . For the fins f 26 to f 28 , the gate electrodes G 14 are formed on both side surfaces of the fins f 26 to f 28 via gate dielectric films 13 a to 13 c , respectively. Upper insulation films 14 a to 14 c are formed between upper surfaces of the fins f 26 to f 28 and the gate electrodes G 14 .

Because of no intentional doping into the fins f 26 to f 28 , channels formed in the fins f 26 to f 28 can be fully depleted and can operate as an intrinsic channel device. To adjust a threshold voltage of field-effect transistors formed in the fins f 26 to f 28 , metal compounds such as titanium nitride, tantalum carbon, a lanthanum material, an aluminum material, and a magnesium material can be used as a single unit or in combination, for the material of the gate electrodes G 14 .

FIG. 3 depicts an equivalent circuit of the semiconductor device shown in FIG. 1 . The equivalent circuit is used for a common-mode feedback (CMFB) circuit or the like.

In FIG. 3 , a constant current source 21 is connected to a drain of a field-effect transistor 25 via a resistor 23 , and a constant current source 22 is connected to a drain of a field-effect transistor 26 via a resistor 24 . A constant current source 27 is connected in common to sources of the field-effect transistors 25 and 26 .

The constant current source 21 can be configured by the gate electrodes G 11 and the fins f 13 to f 18 shown in FIG. 1 . The constant current source 22 can be configured by the gate electrodes G 12 and the fins f 23 to f 28 shown in FIG. 1 . The field-effect transistor 25 can be configured by the gate electrodes G 13 and the fins f 13 to f 18 shown in FIG. 1 . The field-effect transistor 26 can be configured by the gate electrodes G 14 and the fins f 23 to f 28 shown in FIG. 1 . The constant current source 27 can be configured by the gate electrodes G 15 and the fins f 13 to f 19 and f 23 to f 29 shown in FIG. 1 . The resistor 23 can be related to parasitic resistances of the fins f 13 to f 18 between the gate electrode G 11 and the gate electrode G 13 . The resistor 24 can be related to parasitic resistances of the fins f 23 to f 28 between the gate electrode G 12 and the gate electrode G 14 .

The wiring H 11 shown in FIG. 1 is connected to a power source potential (voltage) V dd , and the wiring H 15 is connected to a ground potential (voltage) V ss . If input voltages V in1 and V in2 are applied to the gate electrodes G 13 and G 14 , respectively, output voltages V out1 and V out2 are output from the wirings H 12 and H 13 , respectively, thereby causing the field-effect transistors operate as differential amplifiers.

Even If the gate length is decreased, a short-channel effect can be suppressed enough thanks to the characteristics of the double-gate transistors for the field-effect transistors 25 and 26 shown in FIG. 3 . With double gate transistors, the gain can be increased even in the case of suppressing the short channel effect. Because a double-gate transistor is an intrinsic channel device, the double-gate transistor can suppress the variation of a threshold voltage, which is caused by random dopant fluctuation. A matching characteristics can be improved, even though the field-effect transistors 25 and 26 are differentially operated.

The fins f 11 to f 19 and f 21 to f 29 have a small fin width. Although the parasitic resistance of each of the fins f 11 to f 19 and f 21 to f 29 is large, the parasitic resistance between the gate electrode G 11 and the gate electrode G 13 , and the parasitic resistance between the gate electrode G 12 and the gate electrode G 14 can be decreased by increasing the numbers of the fins f 11 to f 19 and f 21 to f 29 . Therefore, the reduction of the gain can be suppressed. To decrease the parasitic resistance between the gate electrode G 11 and the gate electrode G 13 , the interval between the gate electrode G 11 and the gate electrode G 13 is preferably as small as possible, and the gate electrodes G 11 and G 13 can be superimposed with the wiring H 12 . To decrease the parasitic resistance between the gate electrode G 12 and the gate electrode G 14 , the interval between the gate electrode G 12 and the gate electrode G 14 is preferably as small as possible, and the gate electrodes G 12 and G 14 can be superimposed with the wiring H 13 .

By setting the gate length of the gate electrodes G 11 , G 12 , and G 15 larger than the gate length of the gate electrodes G 13 and G 14 , double-gate transistors can be used for the constant current sources 21 and 22 shown in FIG. 3 . The constant current sources 21 and 22 for supplying a constant current to the field-effect transistors 25 and 26 can be formed in the same fins.

If the fins f 11 to f 19 and f 21 to f 29 are aligned at equal intervals, transistors can be formed by a pattern having a simple repetition of a straight line and a space. Therefore, the sizes of the fins f 11 to f 19 and f 21 to f 29 can be easily managed, and size controllability of the fins f 11 to f 19 and f 21 to f 29 can be improved. Consequently, a matching characteristic of a differential analog circuit can be improved.

The numbers of the fins f 11 to f 19 and f 21 to f 29 are set to even numbers to have the symmetrical geometry therefore, the fins f 11 to f 19 and f 21 to f 29 can be formed by a sidewall transfer process which forms the fin-fin pair. Further, an arrangement pitch of the fins f 11 to f 19 and f 21 to f 29 can be reduced by the sidewall transfer process.

Out of the fins f 11 to f 19 and f 21 to f 29 , the fins f 11 , f 12 , f 21 , and f 22 are aligned at both ends, and are used as dummy fins. Therefore, such field-effect transistors can be manufactured, having the pattern regularity for the lithography and the etching process. Further, the variation of a direct current (DC) characteristic of a threshold voltage and the like can be suppressed, and the degradation of short-channel effect can be also suppressed, because of the excellent pattern regularity.

For example, the fins f 11 to f 19 and f 21 to f 29 are aligned from the device region to device isolation region; i.e. from the region where fins are regularly placed to the region where the fins are placed without the same regularity. In a portion which suddenly changes the pattern regularity to near an isolated pattern, an etching condition should be changed, and the bottom portions of the fins f 11 , f 12 , f 21 , and f 22 become thick in a tapered shape. Even at a time of applying lithography, the sizes of fins aligned at both ends are deviated from the sizes of fins aligned at the inside.

Therefore, if a field effect transistor is manufactured with enough pattern regularity, a variability of DC characteristics of the field-effect transistor can be improved.

If the numbers of the contacts C 13 to C 16 connected to the wirings H 12 to H 14 are set larger than the numbers of the contacts C 11 , C 12 , C 17 , and C 18 connected to the wirings H 11 and H 15 , an effective channel width (=number of fins×height of fins×2) of a current flowing through the field-effect transistors 25 and 26 in FIG. 3 can be increased, and an effective channel width of a current flowing through the constant current sources 21 and 22 in FIG. 3 can be decreased at the same time.

Therefore, while decreasing (drain) conductance of the constant current sources 21 and 22 , a current flowing through the field-effect transistors 25 and 26 can be increased, and the frequency response of the field-effect transistors 25 and 26 can be improved.

If the contacts C 11 to C 15 are symmetrically aligned, a current path can be shortened because a current, entering the fins f 14 and f 16 via the contacts C 11 , can be spread to whole drain region of the field-effect transistor 25 . Even though the number of the contacts C 11 connected to the wiring H 11 is limited, increase of a delay time can be also suppressed thanks to the symmetrical contact allocation.

In the first embodiment, a method of using the fins f 11 , f 12 , f 21 , and f 22 aligned at both ends as dummy fins, out of the fins f 11 to f 19 and f 21 to f 29 , is explained. Instead of using each two fins of the fins f 11 , f 12 , f 21 , and f 22 aligned at both ends as dummy fins, each one of the fins aligned at both ends can be also used as a dummy fin. Alternatively, three or more fins aligned at both ends can be used as dummy fins.

In the first embodiment, a method of forming the contacts C 11 and C 12 is also explained which are connected to the wiring H 11 , in only the fins f 14 , f 16 , f 24 , and f 26 . However, the number of the contacts C 11 and C 12 connected to the wiring H 11 is not necessarily limited to two, and can be any number larger than that of the contacts C 13 and C 14 connected to the wirings H 12 and H 13 , respectively. For example, the contacts C 11 and C 12 connected to the wiring H 11 can be aligned to be formed in only the fins f 15 and f 25 , respectively, or can be aligned to be formed in only the fins f 13 , f 15 , f 17 , f 23 , f 25 , and f 27 , respectively.

In the first embodiment, a method of forming the contacts C 17 and C 18 is also explained which are connected to the wiring H 15 , in only the fins f 14 , f 16 , f 24 , and f 26 , respectively. However, the number of the contacts C 17 and C 18 connected to the wiring H 15 is not necessarily limited to two, and can be any number larger than that of the contacts C 15 and C 16 connected to the wiring H 14 . For example, the contacts C 17 and C 18 connected to the wiring H 15 can be aligned to be formed in only the fins f 15 and f 25 , respectively, or can be aligned to be formed in only the fins f 13 , f 15 , f 17 , f 23 , f 25 , and f 27 , respectively.

A relationship between the gain (=voltage gain) A of the circuit and a resistance value R 1 of the resistors 23 and 24 is explained below by the following equations.

If V in1 and V in2 represent input voltages of the circuit, and also If V out1 and V out2 represent output voltages of the circuit, basic equations of the circuit shown in FIG. 3 are given by equations (1) to (7) as follows.

In the above equations, G 1 , G 2 , and G 3 represent (drain) conductance of the constant current sources 21 and 22 , respectively, and I 1 , I 2 , and I 1 +I 2 represent currents flowing through the constant current sources 21 and 22 , respectively. V dd represents a power source potential, g m represents mutual conductance of the field-effect transistors 25 and 26 , V a represents a source potential of the field-effect transistors 25 and 26 , V b1 and V b2 represent drain potentials of the field-effect transistors 25 and 26 , respectively, and r ds represents an inclination of an I d −V d characteristic of the field-effect transistors 25 and 26 . I d represents a drain current of the field-effect transistors 25 and 26 , and V d represents a drain voltage of the field-effect transistors 25 and 26 .

I 1 and I 2 are obtained from the basic equations of equations (1) to (7), and a relationship between the input voltages V in1 and V in2 and the output voltages V out1 and V out2 is finally obtained.

First, equations (8) and (9) are obtained as follows, by the equations (1), (4), and (5).

Next, equations (10) and (11) are obtained as follows by subtracting V b1 and V b2 from the equations (8) and (9) by using the equations (2) and (3).

Equations (12) and (13) are obtained as follows by arranging the equations (10) and (11) by I 1 and I 2 .

An equation (14) is obtained as follows by writing the equations (12) and (13) by using a matrix and a vector format.

An equation (15) is obtained as follows by solving I 1 and I 2 by the equation (14).

In the above equations, α is defined by an equation (16) shown below.

I 1 and I 2 are solved by the equations (6) and (7), and are changed into a matrix and a vector format, thereby obtaining an equation (17) as follows.

I 1 and I 2 are erased from the equations (15) and (17), thereby obtaining an equation (18) as follows.

In the above equation, β is defined by an equation (19) shown below.

β≡αr ds   (19)

M is defined by an equation (20) shown below.

V out1 and V out2 are solved by the equation (18), thereby obtaining equations (21) and (22) as follows.

In the above equations, a and b are defined by an equation (23) shown below.

A differential voltage V out2 −V out1 is obtained by the equations (21) and (22), thereby obtaining an equation (24) as follows.

The gain A of this circuit is defined as A=|(V out2 −V out1 )/(V in2 −V in1 )|, therefore, the gain A can be expressed by the equation (24) to an equation (25).

It is clear from the equation (25) that if the (drain) conductance of the constant current sources 21 and 22 and the resistors 23 and 24 cannot be disregarded, to increase the gain A, either g m ×r ds is increased, or G 1 is decreased, or R 1 is decreased.

If a condition of G 1 ×R 1 <g m ×r ds for the third term of the denominator is satisfied, the gain A can be increased even though the resistors 23 and 24 cannot be disregarded.

FIG. 4 is a plan view of a layout configuration of a semiconductor device according to a second embodiment of the present invention.

In FIG. 4 , plural fins f 31 to f 38 and f 41 to f 48 are aligned in parallel with each other. Preferably, the width of each of the fins f 31 to f 38 and f 41 to f 48 is equal to each other, and the interval between fins of the fins f 31 to f 38 and f 41 to f 48 is equal to each other. Preferably, the total number of the fins f 31 to f 38 and the total number of the fins f 41 to f 48 are even numbers. A semiconductor material can be used for the material of the fins f 31 to f 38 and f 41 to f 48 . For example, the material can be selected from Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, and GaInAsP.

For the fins f 33 to f 38 and f 43 to f 48 , gate electrode G 21 is formed on both side surfaces of the fins f 33 to f 38 and f 43 to f 48 to cross the fins f 33 to f 38 and f 43 to f 48 .

For the gate electrodes G 21 , gate electrodes G 22 and G 23 are aligned in parallel at a predetermined interval. For the fins f 33 to f 37 , the gate electrode G 22 is formed on both side surfaces of the fins f 33 to f 37 to cross the fins f 33 to f 37 . For the fins f 43 to f 47 , the gate electrode G 23 is formed on both side surfaces of the fins f 43 to f 47 to cross the fins f 43 to f 47 .

For the gate electrodes G 22 and G 23 , gate electrode G 24 is aligned in parallel at a predetermined interval. For the fins f 33 to f 37 and f 43 to f 47 , the gate electrode G 24 is formed on both side surfaces of the fins f 33 to f 37 and f 43 to f 47 to cross the fins f 33 to f 37 and f 43 to f 47 .

Preferably, the gate electrode G 21 can have a larger gate length than that of the gate electrodes G 22 to G 24 . Preferably, a drain resistance in a saturation region of transistors having the gate electrode G 21 is set to be assumed that it is substantially infinite (dI d /dV d =1/R d to 0). Preferably, the gate length of the gate electrodes G 22 to G 24 is set as small as possible to increase mutual conductance and to increase gain, and can be set equal to or smaller than 30 nanometers, for example.

Source/drain layers are formed in the fins f 34 to f 37 and f 44 to f 47 at both sides of the gate electrodes G 21 to G 24 , respectively. The source/drain layers formed in the fins f 34 to f 37 between the gate electrode G 21 and the gate electrode G 22 are shared by the gate electrodes G 21 and G 22 . The source/drain layers formed in the fins f 44 to f 47 between the gate electrodes G 21 and G 23 are shared by the gate electrodes G 21 and G 23 . The source/drain layers formed in the fins f 34 to f 37 between the gate electrodes G 22 and G 24 are shared by the gate electrodes G 22 and G 24 . The source/drain layers formed in the fins f 44 to f 47 between the gate electrodes G 23 and G 24 are shared by the gate electrodes G 23 and G 24 .

The fins f 34 to f 37 and f 44 to f 47 at a drain side at the side of the gate electrode G 21 is connected to a wiring H 21 via contacts C 21 and C 22 , respectively. The fins f 34 to f 37 at a source side at the side of the gate electrode G 21 is connected to a wiring H 23 via contacts C 23 . The fins f 44 to f 47 at a source side at the side of the gate electrode G 21 is connected to a wiring H 24 via contacts C 24 . The fins f 34 to f 37 and f 44 to f 47 at a source side at the side of the gate electrode G 24 is connected to a wiring H 27 via contacts C 25 and C 26 , respectively.

The gate electrode G 21 is connected to a wiring H 22 via contacts C 27 and C 28 , respectively. The gate electrode G 22 is connected to a wiring H 25 via contacts C 29 , and the gate electrode G 23 is connected to the wiring H 25 via contacts C 30 . The gate electrode G 24 is connected to a wiring H 26 via contacts C 31 . Metals such as Al, AlSiCu or Cu can be used for the material of the wirings H 21 to H 27 .

Preferably, the contacts C 22 to C 26 are symmetrically aligned, respectively. Preferably, the gate electrodes G 22 and G 23 are aligned symmetrically with each other, and preferably, the wirings H 23 and H 24 are aligned symmetrically with each other. Embedded wirings formed on the fins f 34 to f 37 and f 44 to f 47 can be used for the contacts C 21 to C 26 .

Out of the fins f 31 to f 38 and f 41 to f 48 , the fins f 31 to f 32 and f 41 and f 42 , those are aligned at both ends, can be used as dummy fins; They can not be used as a part of field-effect transistors.

FIG. 5 depicts an equivalent circuit of the semiconductor device shown in FIG. 4 . The equivalent circuit is used for a mixer circuit or the like.

In FIG. 5 , resistors 33 and 34 are connected to drains of field-effect transistors 35 and 36 , respectively. A drain of a field-effect transistor 37 is connected in common to sources of the field-effect transistor 35 and 36 . The resistors 33 and 34 can be configured by constant current sources.

The resistor 33 can be configured by the gate electrode G 21 and the fins f 34 to f 37 shown in FIG. 4 . The resistor 34 can be configured by the gate electrode G 21 and the fins f 44 to f 47 shown in FIG. 4 . The field-effect transistor 35 can be configured by the gate electrode G 22 and the fins f 34 to f 37 shown in FIG. 4 . The field-effect transistor 36 can be configured by the gate electrode G 23 and the fins f 44 to f 47 shown in FIG. 4 . The field-effect transistor 37 can be configured by the gate electrode G 24 and the fins f 34 to f 37 and f 44 to f 47 shown in FIG. 4 .

The wiring H 21 shown in FIG. 4 is connected to the power source potential V dd , and the wiring H 27 is connected to the ground potential V ss . If the input voltages V in1 and V in2 are input to the gate electrodes G 22 and G 23 , respectively, and also if an input voltage IN 2 is input to the gate electrode G 24 , the output voltages V out1 and V out2 are output from the wirings H 23 and H 24 , respectively. As a result, a product of an input voltage IN 1 =V in1 −V in2 and an input voltage IN 2 is output as an output voltage OUT=V out1 −V out2 , thereby causing the field-effect transistors operate as mixers (multipliers).

Even though a gate length is decreased, a short-channel effect can be suppressed by using double-gate transistors for the field-effect transistors 35 to 37 shown in FIG. 5 . Gain can be increased while suppressing degradation of a cutoff characteristic. A matching characteristic if the field-effect transistors 35 and 36 are differentially operated can be improved.

If the gate electrodes G 22 and G 23 are aligned to cross the plural fins f 34 to f 37 and f 44 to f 47 , respectively, the parasitic resistance between the gate electrodes G 21 and G 22 and the parasitic resistance between the gate electrodes G 21 and G 23 can be decreased. Therefore, reduction of gain can be suppressed.

To decrease the parasitic resistance between the gate electrodes G 21 and G 22 , the interval between the gate electrodes G 21 and G 22 is preferably as small as possible. It is also required that the gate electrodes G 21 and G 22 can be superimposed with the wiring H 23 . To decrease the parasitic resistance between the gate electrodes G 21 and G 23 , the interval between the gate electrodes G 21 and G 23 is preferably as small as possible. It is also required that the gate electrodes G 21 and G 23 can be superimposed with the wiring H 23 .

If the gate length of the gate electrodes G 21 is set larger than that of the gate electrodes G 22 to G 24 , double-gate transistors can work as the resistors 33 and 34 , as shown in FIG. 4 . The resistors 33 and 34 connected to the field-effect transistors 35 and 36 can be formed in the same fins.

If the fins f 31 to f 38 and f 41 to f 48 are aligned at equal intervals, fin size controllability for the fins f 31 to f 38 and f 41 to f 48 can be improved. Consequently, a matching characteristic of a differential analog circuit can be improved.

The numbers of the fins f 31 to f 38 and f 41 to f 48 are set to even numbers, therefore, symmetry can be improved. The fins f 31 to f 38 and f 41 to f 48 can be formed by a sidewall transfer process. Further, an arrangement of the fins f 31 to f 38 and f 41 to f 48 can be reduced.

Out of the fins f 31 to f 38 and f 41 to f 48 , the fins f 11 , f 12 , f 21 , and f 22 are aligned at both ends, and are used as dummy fins. Therefore, such field-effect transistors can be manufactured, having the pattern regularity for the lithography and the etching process. Further, the variation of a DC characteristic of a threshold voltage and the like can be suppressed, and the degradation of short-channel effect can be also suppressed, because of the excellent pattern regularity.

If the numbers of the contacts C 23 to C 26 connected to the wirings H 23 , H 24 , and H 27 are set larger than the numbers of the contacts C 21 and C 22 connected to the wiring H 21 , conductance of the resistors 33 and 34 can be decreased, and a current flowing to the field-effect transistors 35 and 36 can be increased, thereby improving the speed of the field-effect transistors 35 and 36 .

If the contacts C 21 to C 26 are symmetrically aligned, a current path can be shortened because a current, entering the fins f 34 and f 36 via the contacts C 21 , can be spread to whole drain region of the field-effect transistor 35 .

Even though the number of the contacts C 11 connected to the wiring H 11 is limited, increase of a delay time can be also suppressed thanks to the symmetrical contact allocation.

In the second embodiment, a method of using the fins f 31 , f 32 , f 41 , and f 42 , aligned at both ends as dummy fins out of the fins f 31 to f 38 and f 41 to f 48 , is explained. Instead of using each two fins of the fins f 31 , f 32 , f 41 , and f 42 aligned at both ends as dummy fins, each one of the fins aligned at both ends can be also used as a dummy fin. Alternatively, three or more fins aligned at both ends can be used as dummy fins.

In the second embodiment, a method of forming the contacts C 21 and C 22 connected to the wiring H 21 is explained, in only the fins f 34 , f 36 , f 44 , and f 46 . However, the number of the contacts C 21 and C 22 connected to the wiring H 21 is not necessarily limited to two, and can be any number larger than that of the contacts C 23 and C 24 connected to the wirings H 23 and H 24 , respectively.

FIGS. 6A , 7 A, 8 A, and FIG. 9A are plan views of a method of manufacturing a fin structure according to a third embodiment of the present invention, and FIGS. 6B , 7 B, 8 B, and FIG. 9B are cross-sectional views of FIGS. 6A , 7 A, 8 A, and FIG. 9A , cut along a line A 1 -A 1 ′, line A 2 -A 2 ′, line A 3 -A 3 ′, and line A 4 -A 4 ′, respectively.

In FIGS. 6A and 6B , a semiconductor layer 53 is formed on a semiconductor substrate 51 via an insulation layer 52 . For the semiconductor substrate 51 on which the semiconductor layer 53 is formed via the insulation layer 52 , an SOI substrate can be used, for example.

Dummy patterns R 1 made of a first material are formed on the semiconductor layer 53 . For the dummy patterns R 1 , linear patterns aligned in parallel with each other at a predetermined interval can be used. The interval between the dummy patterns R 1 can be set as 2×F+H, where F represents the width of each fin 54 formed on the insulation layer 52 , and H represents the interval between the finally formed fins 54 .

As shown in FIGS. 7A and 7B , an insulation film made of a second material is formed on the semiconductor layer 53 so that a gap between the dummy patterns R 1 is filled. By etching the insulation film by using anisotropic etching such as reactive ion etching (RIE), sidewall patterns R 2 and R 3 are formed on sidewalls of the dummy patterns R 1 . Film thicknesses of the sidewall patterns R 2 and R 3 can be controlled by an initial film thickness of the insulation film formed on the semiconductor layer 53 and by an etching time.

The dummy patterns R 1 are etched by using a difference of etching rate (=by utilizing etching selectivity) between the first material and the second material. Then, the dummy patterns R 1 are removed from the semiconductor layer 53 by leaving the sidewall patterns R 2 and R 3 on the semiconductor layer 53 , as shown in FIGS. 8A and 8B .

Anisotropic etching such as RIE is performed to the semiconductor layer 53 by using the sidewall patters R 2 and R 3 as etching masks, thereby forming the fins 54 on the insulation layer 52 , as shown in FIGS. 9A and 9B .

By the above arrangement, the fins 54 can be formed at a pitch two times of the resolution limit of a lithography process. As a result, the density of the fins 54 can be increased.

If the fins 54 are formed on the insulation layer 52 , gate electrodes are formed on both side surfaces of the fins 54 to cross the fins 54 via gate dielectric films, and source/drain layers of the fins 54 are connected to a wiring via contacts, thereby manufacturing double-gate transistors shown in FIG. 1 or FIG. 4 .

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.