Embedded electronic component package fabrication method

The present Application is a divisional of Huemoeller et al., U.S. patent application Ser. No. 11/298,016, entitled “EMBEDDED ELECTRONIC COMPONENT PACKAGE” filed Dec. 8, 2005, which is herein incorporated by reference in its entirety.

1. Field of the Invention

The present invention relates generally to the packaging of electronic components. More particularly, the present invention relates to an embedded electronic component package and method of fabricating the same.

2. Description of Related Art

One form of an electronic component package included an electronic component such as an integrated circuit chip mounted to a substrate. For example, in a wirebond configuration, the rear surface of the integrated circuit chip was mounted to the substrate, e.g., with an adhesive. Bond wires were used to form the electrical interconnections between the bond pads on the front surface of the integrated circuit chip and the electrically conductive traces on the substrate.

As the art moved to smaller and lighter weight electronic devices, it became increasingly important that the size of the electronic component package used within these electronic devices be as small as possible. However, in the wirebond configuration described above, the traces of the substrate were fanned out around the integrated circuit chip, which placed a fundamental restriction on the minimum electronic component package size. Further, a large impedance was associated with the bond wires.

To allow a further reduction in the electronic component package size as well as to reduce impedance of the interconnections, a flip chip configuration was used instead of a wirebond configuration. In a flip chip configuration, the bond pads on the front surface of the integrated circuit chip were directly connected to the traces on the substrate with flip chip bumps, e.g., solder. This avoided the need to fan out the traces around the integrated circuit chip resulting in a minimum package size. Further, the use of flip chip bumps between the bond pads and the traces on the substrate minimized impedance.

However, the flip chip bumps between the bond pads of the integrated circuit chip and the traces on the substrate were subject to significant stress, e.g., due to differential thermal expansion between the integrated circuit chip and the substrate. Thus, failure of the flip chip bumps often occurred which, in turn, decreased yield and increased the cost of the electronic component package.

To minimize the failure of the flip chip bumps, an underfill material was often applied between the integrated circuit chip and the substrate and around the flip chip bumps. However, the application of the underfill material required an additional manufacturing step and materials, which increased the cost of the electronic component package.

In addition, prior art packages typically were mounted to a substrate, such as a motherboard, such that the entire electronic component, and or package, was situated above the surface of the substrate. Consequently, the electronic connections to the substrate, and the electronic component itself, were extremely vulnerable to stress and breakage.

In addition, the prior art mounting to a substrate, such as a motherboard, with the entire electronic component, and or package, situated above the surface of the substrate meant precious substrate surface area was wasted and the resulting device was larger than ideal.

In accordance with one embodiment of the present invention, a method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads.

Thus, in accordance with this embodiment of the present invention, the bond pads are directly connected to the corresponding first vias. Stated another way, the bond pads are electrically connected to the corresponding first vias without the use of a solder, e.g., without the use of flip chip bumps, and without the need to form a solder wetting layer, e.g., a nickel/gold layer, on the bond pads. This maximizes the reliability of the electrical connection between the first vias and the bond pads, while at the same time minimizes impedance.

Further, since the dielectric strip is directly attached to the electronic component and the bond pads are directly connected to the corresponding first vias, the use of an underfill material is obviated. This simplifies manufacturing, enhances reliability, and thus reduces cost.

In one embodiment of the present invention, a method of forming an embedded electronic component package includes coupling a first surface of a substrate, such as a motherboard, to a second surface of a first dielectric layer, strip, or panel. Then the method and structure of this embodiment of the invention includes forming first via apertures and trace trenches through the first dielectric layer, to expose selected locations on the substrate first surface, and filling the first via apertures and trace trenches with an electrically conductive material to form first electrically conductive vias and traces.

According to this embodiment of the invention, a cavity is then formed in the first surface of the first dielectric layer. An electronic component, such as an integrated circuit, active component, or passive component, is then attached to a bottom surface of the cavity, with a first surface of the electronic component, including bond pads, being either level with, partially below, or partially above the first surface of the first dielectric layer. Once the electronic component is situated in the cavity, a second dielectric layer is applied to the first dielectric layer, thereby encasing the electronic component in dielectric. Then the method and structure of this embodiment of the invention includes forming second via apertures through the second dielectric layer to expose the bond pads and/or the first electrically conductive vias and traces; and filling the second via apertures with an electrically conductive material to form second electrically conductive vias electrically coupled to the bond pads and first electrically conductive vias and traces.

In another embodiment of the invention the first surface of an electronic component is attached to a first surface of a first dielectric strip and then the cavity is formed around the electronic component by laminating two or more layers of a dielectric, such as prepreg material, around and over the electronic component and then curing the dielectric material to encase the electronic component.

Thus, in accordance with these embodiments of the present invention, the electronic component is encased in dielectric material. Consequently, the electronic connections to the substrate, and the electronic component itself, are protected and less vulnerable to stress and breakage than prior art systems. In addition, in the one embodiment with the electronic component encased in dielectric material at least partially below the first surface of the first dielectric layer, in accordance with the present invention, surface area is no longer wasted and the resulting device can be made smaller than prior art devices.

According to this embedded electronic component embodiment of the invention, the bond pads and first electrically conductive vias and traces are directly connected to the corresponding second electrically conductive vias. Stated another way, the bond pads and first electrically conductive vias and traces are electrically connected to the corresponding second electrically conductive vias, and the first surface of the second dielectric layer, without the use of a solder, e.g., without the use of flip chip bumps, and without the need to form a solder wetting layer, e.g., a nickel/gold layer, on the bond pads. This maximizes the reliability of the electrical connection between the second electrically conductive vias, and the first surface of the second dielectric layer, and the bond pads and first electrically conductive vias and traces, while at the same time minimizing impedance and allowing for more direct connections and less routing.

Further, since, according to this embodiment of the invention, the electronic component is virtually encased in dielectric material, and the second dielectric layer is attached directly to the first surface of the electronic component, use of an underfill material is obviated. This simplifies manufacturing, enhances reliability, and thus reduces cost.

The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

FIG. 1A is a cross-sectional view of an assembly during the fabrication of a plurality of wafer level electronic component packages in accordance with one embodiment of the present invention;

FIG. 1B is a cross-sectional view of an assembly during the fabrication of a plurality of wafer level electronic component packages in accordance with another embodiment of the present invention;

FIGS. 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 and 11 are cross-sectional views of the assembly of FIG. 1B at further stages during the fabrication of a plurality of wafer level electronic component packages in accordance with various embodiments of the present invention;

FIG. 12 is a cross-sectional view of an assembly during the fabrication of a plurality of wafer level electronic component packages in accordance with another embodiment of the present invention;

FIG. 13 is a cross-sectional view of the assembly of FIG. 12 at a further stage during the fabrication of a plurality of wafer level electronic component packages in accordance with one embodiment of the present invention;

FIG. 14A shows one embodiment of a cross section of an embedded electronic component package sub-assembly in accordance with the principles of the present invention;

FIG. 14B shows one embodiment of a cross section of the embedded electronic component package sub-assembly of FIG. 14A further in the processing cycle in accordance with the principles of the present invention;

FIG. 14C shows one embodiment of a cross section of the embedded electronic component package sub-assembly of FIG. 14B further in the processing cycle in accordance with the principles of the present invention;

FIG. 14D shows one embodiment of a cross section of the embedded electronic component package sub-assembly of FIG. 14C further in the processing cycle in accordance with the principles of the present invention;

FIG. 14E shows one embodiment of a cross section of the embedded electronic component package sub-assembly of FIG. 14D further in the processing cycle in accordance with the principles of the present invention;

FIG. 14F shows one embodiment of a cross section of the embedded electronic component package sub-assembly of FIG. 14E further in the processing cycle in accordance with the principles of the present invention;

FIG. 14G shows an angled perspective view of the structure of FIG. 14F in accordance with the principles of the present invention;

FIG. 14H shows one embodiment of a cross section of the embedded electronic component package sub-assembly of FIG. 14F further in the processing cycle in accordance with the principles of the present invention;

FIG. 14I shows a angled perspective view of structure of FIG. 14H in accordance with the principles of the present invention;

FIG. 14J shows one embodiment of a cross section of the embedded electronic component package sub-assembly of FIG. 14H further in the processing cycle in accordance with the principles of the present invention;

FIG. 14K shows one embodiment of a cross section of the embedded electronic component package sub-assembly of FIG. 14J further in the processing cycle in accordance with the principles of the present invention; and

FIG. 14L shows one embodiment of a cross section of an embedded electronic component package sub-assembly in accordance with the principles of the present invention;

FIG. 15A shows one embodiment of a cross section of an encased electronic component package sub-assembly in accordance with the principles of the present invention;

FIG. 15B shows one embodiment of a cross section of the encased electronic component package sub-assembly of FIG. 15A further in the processing cycle in accordance with the principles of the present invention;

FIG. 15C shows one embodiment of a cross section of the encased electronic component package sub-assembly of FIG. 15B further in the processing cycle in accordance with the principles of the present invention;

FIG. 15D shows one embodiment of a cross section of the encased electronic component package sub-assembly of FIG. 15C further in the processing cycle in accordance with the principles of the present invention;

FIG. 15E shows one embodiment of a cross section of the encased electronic component package sub-assembly of FIG. 15D further in the processing cycle in accordance with the principles of the present invention;

FIG. 15F shows one embodiment of a cross section of the encased electronic component package sub-assembly of FIG. 15E further in the processing cycle in accordance with the principles of the present invention;

FIG. 15G shows one embodiment of a cross section of the encased electronic component package sub-assembly of FIG. 15F further in the processing cycle in accordance with the principles of the present invention;

FIG. 15H shows one embodiment of a cross section of the encased electronic component package sub-assembly of FIG. 15G further in the processing cycle in accordance with the principles of the present invention;

FIG. 15I shows an overhead view of a pre-punched dielectric layer as used in one embodiment of the structure of FIG. 15H in accordance with the principles of the present invention;

FIG. 15J shows one embodiment of a cross section of the encased electronic component package sub-assembly of FIG. 15H further in the processing cycle in accordance with the principles of the present invention;

FIG. 15K shows one embodiment of a cross section of the encased electronic component package sub-assembly of FIG. 15J further in the processing cycle in accordance with the principles of the present invention;

FIG. 15L shows one embodiment of a cross section of an encased electronic component package sub-assembly in accordance with the principles of the present invention.

FIG. 15M shows one embodiment of a cross section of an encased electronic component package sub-assembly in accordance with the principles of the present invention; and

FIG. 15N shows one embodiment of a cross section of an encased electronic component package sub-assembly in accordance with the principles of the present invention.

Common reference numerals are used throughout the drawings and detailed description to indicate like elements.

In accordance with one embodiment of the present invention, a method of forming an electronic component package includes coupling first surfaces 106 F of electronic components 106 to a first surface 108 U of a dielectric strip 108 with adhesives 110 or 120 ( FIGS. 1A and 1B ), electronic components 106 having bond pads 112 on first surfaces 106 F; forming via apertures 522 through dielectric strip 108 to expose bond pads 112 ( FIG. 5 ); and filling via apertures 522 with an electrically conductive material to form vias 624 electrically coupled to bond pads 112 ( FIG. 6 ).

Thus, in accordance with this embodiment of the present invention, bond pads 112 are directly connected to corresponding vias 624 . Stated another way, bond pads 112 are electrically connected to corresponding vias 624 without the use of a solder, e.g., without the use of flip chip bumps, and without the need to form a solder wetting layer, e.g., a nickel/gold layer, on bond pads 112 . This maximizes the reliability of the electrical connection between vias 624 and bond pads 112 , while at the same time minimizes impedance.

In one embodiment of the present invention, a method of forming an embedded electronic component package includes coupling a first surface ( 1406 in FIG. 14A ) of a substrate ( 1402 in FIG. 14A ), such as a motherboard, to a second surface ( 1405 in FIG. 14B ) of a first dielectric layer, strip, or panel ( 1408 in FIG. 14B ). Then the method and structure of this embodiment of the invention includes forming first via apertures ( 1422 in FIG. 14C ) and trace trenches ( 1423 in FIG. 14C ) through the first dielectric layer, to expose selected locations on the substrate first surface (not shown), and filling the first via apertures and trace trenches with an electrically conductive material to form first electrically conductive vias ( 1424 in FIG. 14E ) and traces ( 1425 in FIG. 14E ).

According to this embodiment of the invention, a cavity ( 1430 in FIGS. 14F and 14G ) is then formed in the first surface of the first dielectric layer. An electronic component ( 1440 in FIGS. 14H and 141 ), such as an integrated circuit, active component, or passive component, is then attached to a bottom surface ( 1433 in FIG. 14H ) of the cavity, with a first surface of the electronic component ( 1441 in FIGS. 14H and 141 ), including bond pads ( 1445 in FIGS. 14J and 1445A , 1445 B, 1445 C in FIG. 14K ), being either level with, partially below, or partially above the first surface of the first dielectric layer. Once the electronic component is situated in the cavity, a second dielectric layer, strip, or panel ( 1448 in FIG. 14K ) is applied to the first dielectric layer, thereby encasing the electronic component in dielectric. Then the method and structure of this embodiment of the invention includes forming second via apertures ( 1460 A, 1460 B, 1460 C, 1460 D and 1460 E in FIG. 14K ) through the second dielectric layer to expose the bond pads and/or the first electrically conductive vias and traces; and filling the second via apertures with an electrically conductive material to form second electrically conductive vias ( 1461 A, 1461 B, 1461 C, 1461 D, 1461 E in FIG. 14L ) electrically coupled to the bond pads and first electrically conductive vias and traces.

Thus, in accordance with this embodiment of the present invention, the electronic component is encased in dielectric material at least partially below the first surface of the first dielectric layer. Consequently, the electronic connections to the substrate, and the electronic component itself, are protected and less vulnerable to stress and breakage than prior art systems. In addition, with the electronic component encased in dielectric material at least partially below the first surface of the first dielectric layer, and below the first surface of the second dielectric layer, in accordance with the present invention, surface area, i.e., area of the first surface of the second dielectric layer is no longer wasted and the resulting device can be made smaller than prior art devices.

According to this embodiment of the invention, the bond pads and first electrically conductive vias and traces are directly connected to the corresponding second electrically conductive vias. Stated another way, the bond pads and first electrically conductive vias and traces are electrically connected to the corresponding second electrically conductive vias, and the first surface of the second dielectric layer, without the use of a solder, e.g., without the use of flip chip bumps, and without the need to form a solder wetting layer, e.g., a nickel/gold layer, on the bond pads. This maximizes the reliability of the electrical connection between the second electrically conductive vias, and the first surface of the second dielectric layer, and the bond pads and first electrically conductive vias and traces, while at the same time minimizing impedance and allowing for more direct connections and less routing.

Further, since, according to this embodiment of the invention, the electronic component is virtually encased in dielectric material, and the second dielectric layer is attached directly to the first surface of the electronic component, use of an underfill material is obviated. This simplifies manufacturing, enhances reliability, and thus reduces cost.

More particularly, FIG. 1A is a cross-sectional view of an assembly 100 A during the fabrication of a plurality of wafer level electronic component packages in accordance with one embodiment of the present invention. Referring now to FIG. 1A , assembly 100 A includes a rigid support strip 102 , e.g., an aluminum, copper or stainless steel plate. Support strip 102 includes fiducials 104 on an upper, e.g., first, surface 102 U of support strip 102 . Fiducials 104 are used for alignment and mounting of electronic components 106 , e.g., integrated circuit chips, as discussed further below.

A dielectric strip 108 is mounted to support strip 102 . Electronic components 106 are mounted to dielectric strip 108 with adhesives 110 , e.g., liquid adhesives or double-sided sticky tapes, although other adhesives are used in other embodiments. To illustrate, a first electronic component 106 A of the plurality of electronic components 106 is mounted to dielectric strip 108 with a first adhesive 110 A of the plurality of adhesives 110 . Dielectric strip 108 , sometimes called a first dielectric strip, and adhesives 110 are electrical insulators, i.e., dielectrics.

More particularly, front, e.g., first, surfaces 106 F of electronic components 106 are mounted to an upper, e.g., first, surface 108 U of dielectric strip 108 with adhesives 110 . A lower, e.g., second, surface 108 L of dielectric strip 108 is mounted to upper surface 102 U of support strip 102 . For example, dielectric strip 108 is tacky, sometimes called sticky, and is simply pressed against support strip 102 to mount dielectric strip 108 to support strip 102 .

In one embodiment, adhesives 110 are applied to front surfaces 106 F of electronic components 106 while electronic components 106 are still in wafer form, i.e., before they are singulated.

In one embodiment, dielectric strip 108 is transparent such that fiducials 104 are visible through dielectric strip 108 . Electronic components 106 are aligned to fiducials 104 and mounted to dielectric strip 108 with adhesives 110 , e.g., using an optical alignment system. Adhesives 110 are cured, if necessary.

In one embodiment, electronic components 106 are mounted in a single row on dielectric strip 108 . However, in other embodiments, electronic components 106 are mounted in an array on dielectric strip 108 . Illustratively, electronic components 106 are mounted in a 2×2, 3×3, . . . , or n×m array. In yet another embodiment, only a single electronic component 106 is mounted to dielectric strip 108 , i.e., the wafer level electronic component package is fabricated as an individual unit instead of as one of a plurality of units fabricated simultaneously.

Formed on front surface 106 F of electronic components 106 are bond pads 112 , e.g., formed of aluminum. Bond pads 112 are connected to the internal circuitry of electronic components 106 .

In one embodiment, bond pads 112 are distributed in an array on front surface 106 F. In another embodiment, bond pads 112 are formed on front surface 106 F directly adjacent sides S of electronic components 106 in a typical wirebond configuration pattern.

FIG. 1B is a cross-sectional view of an assembly 100 B during the fabrication of a plurality of wafer level electronic component packages in accordance with another embodiment of the present invention. Assembly 100 B of FIG. 1B is similar to assembly 100 A of FIG. 1A and only the significant differences are discussed below.

Referring now to FIGS. 1A and 1B together, instead of mounting electronic components 106 to dielectric strip 108 using individual adhesives 110 as illustrated in FIG. 1A , an adhesive strip 120 ( FIG. 1B ) is used to mount electronic components 106 .

Adhesive strip 120 is an electrical insulator. Illustratively, adhesive strip 120 is a liquid adhesive, for example, applied by spin coating. As another example, adhesive strip 120 is a double-sided sticky tape although other adhesives are used in other embodiments.

More particularly, a lower, e.g., first, surface 120 L of adhesive strip 120 is mounted to upper surface 108 U of dielectric strip 108 . Front surfaces 106 F of electronic components 106 are mounted to an upper, e.g., second, surface 120 U of adhesive strip 120 . Although use of adhesive strip 120 is illustrated in the figures that follow and discussed below for purposes of simplicity, it is to be understood that adhesives 110 ( FIG. 1A ) are used instead of adhesive strip 120 in an alternative embodiment.

FIG. 2 is a cross-sectional view of assembly 100 B of FIG. 1B at a further stage during the fabrication of a plurality of wafer level electronic component packages in accordance with one embodiment of the present invention. Referring now to FIG. 2 , heat sinks 214 , e.g., copper slugs, are mounted to rear, e.g., second, surfaces 106 R of electronic components 106 . During use, heat sinks 214 enhance heat dissipation from electronic components 106 to the ambient environment.

To illustrate, a first heat sink 214 A of the plurality of heat sinks 214 is mounted to rear surface 106 R of electronic component 106 A.

In one embodiment, legs 216 of heat sinks 214 adhere to adhesive strip 120 to hold heat sinks 214 in place. In accordance with one embodiment, a thermal pad or grease is used between heat sinks 214 and rear surfaces 106 R of electronic components 106 to enhance heat transfer from electronic components 106 to heat sinks 214 .

In another embodiment, adhesives 218 , e.g., thermal adhesives having a relatively high heat transfer coefficient, mount heat sinks 214 to rear surface 106 R of electronic components 106 . To illustrate, heat sink 214 A is mounted to rear surface 106 R of electronic component 106 A with a first adhesive 218 A of the plurality of adhesives 218 .

Although heat sinks 214 are not illustrated in the figures which follow or discussed further below for purposes of simplicity, it is to be understood that the assembly is fabricated to include heat sinks 214 in an alternative embodiment.

FIG. 3 is a cross-sectional view of assembly 100 B of FIG. 1B at a further stage during the fabrication of a plurality of wafer level electronic component packages in accordance with one embodiment of the present invention. Referring now to FIG. 3 , electronic components 106 are encapsulated, sometimes called overmolded, in an encapsulant 320 . Encapsulant 320 protects electronic components 106 from the ambient environment.

Illustratively, a liquid encapsulant is applied and cured to form encapsulant 320 . In another embodiment, a plastic encapsulant is applied, e.g., using a transfer or injection mold process, to form encapsulant 320 .

FIG. 4 is a cross-sectional view of assembly 100 B of FIG. 3 at a further stage during the fabrication of a plurality of wafer level electronic component packages in accordance with one embodiment of the present invention. Referring now to FIGS. 3 and 4 together, support strip 102 is removed from dielectric strip 108 . In one embodiment, upper surface 102 U of support strip 102 is pretreated, e.g., a release agent is applied, to facilitate easy removal of support strip 102 . In one embodiment, support strip 102 is reusable and thus reused to fabricate another assembly 100 B as illustrated in FIG. 1B after removal from dielectric strip 108 thus minimizing the cost of fabricating assembly 100 B.

Once support strip 102 is removed, encapsulant 320 provides rigidity and support for assembly 100 B. Further, removal of support strip 102 exposes lower surface 108 L of dielectric strip 108 for further processing as discussed further below.

FIG. 5 is a cross-sectional view of assembly 100 B of FIG. 4 at a further stage during the fabrication of a plurality of wafer level electronic component packages in accordance with one embodiment of the present invention. Referring now to FIG. 5 , a plurality of via apertures 522 are formed using a laser, i.e., using laser ablation. Via apertures 522 are sometimes called first via apertures.

Via apertures 522 extend through dielectric strip 108 and through adhesive strip 120 to bond pads 112 of electronic components 106 . In one embodiment, via apertures 522 are cylindrical in shape. Bond pads 112 are exposed through via apertures 522 .

In one embodiment, the laser intensity is set to be sufficient to remove dielectric strip 108 and adhesive strip 120 . However, the laser intensity is set to be insufficient to remove bond pads 112 . Accordingly, pulsing of the laser forms a single via aperture 522 extending through dielectric strip 108 and through adhesive strip 120 to a bond pad 112 of electronic components 106 . The laser is then stepped to the next location to form the next via aperture 522 .

To illustrate, electronic component 106 A includes bond pads 112 A, 112 B, and 112 C on front surface 106 F of electronic component 106 A. Via apertures 522 A, 522 B, 522 C of the plurality of via apertures 522 extend through dielectric strip 108 and through adhesive strip 120 to bond pads 112 A, 112 B, 112 C, respectively.

To further illustrate, initially, the laser is pulsed to form via aperture 522 A. The laser is then stepped and pulsed again to form via aperture 522 B. The laser is then stepped and pulsed again to form via aperture 522 C. The laser is stepped and pulsed repeatedly until all of via apertures 522 are formed. However, in another embodiment, a plurality of lasers are simultaneous pulsed to form some or all of via apertures 522 simultaneously. In yet other embodiments, via apertures 522 are formed using selective etching, mechanical drilling, or other techniques.

FIG. 6 is a cross-sectional view of assembly 100 B of FIG. 5 at a further stage during the fabrication of a plurality of wafer level electronic component packages in accordance with one embodiment of the present invention. Referring now to FIGS. 5 and 6 together, via apertures 522 are filled with an electrically conductive material, e.g., a metal or metal containing material, an electrically conductive adhesive such as a silver filled adhesive or polymer, or solder paste, to form electrically conductive vias 624 . Vias 624 are sometimes called first vias.

In one embodiment, copper or a copper containing material is plated in via apertures 522 to form vias 624 . In another embodiment, via apertures 522 are filled with an electrically conductive adhesive, which is then cured if necessary, to form vias 624 . In yet another embodiment, via apertures 522 are filled with a solder paste. Assembly 100 B is then heated to reflow the solder paste to form vias 624 .

After formation of vias 624 , any excess electrically conductive material formed on lower surface 108 L of dielectric strip 108 is removed. Illustratively, an etch or physical grinding process is used.

In one embodiment, an over-etch process is used to slightly over-etch vias 624 . Thus, vias 624 remain recessed within via apertures 522 . This ensures that shorting between vias 624 from excess electrically conductive material is avoided.

Vias 624 are electrically connected to corresponding bond pads 112 . To illustrate, vias 624 A, 624 B, 624 C of the plurality of vias 624 are electrically connected to bond pads 112 A, 112 B, 112 C, respectively. Vias 624 extend from bond pads 112 , through adhesive strip 120 and through dielectric strip 108 to be adjacent or slightly recessed from (above in the view of FIG. 6 ) lower surface 108 L of dielectric strip 108 .

Bond pads 112 are directly connected to corresponding vias 624 . Stated another way, bond pads 112 are electrically connected to corresponding vias 624 without the use of a solder, e.g., without the use of flip chip bumps, and without the need to form a solder wetting layer, e.g., a nickel/gold layer, on bond pads 112 . This maximizes the reliability of the electrical connection between vias 624 and bond pads 112 , while at the same time minimizes impedance.

Further, since dielectric strip 108 is directly attached to electronic components 106 by adhesive strip 120 and bond pads 112 are directly connected to corresponding vias 624 , the use of an underfill material is obviated. This simplifies manufacturing, enhances reliability, and thus reduces cost.

After formation of vias 624 , assembly 100 B is inspected, e.g., optically using an automatic inspection system, to insure that all via apertures 522 are properly filled with electrically conductive material, i.e., to inspect the integrity of vias 624 . In one embodiment, any defective or unformed vias 624 detected during the inspection are corrected, e.g., by etch removal of vias 624 , reapplication of the electrically conductive material to reform vias 624 , e.g., re-plating, and removal of any excess electrically conductive material on lower surface 108 L of dielectric strip 108 .

In this manner, the wafer level electronic component packages are fabricated with a maximum yield, e.g., essentially a 100 percent yield. This further minimizes the fabrication cost of the wafer level electronic component packages.

FIG. 7 is a cross-sectional view of assembly 100 B of FIG. 6 at a further stage during the fabrication of a plurality of wafer level electronic component packages in accordance with one embodiment of the present invention. Referring now to FIG. 7 , a second dielectric strip 708 is mounted to dielectric strip 108 . More particularly, an upper, e.g., first, surface 708 U of dielectric strip 708 is mounted to lower surface 108 L of dielectric strip 108 .

For example, dielectric strip 708 is mounted to dielectric strip 108 using a tack cure. More particularly, dielectric strip 708 is pressed on to dielectric strip 108 . Assembly 100 B is heated to fuse together and bond dielectric strip 708 to dielectric strip 108 .

Illustratively, dielectric strip 108 and dielectric strip 708 are polytetrafluoroethylene (PTFE), liquid crystal polymer (LCP) or a non-woven arimid although other low-K dielectric materials are used in other embodiments.

A plurality of via apertures 722 and trace channels 726 are formed using a laser, i.e., using laser ablation. Via apertures 722 and trace channels 726 extend through dielectric strip 708 and to vias 624 . Via apertures 722 are sometimes called second via apertures.

In one embodiment, via apertures 722 are cylindrical in shape and extend vertically, i.e., in a first direction perpendicular to front surface 106 F of electronic components 106 , through dielectric strip 708 to vias 624 . Trace channels 726 are trenches extending horizontally, i.e., in a second direction perpendicular to the first direction and parallel to front surface 106 F of electronic components 106 , from vias 624 .

Vias 624 are exposed through via apertures 722 and trace channels 726 . To illustrate, a first via aperture 722 A of the plurality of via apertures 722 extends through dielectric strip 708 to via 624 A.

To further-illustrate, a first trace channel 726 A of the plurality of trace channels 726 extends through dielectric strip 708 to via 624 B. More particularly, via 624 B is exposed at a first end 728 of trace channel 726 A. Trace channel 726 A extends horizontally outwards from a center C of electronic component 106 A and outwards from via 624 B to a second end 730 of trace channel 726 A in a fan-out configuration.

To further illustrate, a second trace channel 726 B of the plurality of trace channels 726 extends through dielectric strip 708 to via 624 C. More particularly, via 624 C is exposed at a first end 728 of trace channel 726 B. Trace channel 726 B extends horizontally inwards toward center C from via 624 C to a second end 730 of trace channel 726 B in a fan-in configuration.

In one embodiment, a laser is stepped and pulsed repeatedly to form via apertures 722 and trace channels 726 . However, in another embodiment, a plurality of lasers are simultaneous pulsed to form some or all of via apertures 722 and trace channels 726 simultaneously. During formation of trace channels 726 , the laser is moved during pulsing to form the horizontal trenches of trace channels 726 .

By controlling the laser intensity and pulse time, via apertures 722 and trace channels 726 are all formed to have the same depth, this depth being equal to the thickness of dielectric strip 708 . This simplifies and enhances reliability of filling, e.g., plating, of via apertures 722 and trace channels 726 with an electrically conductive material as discussed below.

FIG. 8 is a cross-sectional view of assembly 100 B of FIG. 7 at a further stage during the fabrication of a plurality of wafer level electronic component packages in accordance with one embodiment of the present invention. Referring now to FIGS. 7 and 8 together, via apertures 722 and trace channels 726 are filled with an electrically conductive material, e.g., a metal or metal containing material, an electrically conductive adhesive, or solder paste, to form electrically conductive vias 824 and electrically conductive traces 832 , respectively. Vias 824 are sometimes called second vias.

In one embodiment, copper or a copper containing material is plated in via apertures 722 and trace channels 726 to form vias 824 and traces 832 , respectively. In another embodiment, via apertures 722 and trace channels 726 are filled with an electrically conductive adhesive, which is then cured if necessary, to form vias 824 and traces 832 , respectively. In yet another embodiment, via apertures 722 and trace channels 726 are filled with a solder paste. Assembly 100 B is then heated to reflow the solder paste to form vias 824 and traces 832 , respectively.

Vias 824 form vertical electrical connectors, i.e., form electrical connectors extending vertically. Traces 832 form horizontal electrical connectors, i.e., form electrical connectors extending horizontally.

After formation of vias 824 and traces 832 , any excess electrically conductive material formed on a lower, e.g., second, surface 708 L of dielectric strip 708 is removed. Illustratively, an etch or physical grinding process is used. In one embodiment, an over-etch process is used to slightly over-etch vias 824 and traces 832 . This ensures that shorting between vias 824 and/or traces 832 from excess electrically conductive material is avoided.

Vias 824 and traces 832 are electrically connected to corresponding vias 624 . To illustrate, a first via 824 A of the plurality of vias 824 is electrically connected to via 624 A. Vias 824 extend from vias 624 , through dielectric strip 708 to be adjacent or recessed from lower surface 708 L of dielectric strip 708 .

To further illustrate, a first trace 832 A of the plurality of traces 832 is electrically connected to via 624 B. More particularly, a first end 834 of trace 832 A is electrically connected to via 624 B. Trace 832 A extends horizontally outwards from a center C of electronic component 106 A and outwards from via 624 B to a second end 836 of trace 832 A in a fan-out configuration.

To further illustrate, a second trace 832 B of the plurality of traces 832 is electrically connected to via 624 C. More particularly, a first end 834 of trace 832 B is electrically connected to via 624 C. Trace 832 B extends horizontally inwards toward center C from via 624 C to a second end 836 of trace 832 B in a fan-in configuration.

Although a fan-out trace and a fan-in trace, i.e., traces 832 A, 832 B, respectively, are illustrated and discussed, in other embodiments, only fan-in traces or fan-out traces are formed.

After formation of vias 824 and traces 832 , assembly 100 B is inspected to insure that all via apertures 722 and trace channels 726 are properly filled with electrically conductive material, i.e., to inspect the integrity of vias 824 and traces 832 .

In one embodiment, any defective or unformed vias 824 and traces 832 detected during the inspection are corrected, e.g., by etch removal of vias 824 and traces 832 , reapplication of the electrically conductive material to reform vias 824 and traces 832 , and removal of any excess electrically conductive material on lower surface 708 L of dielectric strip 708 . In this manner, the wafer level electronic component packages are fabricated with a maximum yield.

FIG. 9 is a cross-sectional view of assembly 100 B of FIG. 8 at a further stage during the fabrication of a plurality of wafer level electronic component packages in accordance with one embodiment of the present invention. Referring now to FIG. 9 , a third dielectric strip 908 is mounted to dielectric strip 708 . More particularly, an upper, e.g., first, surface 908 U of dielectric strip 908 is mounted to lower surface 708 L of dielectric strip 708 . Dielectric strip 908 is similar to dielectric strip 708 and mounted in a manner similar to that discussed above with regards to mounting of dielectric strip 708 to dielectric strip 108 .

A plurality of via apertures 922 are formed using a laser, i.e., using laser ablation. Via apertures 922 extend through dielectric strip 908 to vias 824 and traces 832 . In one embodiment, via apertures 922 are cylindrical in shape. Via apertures 922 are sometimes called third via apertures.

Vias 824 and second ends 836 of traces 832 are exposed through via apertures 922 . To illustrate, via apertures 922 A, 922 B, 922 C of the plurality of via apertures 922 extend through dielectric strip 908 to via 824 A and second ends 836 of traces 832 A, 832 B, respectively.

Via apertures 922 are formed in a manner similar to via apertures 522 of FIG. 5 so formation of via apertures 922 is not discussed in detail to avoid detracting from the principals of the invention.

Via apertures 922 are filled with an electrically conductive material, e.g., a metal or metal containing material, an electrically conductive adhesive, or solder paste, to form electrically conductive vias 924 . Via apertures 922 are filled to form vias 924 in a manner similar to that discussed with regards to vias 624 of FIG. 6 so formation of vias 924 is not discussed in detail to avoid detracting from the principals of the invention. Vias 924 are sometimes called third vias.

After formation of vias 924 , any excess electrically conductive material formed on a lower, e.g., second, surface 908 U of dielectric strip 908 is removed. Illustratively, an etch or physical grinding process is used. In one embodiment, an over-etch process is used to slightly over-etch vias 924 . Thus, vias 924 remain recessed within via apertures 922 . This ensures that shorting between vias 924 from excess electrically conductive material is avoided.

Vias 924 are electrically connected to corresponding vias 824 and second ends 836 of traces 832 . To illustrate, vias 924 A, 924 B, 924 C of the plurality of vias 924 are electrically connected to via 824 A and second ends 836 of traces 832 A, 832 B, respectively. Vias 924 extend from vias 824 and second ends 836 of traces 832 through dielectric strip 908 to be adjacent or slightly recessed from lower surface 908 L of dielectric strip 908 .

In one embodiment, vias 924 are formed to have a larger diameter than the width of traces 832 and/or the diameter of vias 824 . By forming vias 924 with the appropriate diameter, tolerance in the positioning of vias 924 is accommodated. Stated another way, by forming vias 924 with a sufficiently large diameter, electrical contact between vias 924 and vias 824 /traces 832 is assured.

After formation of vias 924 , assembly 100 B is inspected to insure that all via apertures 922 are properly filled with electrically conductive material, i.e., to inspect the integrity of vias 924 .

In one embodiment, any defective or unformed vias 924 detected during the inspection are corrected, e.g., by etch removal of vias 924 , reapplication of the electrically conductive material to reform vias 924 , and removal of any excess electrically conductive material on lower surface 908 L of dielectric strip 908 . In this manner, the wafer level electronic component packages are fabricated with a maximum yield.

FIG. 10 is a cross-sectional view of assembly 100 B of FIG. 9 at a further stage during the fabrication of a plurality of wafer level electronic component packages in accordance with one embodiment of the present invention. Referring now to FIG. 10 , a fourth dielectric strip 1008 is mounted to dielectric strip 908 . More particularly, an upper, e.g., first, surface 1008 U of dielectric strip 1008 is mounted to lower surface 908 L of dielectric strip 908 . Dielectric strip 1008 is similar to dielectric strip 708 and mounted in a manner similar to that discussed above with regards to mounting of dielectric strip 708 to dielectric strip 108 .

A plurality of land apertures 1040 are formed using a laser, i.e., using laser ablation. Land apertures 1040 extend through dielectric strip 1008 to vias 924 . In one embodiment, land apertures 1040 are cylindrical in shape but can be patterned in a variety of shapes depending upon the particular interconnection structure used, e.g., interconnection balls or lands.

Vias 924 are exposed through land apertures 1040 . To illustrate, land apertures 1040 A, 1040 B, 1040 C of the plurality of land apertures 1040 extend through dielectric strip 1008 to vias 924 A, 924 B, 924 C, respectively.

Land apertures 1040 are formed in a manner similar to via apertures 522 of FIG. 5 so formation of land apertures 1040 is not discussed in detail to avoid detracting from the principals of the invention.

Land apertures 1040 are filled with an electrically conductive material, e.g., a metal or metal containing material, an electrically conductive adhesive, or solder paste, to form electrically conductive lands 1044 . Land apertures 1040 are filled to form lands 1044 in a manner similar to that discussed with regards to vias 624 of FIG. 6 so formation of lands 1044 is not discussed in detail to avoid detracting from the principals of the invention. After formation of lands 1044 , any excess electrically conductive material formed on a lower, e.g., second, surface 1008 L of dielectric strip 1008 is removed. Illustratively, an etch or physical grinding process is used.

In one embodiment, an over-etch process is used to slightly over-etch lands 1044 . Thus, lands 1044 remain recessed within land apertures 1040 . This ensures that shorting between lands 1044 from excess electrically conductive material is avoided.

Lands 1044 are electrically connected to corresponding vias 924 . To illustrate, lands 1044 A, 1044 B, 1044 C of the plurality of lands 1044 are electrically connected to vias 924 A, 924 B, 924 C, respectively. Lands 1044 extend from vias 924 through dielectric strip 1008 to be adjacent or slightly recessed from lower surface 1008 L of dielectric strip 1008 .

After formation of lands 1044 , assembly 100 B is inspected to insure that all land apertures 1040 are properly filled with electrically conductive material, i.e., to inspect the integrity of lands 1044 . In one embodiment, any defective or unformed lands 1044 detected during the inspection are corrected, e.g., by etch removal of lands 1044 , reapplication of the electrically conductive material to reform lands 1044 , and removal of any excess electrically conductive material on lower surface 1008 L of dielectric strip 1008 . In this manner, the wafer level electronic component packages are fabricated with a maximum yield.

After formation of lands 1044 , in one embodiment, a solder on paste (SOP) is applied to lands 1044 . This solder on paste is reflowed, i.e., heated to a melt and cooled to resolidify, to form solder lands, which are represented as item 1046 in FIG. 10 in accordance with this embodiment.

In accordance with this embodiment, the resulting wafer level electronic component package is a land grid array package. The solder lands are used to electrically connect the wafer level electronic component package to the larger substrate, e.g., a mother or daughter board, for example, using a high lead solder such as a 90/10 lead/tin solder.

In another embodiment, a ball grid array package is formed. More particular, after formation of lands 1044 , an organic solderability protectant (OSP), sometimes called an organic solderability preservative, is applied to lands 1044 . The organic solderability protectant, which is represented as item 1046 in FIG. 10 in accordance with this embodiment, enhances the solder wet-ability of lands 1044 . For simplicity of discussion, the organic solderability protectant is hereinafter referred to as OSP 1046 . However, in another embodiment, OSP 1046 is not used.

FIG. 11 is a cross-sectional view of assembly 100 B of FIG. 10 at a further stage during the fabrication of a plurality of wafer level electronic component packages 1148 in accordance with one embodiment of the present invention. Referring now to FIG. 11 , electrically conductive interconnection balls 1150 , e.g., eutectic lead/tin solder, are formed on lands 1044 . Interconnection balls 1150 are formed in a conventional manner. During formation of interconnection balls 1150 , OSP 1046 is consumed.

Interconnection balls 1150 are used to electrically connect wafer level electronic component packages 1148 to the larger substrate, e.g., a mother or daughter board. Assembly 100 B is then singulated, e.g., using a mechanical saw or laser, to form the plurality of wafer level electronic component packages 1148 .

Each interconnection ball 1150 is electrically connected to a corresponding bond pad 112 as discussed above. In this manner, the pattern of bond pads 112 is redistributed to the pattern of interconnection balls 1150 .

For example, bond pads 112 are formed on front surface 106 F directly adjacent sides S of electronic components 106 in a typical wirebond configuration pattern. However, interconnection balls 1150 are distributed in an array pattern. Thus, the wirebond configuration pattern of bond pads 112 is redistributed to an array pattern of interconnection balls 1150 . Although an array pattern of interconnection balls 1150 is discussed above, interconnection balls 1150 are distributed in any one of a number of desired patterns in other embodiments.

Further, interconnection balls 1150 are connected to bond pads 112 using a minimum path length. To illustrate, bond pad 112 A is coupled to a first interconnection ball 1150 A of the plurality of interconnection balls 1150 by vias 624 A, 824 A, 924 A, land 1044 A, which are directly aligned with one another. By using a minimum path length, heat transfer between bond pads 112 and more generally between electronic components 106 and interconnection balls 1150 is maximized thus improving the thermal performance of wafer level electronic component packages 1148 . For similar reasons, impedance between bond pads 112 and interconnection balls 1150 is minimized.

As set forth above, (1) a dielectric strip is applied; (2) the dielectric strip is laser patterned to form via apertures and/or trace channels; (3) the via apertures and/or trace channels are filled with electrically conductive material to form vias and/or traces; (4) excess electrically conductive material is removed from the lower surface of the dielectric strip; and (5) the formed vias and/or traces are inspected and corrected, if necessary. This process is repeated any number of desired times until the desired redistribution is achieved.

Further, since the via apertures 522 , 722 , 922 and/or trace channels 726 are formed with a laser in one embodiment, any changes in the design layout of the via apertures 522 , 722 , 922 and/or trace channels 726 are relatively simple to execute. More particularly, these design layout changes are made in the computer software, e.g., the CAD software, which drives the laser. Accordingly, the design layout changes are made with some relatively simple programming and executed immediately.

Referring still to FIG. 11 , although four dielectric strips 108 , 708 , 908 , 1008 are illustrated and discussed above, more or less than four dielectric strips are used in other embodiments. Generally, at least one dielectric strip, e.g., dielectric strip 108 , is used.

Further, although vias 624 , 824 , 924 , traces 832 , and lands 1044 are discussed above as being formed in various dielectric strips 108 , 708 , 908 , and 1008 for purposes of discussion, in light of this disclosure, those of skill in the art will understand that vias, traces, lands and/or combinations thereof can be formed in any single dielectric strip 108 , 708 , 908 , or 1008 .

Further, although vias 624 , 824 , 924 , traces 832 , and lands 1044 are discussed as distinct types of structures for purposes of discussion, in light of this disclosure, those of skill in the art will understand that vias 624 , 824 , 924 , traces 832 , and lands 1044 can be similar in structure. For example, a via or trace can form a land.

Still further, via apertures 522 , 722 , 922 , trace channels 726 and land apertures 1040 are filled immediately after formation, i.e., before application of the next dielectric strip, with an electrically conductive material to form the vias 624 , 824 , 924 , traces 832 and lands 1044 , respectively, in the discussion above. However, in an alternative embodiment, via apertures 522 , 722 , 922 , trace channels 726 and land apertures 1040 are formed in some or all of dielectric strips 108 , 708 , 908 , 1008 . After formation, via apertures 522 , 722 , 922 , trace channels 726 and land apertures 1040 are filled at the same time, e.g., in a single plating operation, with an electrically conductive material to form vias 624 , 824 , 924 , traces 832 and lands 1044 , respectively.

FIG. 12 is a cross-sectional view of an assembly 1200 during the fabrication of a plurality of wafer level electronic component packages in accordance with one embodiment of the present invention. Referring now to FIG. 12 , assembly 1200 includes an electronic component substrate 1252 such as a silicon wafer. Electronic component substrate 1252 includes a plurality of electronic components 106 - 1 integrally connected together. Electronic components 106 - 1 include bond pads 112 on front surfaces 106 F of electronic components 106 - 1 , and more generally on a lower, e.g., first, surface 1252 L of electronic component substrate 1252 .

Electronic components 106 - 1 are integrally connected together in an array, e.g., a 2×2, 3×3 . . . or n×m array. Each of electronic components 106 - 1 is delineated by a singulation street 1254 , which is located between adjacent electronic components 106 - 1 . For example, a first singulation street 1254 A of the plurality of singulation streets 1254 delineates a first electronic component 106 - 1 A from a second electronic component 106 - 1 B of the plurality of electronic components 106 - 1 . The other electronic components 106 - 1 are similarly delineated from adjacent electronic components 106 - 1 by corresponding singulation streets 1254 .

Upper surface 108 U of dielectric strip 108 is mounted to front surfaces 106 F of electronic components 106 - 1 , and more generally to lower surface 1252 L of electronic component substrate 1252 with adhesive strip 120 . Electronic component substrate 1252 provides rigidity and support for assembly 1200 .

FIG. 13 is a cross-sectional view of assembly 1200 of FIG. 12 at a further stage during the fabrication of a plurality of wafer level electronic component packages in accordance with one embodiment of the present invention. Referring now to FIG. 13 , vias 624 , 824 , 924 , traces 832 , and lands 1044 are formed in dielectric strips 108 , 708 , 908 , and 1008 as discussed above in reference to FIGS. 5-11 , the discussion of which is incorporated herein by reference in its entirety.

In the embodiment illustrated in FIG. 13 , interconnection balls 1150 are formed on lands 1044 to form a ball grid array (BGA) package. Each interconnection ball 1150 is coupled to a corresponding bond pad 112 . However, it is to be understood that a land grid array (LGA) package can also be fabricated.

Processing of assembly 1200 is a true wafer scale process. After formation of vias 624 , 824 , 924 , traces 832 , lands 1044 in dielectric strips 108 , 708 , 908 , 1008 , assembly 1200 is singulated along singulation streets 1254 ( FIG. 12 ) resulting in the fabrication of wafer level electronic component packages 1348 . Singulation is performed before or after fabrication of interconnection balls 1150 .

In one embodiment of the invention, trace channels 726 ( FIGS. 7 and 8 ) are optimally formed in a shape suited to holding a metal layer, such as a copper metal layer, in place. In one embodiment of the invention, trace channels 726 are formed to be Gaussian in shape. In one embodiment of the invention, trace channels 726 are formed to be v-shaped. In one embodiment of the invention trace channels 726 are formed to be a generally trapezoidal shape.

In one embodiment of the invention, trace channels 726 are also formed such that the inner surface of the trace channel is textured or rough. This provides even better bonding between the metal layer and the surface of the trace channel 726 . In one embodiment of the invention, the surface of the metal layer to be applied is also textured, or matted to provide even better bonding between the metal layer and the surface of the trace 726 .

One embodiment of the invention is an embedded electronic component package. The method for creating the embedded electronic component package of this embodiment includes coupling a substrate to a first dielectric layer, strip, or panel, and forming first electrically conductive vias and traces in the first dielectric layer. A cavity is then formed in the first dielectric layer and an electronic component is attached in the cavity, with a first surface of the electronic component, including the bond pads, being either level with, partially below, or partially above the first surface of the first dielectric layer. A second dielectric layer, strip, or panel, is then applied to the first dielectric layer, thereby encasing the electronic component in dielectric. Second via apertures are then formed through the second dielectric layer to expose selected bond pads and/or selected first electrically conductive vias and traces. The second via apertures are then filled with an electrically conductive material to form second electrically conductive vias electrically coupled to selected bond pads and selected first electrically conductive vias and traces.

In particular, FIG. 14A is a cross-sectional side view of a substrate 1402 , such as a motherboard. In one embodiment of the invention, a conductive layer 1404 of copper traces and pads, or other conductive material, is formed on substrate 1402 and includes various electrical contacts and traces (not shown).

FIG. 14B is a cross-sectional side view of an assembly 1400 B including substrate 1402 with a first dielectric layer, strip, or panel, 1408 , collectively referred to herein as first dielectric layer 1408 . As shown in FIG. 14B , a first dielectric layer second surface 1405 is applied to substrate first surface 1406 . In one embodiment of the invention, first dielectric layer 1408 is applied directly to substrate first surface 1406 . In other embodiments of the invention, first dielectric layer 1408 is applied to substrate first surface 1406 with adhesives (not shown) such as liquid adhesives or double-sided sticky tapes, although other adhesives are used in other embodiments. In one embodiment of the invention, first dielectric layer 1408 is polytetrafluoroethylene (PTFE), liquid crystal polymer (LCP) or a non-woven arimid although other low-K dielectric materials are used in other embodiments. In other embodiments of the invention dielectric layer 1408 is applied by pressing, screen coating or curtain coating.

FIG. 14C is a cross-sectional view of an assembly 1400 C in accordance with another embodiment of the present invention. Assembly 1400 C of FIG. 14C is similar to assembly 1400 B of FIG. 14B and only the significant differences are discussed below. Referring now to FIG. 14C , a plurality of first via apertures 1422 and first trace trenches 1423 are formed in a first dielectric layer first surface 1407 of first dielectric layer 1408 by methods similar to those discussed above. In one embodiment of the invention, first via apertures 1422 and first trace trenches 1423 are formed using a laser, i.e., using laser ablation.

FIG. 14D is a cross-sectional view of assembly 1400 D in accordance with one embodiment of the present invention. Assembly 1400 D of FIG. 14D is similar to assembly 1400 C of FIG. 14C and only the significant differences are discussed below. Referring now to FIG. 14D first dielectric layer first surface 1407 is covered with a first conductive layer 1409 . In one embodiment of the invention, first conductive layer 1409 is metal or metal containing material, an electrically conductive adhesive such as a silver filled adhesive or polymer, or solder paste. First conductive layer 1409 is applied in order to fill first via apertures 1422 and first trace trenches 1423 with the electrically conductive material. In one embodiment, copper or a copper containing material is plated in first via apertures 1422 and first trace trenches 1423 . In another embodiment, first via apertures 1422 and first trace trenches 1423 are filled with an electrically conductive adhesive, which is then cured if necessary. In yet another embodiment, first via apertures 1422 and first trace trenches 1423 are filled with a solder paste and assembly 1400 D is then heated to reflow the solder paste.

FIG. 14E is a cross-sectional view of assembly 1400 E in accordance with one embodiment of the present invention. Assembly 1400 E of FIG. 14E is similar to assembly 1400 D of FIG. 14D and only the significant differences are discussed below. Referring now to FIG. 14E , any excess material of first conductive layer 1409 is removed and made at least level/planar with first dielectric layer first surface 1407 to thereby form first electrically conductive vias 1424 and first traces 1425 from first via apertures 1422 and first trace trenches 1423 . In one embodiment, an over-etch process is used to slightly over-etch first electrically conductive vias 1424 and first traces 1425 . This ensures that shorting between vias from excess electrically conductive material is avoided.

FIG. 14F is a cross-sectional view of assembly 1400 F in accordance with one embodiment of the present invention. Assembly 1400 F of FIG. 14F is similar to assembly 1400 E of FIG. 14E and only the significant differences are discussed below. Referring now to FIG. 14F , a cavity 1430 is formed in first dielectric layer first surface 1407 . In one embodiment of the invention, cavity 1430 is formed using a laser, i.e., using laser ablation. As seen in FIG. 14F , cavity 1430 includes a cavity bottom surface 1433 . In one embodiment of the invention, cavity bottom surface 1433 is a portion of first dielectric layer 1408 . In another embodiment of the invention, cavity bottom surface 1433 is simply first surface 1406 of substrate 1402 . In one embodiment of the invention, cavity bottom surface 1433 lies at a depth 1435 of 3 mils (75 microns) below first dielectric layer first surface 1407 . In other embodiments, bottom surface 1433 lies at a depth 1435 or greater or less than 3 mils (75 microns) depending on the wafer thickness.

FIG. 14G shows a angled perspective view of structure 1400 F of FIG. 14F including: substrate 1402 ; substrate conductive layer 1404 ; first dielectric layer 1408 ; and cavity 1430 formed in first dielectric layer first surface 1407 and having cavity bottom surface 1433 .

FIG. 14H is a cross-sectional view of assembly 1400 H in accordance with one embodiment of the present invention. Assembly 1400 H of FIG. 14H is similar to assembly 1400 F of FIG. 14F and only the significant differences are discussed below. Referring now to FIG. 14H , an electronic component 1440 is positioned in cavity 1430 with an electronic component second surface 1443 mounted/attached to cavity bottom surface 1433 . In one embodiment of the invention, electronic component second surface 1443 of electronic component 1440 is mounted to cavity bottom surface 1433 with adhesives (not shown), e.g., liquid adhesives or double-sided sticky tapes, although other adhesives are used in other embodiments. As discussed above, formed on first surface 1441 of electronic component 1440 are bond pads 1445 , e.g., formed of aluminum. Bond pads 1445 are connected to the internal circuitry of electronic component 1440 . In one embodiment, bond pads 1445 are distributed in an array on electronic component first surface 1441 . In another embodiment, bond pads 1445 are formed on electronic component first surface 1441 directly adjacent side S of electronic component 1440 in a typical wirebond configuration pattern. In one embodiment of the invention, cavity 1430 is formed such that electronic component first surface 1441 is level/planar with first dielectric layer first surface 1407 . In one embodiment of the invention, cavity 1430 is formed such that electronic component first surface is slightly above first dielectric layer first surface 1407 . In one embodiment of the invention, cavity 1430 is formed such that electronic component first surface 1441 is slightly below first dielectric layer first surface 1407 . According to the invention, electronic component 1440 can be an integrated circuit, a passive component, an active component, or any combination thereof.

FIG. 14I shows an angled perspective view of structure 1400 H of FIG. 14H including: substrate 1402 ; substrate conductive layer 1404 ; first dielectric layer 1408 ; cavity 1430 formed in first dielectric layer first surface 1407 ; and electronic component 1440 positioned on cavity bottom surface 1433 (not shown) of cavity 1430 with electronic component first surface and bond pads 1445 uncovered.

FIG. 14J is a cross-sectional view of assembly 1400 J in accordance with one embodiment of the present invention. Assembly 1400 J of FIG. 14J is similar to assembly 1400 H of FIG. 14H and only the significant differences are discussed below. Referring now to FIG. 14J , a second dielectric layer, strip, or panel, 1448 , herein referred to collectively as second dielectric layer 1448 , is applied to first dielectric layer 1408 . More particularly, a second dielectric layer second surface 1447 is mounted to first dielectric layer first surface 1407 . In one embodiment, second dielectric layer second surface 1447 is applied to first dielectric layer first surface 1407 using a tack cure. More particularly, second dielectric layer second surface 1447 is pressed on to first dielectric layer first surface 1407 . In one embodiment, second dielectric layer second surface 1447 is applied to first dielectric layer first surface 1407 by screen coating. In one embodiment, second dielectric layer second surface 1447 is applied to first dielectric layer first surface 1407 by curtain coating. In other embodiments of the invention, any other method of dielectric application is used to apply second dielectric layer 1448 .

In one embodiment of the invention, gap portions 1450 between electronic component 1440 sides S and cavity 1430 walls W are filled in by simply pressing second dielectric layer 1448 into first dielectric layer 1408 to form fill gap portions 1450 . In another embodiment of the invention, gap portions 1450 are filled by a separate dielectric layer(s) (not shown) applied in a laminate fashion. In yet another embodiment of the invention, second dielectric layer 1448 is custom made to include thicker portions designed to fill gap portions 1450 . In yet another embodiment of the invention, second dielectric layer 1448 is applied as a liquid and gap portions 1450 are filled with second dielectric layer 1448 while it is in a liquid state. In this embodiment, second dielectric layer 1448 is then cured. In one embodiment, assembly 1400 J is heated to fuse together and bond first dielectric layer 1408 with second dielectric layer 1448 . In one embodiment of the invention, first dielectric layer 1408 and second dielectric layer 1448 are polytetrafluoroethylene (PTFE), liquid crystal polymer (LCP) or a non-woven arimid although other low-K dielectric materials are used in other embodiments.

FIG. 14K is a cross-sectional view of an assembly 1400 K in accordance with one embodiment of the present invention. Assembly 1400 K of FIG. 14K is similar to assembly 1400 J of FIG. 14J and only the significant differences are discussed below. Referring now to FIG. 14K , a plurality of second via apertures 1460 A, 1460 B, 1460 C, 1460 D and 1460 E are formed using a laser, i.e., using laser ablation. Second via apertures 1460 A, 1460 B, 1460 C, 1460 D and 1460 E extend through second dielectric layer 1448 to selected ones of bond pads 1445 A, 1445 B, 1445 C of electronic component 1440 and selected ones of first electrically conductive vias 1424 and first electrically conductive traces 1425 . In one embodiment, second via apertures 1460 A, 1460 B, 1460 C, 1460 D and 1460 E are cylindrical in shape, however, other shapes are used in other embodiments. Bond pads 1445 A, 1445 B, 1445 C of electronic component 1440 and first electrically conductive vias 1424 and first electrically conductive traces 1425 are exposed through second via apertures 1460 A, 1460 B, 1460 C, 1460 D and 1460 E. In one embodiment, the laser intensity is set to be sufficient to remove second dielectric layer 1448 . However, the laser intensity is set to be insufficient to remove bond pads 1445 A, 1445 B, 1445 C. Accordingly, pulsing of the laser forms a single second via aperture 1460 A, 1460 B, 1460 C, 1460 D or 1460 E extending through second dielectric layer 1448 to one of bond pads 1445 A, 1445 B, or 1445 C of electronic component 1440 . The laser is then stepped to the next location to form the next second via aperture 1460 A, 1460 B, 1460 C, 1460 D or 1460 E. To illustrate, electronic component 1440 includes bond pads 1445 A, 1445 B, 1445 C on first surface of electronic component 1440 . Second via aperture 1460 A, 1460 B, 1460 C of the plurality of second via aperture 1460 A, 1460 B, 1460 C, 1460 D and 1460 E extend through second dielectric layer 1448 to bond pads 1445 A, 1445 B, 1445 C, respectively. In addition, second via aperture 1460 E and 1460 D of the plurality of second via aperture 1460 A, 1460 B, 1460 C, 1460 D and 1460 E extend through second dielectric layer 1448 to first electrically conductive vias 1424 and first electrically conductive traces 1425 , respectively. To further illustrate, initially, the laser is pulsed to form second via aperture 1460 A. The laser is then stepped and pulsed again to form second via aperture 1460 B. The laser is then stepped and pulsed again to form second via aperture 1460 C. The laser is stepped and pulsed repeatedly until all of second via aperture 1460 A, 1460 B, 1460 C, 1460 D and 1460 E are formed. However, in another embodiment, a plurality of lasers are simultaneous pulsed to form some or all of second via aperture 1460 A, 1460 B, 1460 C, 1460 D and 1460 E simultaneously. In yet other embodiments, second via aperture 1460 A, 1460 B, 1460 C, 1460 D and 1460 E are formed using selective etching, mechanical drilling, or other techniques.

FIG. 14L is a cross-sectional view of an assembly 1400 L in accordance with one embodiment of the present invention. Assembly 1400 L of FIG. 14L is similar to assembly 1400 K of FIG. 14K and only the significant differences are discussed below. Referring now to FIGS. 14K and 14L together, second via apertures 1460 A, 1460 B, 1460 C, 1460 D and 1460 E are filled with an electrically conductive material, e.g., a metal or metal containing material, an electrically conductive adhesive such as a silver filled adhesive or polymer, or solder paste, to form second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E.

In one embodiment, copper or a copper containing material is plated in second via apertures 1460 A, 1460 B, 1460 C, 1460 D and 1460 E to form second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E. In another embodiment, second via apertures 1460 A, 1460 B, 1460 C, 1460 D and 1460 E are filled with an electrically conductive adhesive, which is then cured, if necessary, to form second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E. In yet another embodiment, second via apertures 1460 A, 1460 B, 1460 C, 1460 D and 1460 E are filled with a solder paste. Assembly 1400 L is then heated to reflow the solder paste to form second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E. After formation of second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E, any excess electrically conductive material formed on second dielectric layer first surface 1470 is removed. Illustratively, an etch or physical grinding process is used. In one embodiment, an over-etch process is used to slightly over-etch second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E. Thus, second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E remain recessed within second via apertures 1460 A, 1460 B, 1460 C, 1460 D and 1460 E. This ensures that shorting between second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E from excess electrically conductive material is avoided.

Second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E are electrically connected to corresponding bond pads 1445 A, 1445 B, 1445 C of electronic component 1440 and first electrically conductive vias 1424 and first electrically conductive traces 1425 . To illustrate, second electrically conductive vias 1461 A, 1461 B, 1461 C of the plurality of second electrically conductive vias 1461 A, 1461 B, 1461 C are electrically connected to bond pads 1445 A, 1445 B, 1445 C of electronic component 1440 , respectively. Consequently, second electrically conductive vias 1461 A, 1461 B, 1461 C extend from bond pads 1445 A, 1445 B, 1445 C, through second dielectric layer 1448 , to be adjacent or slightly recessed from second dielectric layer first surface 1470 . Likewise, second electrically conductive vias 1461 D, 1461 E are electrically connected to first electrically conductive vias 1424 and first electrically conductive traces 1425 . Consequently, second electrically conductive vias 1461 D, 1461 E extend from first electrically conductive vias 1424 and first electrically conductive traces 1425 , through second dielectric layer 1448 , to be adjacent or slightly recessed from second dielectric layer first surface 1470 . Stated another way, bond pads 1445 A, 1445 B, 1445 C of electronic component 1440 and first electrically conductive vias 1424 and first electrically conductive traces 1425 are electrically connected to corresponding second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E, and second dielectric first surface 1447 , without the use of a solder, e.g., without the use of flip chip bumps, and without the need to form a solder wetting layer, e.g., a nickel/gold layer, on bond pads 1445 A, 1445 B, 1445 C. This maximizes the reliability of the electrical connection between second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E and bond pads 1445 A, 1445 B, 1445 C of electronic component 1440 and first electrically conductive vias 1424 and first electrically conductive traces 1425 , while at the same time minimizing impedance.

After formation of second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E, assembly 1400 L is inspected, e.g., optically using an automatic inspection system, to insure that all second via apertures 1460 A, 1460 B, 1460 C, 1460 D and 1460 E are properly filled with electrically conductive material, i.e., to inspect the integrity of second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E. In one embodiment, any defective or unformed second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E detected during the inspection are corrected, e.g., by etch removal of second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E, reapplication of the electrically conductive material to reform second electrically conductive vias 1461 A, 1461 B, 1461 C, 1461 D, and 1461 E, e.g., re-plating, and removal of any excess electrically conductive material.

In this manner, the embedded electronic component packages are fabricated with a maximum yield, e.g., essentially a 100 percent yield. This further minimizes the fabrication cost of the wafer level electronic component packages.

One embodiment of the invention is an encased electronic component package. The method for creating the encased electronic component package of this embodiment includes coupling a substrate to a first dielectric layer, strip, or panel, and forming first electrically conductive vias and traces in the first dielectric layer. A first surface of an electronic component, is then attached to a first surface of the dielectric layer, strip, or panel in an attachment region. One or more further dielectric layers, strips, or panels, including die cutouts, are then applied to the first dielectric layer, thereby surrounding the electronic component in dielectric. A top dielectric layer is then applied to the structure to cover, and thereby encase, the electronic component. In one embodiment of the invention, the subsequent dielectric layers encapsulating the electronic component are made of prepreg or a similar material, which can be partially re-flowed and then cured to encase the electronic component in a custom fitting operation. Second via apertures are then formed through encasement to expose selected bond pads and/or selected first electrically conductive vias and traces. The second via apertures are then filled with an electrically conductive material to form second electrically conductive vias electrically coupled to selected bond pads and selected first electrically conductive vias and traces.

In particular, FIG. 15A is a cross-sectional side view of a substrate 1502 , such as a motherboard. In one embodiment of the invention, a conductive layer 1504 of copper traces and pads, or other conductive material, is formed on substrate first surface 1506 and includes various electrical contacts and traces (not shown).

FIG. 15B is a cross-sectional side view of an assembly 1500 B including substrate 1502 with a first dielectric layer, strip, or panel, 1508 , collectively referred to herein as first dielectric layer 1508 . As shown in FIG. 15B , a first dielectric layer second surface 1505 is applied to substrate first surface 1506 . In one embodiment of the invention, first dielectric layer 1508 is applied directly to substrate first surface 1506 . In other embodiments of the invention, first dielectric layer 1508 is applied to substrate first surface 1506 with adhesives (not shown) such as liquid adhesives or double-sided sticky tapes, although other adhesives are used in other embodiments. In one embodiment of the invention, first dielectric layer 1508 is polytetrafluoroethylene (PTFE), liquid crystal polymer (LCP) or a non-woven arimid although other low-K dielectric materials are used in other embodiments. In other embodiments of the invention dielectric layer 1508 is applied by pressing, screen coating or curtain coating.

FIG. 15C is a cross-sectional view of an assembly 1500 C in accordance with another embodiment of the present invention. Assembly 1500 C of FIG. 15C is similar to assembly 1500 B of FIG. 15B and only the significant differences are discussed below. Referring now to FIG. 15C , a plurality of first via apertures 1522 and first trace trenches 1523 are formed in a first dielectric layer first surface 1507 of first dielectric layer 1508 by methods similar to those discussed above. In one embodiment of the invention, first via apertures 1522 and first trace trenches 1523 are formed using a laser, i.e., using laser ablation.

FIG. 15D is a cross-sectional view of assembly 1500 D in accordance with one embodiment of the present invention. Assembly 1500 D of FIG. 15D is similar to assembly 1500 C of FIG. 15C and only the significant differences are discussed below. Referring now to FIG. 15D first dielectric layer first surface 1507 is covered with a first conductive layer 1509 . In one embodiment of the invention, first conductive layer 1509 is metal or metal containing material, an electrically conductive adhesive such as a silver filled adhesive or polymer, or solder paste. First conductive layer 1509 is applied in order to fill first via apertures 1522 and first trace trenches 1523 with the electrically conductive material. In one embodiment, copper or a copper containing material is plated in first via apertures 1522 and first trace trenches 1523 . In another embodiment, first via apertures 1522 and first trace trenches 1523 are filled with an electrically conductive adhesive, which is then cured if necessary. In yet another embodiment, first via apertures 1522 and first trace trenches 1523 are filled with a solder paste and assembly 1500 D is then heated to reflow the solder paste.

FIG. 15E is a cross-sectional view of assembly 1500 E in accordance with one embodiment of the present invention. Assembly 1500 E of FIG. 15E is similar to assembly 1500 D of FIG. 15D and only the significant differences are discussed below. Referring now to FIG. 15E , any excess material of first conductive layer 1509 is removed and made at least level/planar with first dielectric layer first surface 1507 to thereby form first electrically conductive vias 1524 and first traces 1525 from first via apertures 1522 and first trace trenches 1523 . In one embodiment, an over-etch process is used to slightly over-etch first electrically conductive vias 1524 and first traces 1525 . This ensures that shorting between vias from excess electrically conductive material is avoided.

FIG. 15F is a cross-sectional view of assembly 1500 F in accordance with one embodiment of the present invention. Assembly 1500 F of FIG. 15F is similar to assembly 1500 E of FIG. 15E and only the significant differences are discussed below. Referring now to FIG. 15F , a die attachment area 1570 is formed on first dielectric layer first surface 1507 . In one embodiment of the invention, die attachment area 1570 is copper, or other suitable metal, which is screened onto, sprayed onto, or otherwise applied to dielectric layer first surface 1507 . In one embodiment of the invention, die attachment area 1570 also includes a passivation layer and/or an adhesive layer (not shown). In one embodiment of the invention, die attachment area 1570 is marked with one or more fiducials (not shown).

FIG. 15G is a cross-sectional view of assembly 1500 F in accordance with one embodiment of the present invention. Assembly 1500 G of FIG. 15G is similar to assembly 1500 F of FIG. 15F and only the significant differences are discussed below. Referring now to FIG. 15G , an electronic component 1540 is positioned on die attach area 1570 with an electronic component second surface 1543 mounted/attached to die attach area 1570 . In one embodiment of the invention, electronic component second surface 1543 of electronic component 1540 is mounted in die attach area 1570 with adhesives (not shown), e.g., liquid adhesives or double-sided sticky tapes, although other adhesives are used in other embodiments. As discussed above, formed on first surface 1541 of electronic component 1540 are bond pads 1545 , e.g., formed of aluminum. Bond pads 1545 are connected to the internal circuitry of electronic component 1540 . In one embodiment, bond pads 1545 are distributed in an array on electronic component first surface 1541 . In another embodiment, bond pads 1545 are formed on electronic component first surface 1541 directly adjacent side S of electronic component 1540 in a typical wirebond configuration pattern.

FIG. 15H is a cross-sectional view of assembly 1500 H in accordance with one embodiment of the present invention. Assembly 1500 H of FIG. 15H is similar to assembly 1500 G of FIG. 15G and only the significant differences are discussed below. Referring now to FIG. 15H , a second dielectric layer, strip, or panel, 1548 , herein referred to collectively as second dielectric layer 1548 , is applied to first dielectric layer 1508 . More particularly, a second dielectric layer second surface 1547 is mounted to first dielectric layer first surface 1507 . In one embodiment, second dielectric layer second surface 1547 is applied to first dielectric layer first surface 1507 using a tack cure. More particularly, second dielectric layer second surface 1547 is pressed on to first dielectric layer first surface 1507 . In one embodiment, second dielectric layer second surface 1547 is applied to first dielectric layer first surface 1507 by screen coating. In one embodiment, second dielectric layer second surface 1547 is applied to first dielectric layer first surface 1507 by curtain coating. In other embodiments of the invention, any other method of dielectric application is used to apply second dielectric layer 1548 .

In one embodiment of the invention, second dielectric layer 1548 includes pre-punched die holes 1574 that are at least as long, and at least as wide as, electronic component 1540 so that electronic component 1540 sits within die hole 1574 . FIG. 15I shows an overhead view of a singulated portion of a second dielectric layer 1548 including second dielectric layer second surface 1547 , and die hole 1574 prior to application of second dielectric layer second surface 1547 to first dielectric layer first surface 1507 .

FIG. 15J is a cross-sectional view of assembly 1500 J in accordance with one embodiment of the present invention. Assembly 1500 J of FIG. 15J is similar to assembly 1500 H of FIG. 15H and only the significant differences are discussed below. Referring now to FIG. 15J , a third dielectric layer, strip, or panel, 1578 , herein referred to collectively as third dielectric layer 1578 , is applied to second dielectric layer 1548 . More particularly, a third dielectric layer second surface 1577 is mounted to second dielectric layer first surface 1576 . In one embodiment, third dielectric layer second surface 1577 is applied to second dielectric layer first surface 1576 using a tack cure. More particularly, third dielectric layer second surface 1577 is pressed onto second dielectric layer first surface 1576 . In one embodiment, third dielectric layer second surface 1577 is applied to second dielectric layer first surface 1576 by screen coating. In one embodiment, third dielectric layer second surface 1577 is applied to second dielectric layer first surface 1576 by curtain coating. In other embodiments of the invention, any other method of dielectric application is used to apply third dielectric layer 1578 .

In one embodiment of the invention, third dielectric layer 1578 , like second dielectric layer 1548 includes pre-punched die holes 1580 that are at least as long and at least as wide as electronic component 1540 so that electronic component 1540 sits within die hole 1580 . As seen in FIG. 15J , with the application of third dielectric layer 1578 to second dielectric layer 1548 , a cavity 1582 is formed around electronic component 1540 such that electronic component 1540 sits within cavity 1582 with first surface 1541 below a first surface 1586 of third dielectric layer 1578 . Those of skill in the art will readily recognize that while two additional layers of dielectric material were discussed above to form cavity 1582 , in other embodiments of the invention one, three or any number of layers of dielectric material may be used and/or required to form cavity 1582 , depending on the needs of the designer and the height of the electronic component used. Consequently, using the method of this embodiment of the invention, considerable design and material flexibility is provided.

FIG. 15K is a cross-sectional view of assembly 1500 K in accordance with one embodiment of the present invention. Assembly 1500 K of FIG. 15K is similar to assembly 1500 ) of FIG. 15J and only the significant differences are discussed below. Referring now to FIG. 15K , a fourth dielectric layer, strip, or panel, 1588 , herein referred to collectively as fourth dielectric layer 1588 , is applied to third dielectric layer 1578 . More particularly, a fourth dielectric layer second surface 1587 is mounted to third dielectric layer first surface 1586 . In one embodiment, fourth dielectric layer second surface 1587 is applied to third dielectric layer first surface 1586 using a tack cure. More particularly, fourth dielectric layer second surface 1587 is pressed on to third dielectric layer first surface 1586 . In one embodiment, fourth dielectric layer second surface 1587 is applied to third dielectric layer first surface 1586 by screen coating. In one embodiment, fourth dielectric layer second surface 1587 is applied to third dielectric layer first surface 1586 by curtain coating. In other embodiments of the invention, any other method of dielectric application is used to apply fourth dielectric layer 1588 .

As seen in FIG. 15K , in one embodiment of the invention, fourth dielectric layer 1588 does not include any holes and the application of fourth dielectric layer 1588 results in electronic component 1540 being encased in dielectric material within cavity 1582 with sides S of electronic component 1540 and first surface 1541 of electronic component 1540 surrounded by dielectric material.

In one embodiment of the invention, second, third and fourth dielectric layers 1548 , 1578 and 1588 are made of a re-flowable resin material, such as prepreg, so that when heat, or another catalyst is applied to the structure formed by second, third and fourth dielectric layers 1548 , 1578 and 1588 , the structure re-flows to encase electronic component 1540 in a more or less custom fit.

FIG. 15L is a cross-sectional view of assembly 1500 L in accordance with one embodiment of the present invention. Assembly 1500 L of FIG. 15L is similar to assembly 1500 K of FIG. 15K and only the significant differences are discussed below. Referring now to FIG. 15L , the assembly is shown after second, third and fourth dielectric layers 1548 , 1578 and 1588 are re-flowed by heat, or another catalyst, to encase electronic component 1540 in encasement 1590 of dielectric material.

Of note is the fact that in the embodiment of the invention shown in FIG. 15L no gap portions, such as gap portions 1450 between electronic component 1440 sides S and cavity 1430 walls W of FIG. 14H discussed above, remain or are an issue.

FIG. 15M is a cross-sectional view of an assembly 1500 M in accordance with one embodiment of the present invention. Assembly 1500 M of FIG. 15M is similar to assembly 1500 L of FIG. 15L and only the significant differences are discussed below. Referring now to FIG. 15M , a plurality of second via apertures 1560 A, 1560 B, 1560 C, 1560 D and 1560 E are formed using a laser, i.e., using laser ablation. Second via apertures 1560 A, 1560 B, 1560 C, 1560 D and 1560 E extend through encasement 1590 to selected ones of bond pads 1545 A, 1545 B, 1545 C of electronic component 1540 and selected ones of first electrically conductive vias 1524 and first electrically conductive traces 1525 . In one embodiment, second via apertures 1560 A, 1560 B, 1560 C, 1560 D and 1560 E are cylindrical in shape, however, other shapes are used in other embodiments. Bond pads 1545 A, 1545 B, 1545 C of electronic component 1540 and first electrically conductive vias 1524 and first electrically conductive traces 1525 are exposed through second via apertures 1560 A, 1560 B, 1560 C, 1560 D and 1560 E. In one embodiment, the laser intensity is set to be sufficient to remove portions of encasement 1590 . However, the laser intensity is set to be insufficient to remove bond pads 1545 A, 1545 B, 1545 C. Accordingly, pulsing of the laser forms a single second via aperture 1560 A, 1560 B, 1560 C, 1560 D or 1560 E extending through encasement 1590 to one of bond pads 1545 A, 1545 B, or 1545 C of electronic component 1540 . The laser is then stepped to the next location to form the next second via aperture 1560 A, 1560 B, 1560 C, 1560 D or 1560 E. To illustrate, electronic component 1540 includes bond pads 1545 A, 1545 B, 1545 C on first surface of electronic component 1540 . Second via aperture 1560 A, 1560 B, 1560 C of the plurality of second via aperture 1560 A, 1560 B, 1560 C, 1560 D and 1560 E extend through encasement 1590 to bond pads 1545 A, 1545 B, 1545 C, respectively. In addition, second via aperture 1560 E and 1560 D of the plurality of second via aperture 1560 A, 1560 B, 1560 C, 1560 D and 1560 E extend through encasement 1590 to first electrically conductive vias 1524 and first electrically conductive traces 1525 , respectively. To further illustrate, initially, the laser is pulsed to form second via aperture 1560 A. The laser is then stepped and pulsed again to form second via aperture 1560 B. The laser is then stepped and pulsed again to form second via aperture 1560 C. The laser is stepped and pulsed repeatedly until all of second via aperture 1560 A, 1560 B, 1560 C, 1560 D and 1560 E are formed. However, in another embodiment, a plurality of lasers are simultaneous pulsed to form some or all of second via aperture 1560 A, 1560 B, 1560 C, 1560 D and 1560 E simultaneously. In yet other embodiments, second via aperture 1560 A, 1560 B, 1560 C, 1560 D and 1560 E are formed using selective etching, mechanical drilling, or other techniques.

FIG. 15N is a cross-sectional view of an assembly 1500 N in accordance with one embodiment of the present invention. Assembly 1500 N of FIG. 15N is similar to assembly 1500 M of FIG. 15M and only the significant differences are discussed below. Referring now to FIGS. 15M and 15N together, second via apertures 1560 A, 1560 B, 1560 C, 1560 D and 1560 E are filled with an electrically conductive material, e.g., a metal or metal containing material, an electrically conductive adhesive such as a silver filled adhesive or polymer, or solder paste, to form second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E.

In one embodiment, copper or a copper containing material is plated in second via apertures 1560 A, 1560 B, 1560 C, 1560 D and 1560 E to form second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E. In another embodiment, second via apertures 1560 A, 1560 B, 1560 C, 1560 D and 1560 E are filled with an electrically conductive adhesive, which is then cured, if necessary, to form second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E. In yet another embodiment, second via apertures 1560 A, 1560 B, 1560 C, 1560 D and 1560 E are filled with a solder paste. Assembly 1500 L is then heated to reflow the solder paste to form second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E. After formation of second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E, any excess electrically conductive material formed on encasement first surface 1599 is removed. Illustratively, an etch or physical grinding process is used. In one embodiment, an over-etch process is used to slightly over-etch second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E. Thus, second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E remain recessed within second via apertures 1560 A, 1560 B, 1560 C, 1560 D and 1560 E. This ensures that shorting between second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E from excess electrically conductive material is avoided.

Second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E are electrically connected to corresponding bond pads 1545 A, 1545 B, 1545 C of electronic component 1540 and first electrically conductive vias 1524 and first electrically conductive traces 1525 . To illustrate, second electrically conductive vias 1561 A, 1561 B, 1561 C of the plurality of second electrically conductive vias 1561 A, 15613 , 1561 C are electrically connected to bond pads 1545 A, 1545 B, 1545 C of electronic component 1540 , respectively. Consequently, second electrically conductive vias 1561 A, 1561 B, 1561 C extend from bond pads 1545 A, 1545 B, 1545 C, through encasement 1590 , to be adjacent or slightly recessed from encasement first surface 1599 . Likewise, second electrically conductive vias 1561 D, 1561 E are electrically connected to first electrically conductive vias 1524 and first electrically conductive traces 1525 . Consequently, second electrically conductive vias 1561 D, 1561 E extend from first electrically conductive vias 1524 and first electrically conductive traces 1525 , through encasement 1590 , to be adjacent or slightly recessed from encasement first surface 1599 . Stated another way, bond pads 1545 A, 1545 B, 1545 C of electronic component 1540 and first electrically conductive vias 1524 and first electrically conductive traces 1525 are electrically connected to corresponding second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E, and encasement first surface 1599 , without the use of a solder, e.g., without the use of flip chip bumps, and without the need to form a solder wetting layer, e.g., a nickel/gold layer, on bond pads 1545 A, 1545 B, 1545 C. This maximizes the reliability of the electrical connection between second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E and bond pads 1545 A, 1545 B, 1545 C of electronic component 1540 and first electrically conductive vias 1524 and first electrically conductive traces 1525 , while at the same time minimizing impedance.

After formation of second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E, assembly 1500 N is inspected, e.g., optically using an automatic inspection system, to insure that all second via apertures 1560 A, 1560 B, 1560 C, 1560 D and 1560 E are properly filled with electrically conductive material, i.e., to inspect the integrity of second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E. In one embodiment, any defective or unformed second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E detected during the inspection are corrected, e.g., by etch removal of second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E, reapplication of the electrically conductive material to reform second electrically conductive vias 1561 A, 1561 B, 1561 C, 1561 D, and 1561 E, e.g., re-plating, and removal of any excess electrically conductive material.

In this manner, the encased electronic component packages are fabricated with a maximum yield, e.g., essentially a 100 percent yield. This further minimizes the fabrication cost of the wafer level electronic component packages.

This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification or not, such as variations in structure, dimension, type of material and manufacturing process may be implemented by one of skill in the art in view of this disclosure.