LexDanaLexDanabeta
Inventor

David Jon Hiner

Inventor
Chandler, AZ, US

Overview

79→
Patents
2004–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 79 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1036%
H01LSemiconductor devices18%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H05KPrinted circuits11%
Y10TTechnical subjects covered by former us classification11%
H10DInorganic electric semiconductor devices3%
H10BElectronic memory devices2%
H01PWaveguides1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests0%
PatentTitleYear
11,094,560Encapsulated semiconductor package202111,081,370Methods of manufacturing an encapsulated semiconductor device202110,943,858Semiconductor package and fabricating method thereof202110,811,277Encapsulated semiconductor package202010,784,232Semiconductor package and fabricating method thereof202010,714,378Semiconductor device package and manufacturing method thereof202010,672,740Semiconductor package with high routing density patch202010,497,674Semiconductor package and fabricating method thereof201910,461,006Encapsulated semiconductor package201910,312,220Semiconductor package and fabricating method thereof201910,283,400Semiconductor device package and manufacturing method thereof201910,192,816Semiconductor package and fabricating method thereof201910,128,194Trace stacking structure and method201810,090,234Semiconductor device package and manufacturing method thereof201810,074,630Semiconductor package with high routing density patch201810,032,748Semiconductor package and fabricating method thereof201810,014,240Embedded component package and fabrication method20189,966,300Semiconductor device package and manufacturing method thereof20189,852,976Semiconductor package and fabricating method thereof20179,818,684'Electronic device with a plurality of redistribution structures having different respective sizes'20179,812,386'Encapsulated semiconductor package'20179,799,592'Semicondutor device with through-silicon via-less deep wells'20179,704,842'Interposer, manufacturing method thereof, semiconductor package using the same, and method for fabricating the semiconductor package'20179,691,635'Buildup dielectric layer having metallization pattern semiconductor package fabrication method'20179,653,428'Semiconductor package and fabricating method thereof'20179,627,353'Method of manufacturing a semiconductor package'20179,576,917'Embedded die in panel method and structure'20179,553,041'Semiconductor device package and manufacturing method thereof'20179,543,242'Semiconductor package and fabricating method thereof'20179,462,704'Extended landing pad substrate package structure and method'20169,437,575'Semiconductor device package formed in a chip-on-wafer last process using thin film adhesives'20169,349,681'Semiconductor device package and manufacturing method thereof'20169,324,614'Through via nub reveal method and structure'20169,230,883'Trace stacking structure and method'20169,159,672'Through via connected backside embedded circuit features structure and method'20159,136,159'Method and system for a semiconductor for device package with a die-to-packaging substrate first bond'20159,129,943'Embedded component package and fabrication method'20159,082,833'Through via recessed reveal structure and method'20159,048,298'Backside warpage control structure and fabrication method'20159,040,349'Method and system for a semiconductor device package with a die to interposer wafer first bond'20158,987,050'Method and system for backside dielectric patterning for wafer warpage and stress control'20158,872,329'Extended landing pad substrate package structure and method'20148,826,531'Method for making an integrated circuit substrate having laminated laser-embedded circuit layers'20148,802,499'Methods for temporary wafer molding for chip-on-wafer assembly'20148,501,543'Direct-write wafer level chip scale package'20138,440,554'Through via connected backside embedded circuit features structure and method'20138,432,022'Shielded embedded electronic component substrate fabrication method and structure'20138,409,658'Conformal shielding process using flush structures'20138,390,130'Through via recessed reveal structure and method'20138,341,835'Buildup dielectric layer having metallization pattern semiconductor package fabrication method'20138,324,511'Through via nub reveal method and structure'20128,316,536'Multi-level circuit substrate fabrication method'20128,296,941'Conformal shielding employing segment buildup'20128,220,145'Isolated conformal shielding'20128,188,584'Direct-write wafer level chip scale package'20128,176,628'Protruding post substrate package structure and method'20128,110,909'Semiconductor package including top-surface terminals for mounting another semiconductor package'20128,026,587'Semiconductor package including top-surface terminals for mounting another semiconductor package'20117,977,163'Embedded electronic component package fabrication method'20117,911,037'Method and structure for creating embedded metal features'20117,723,210'Direct-write wafer level chip scale package'20107,692,286'Two-sided fan-out wafer escape package'20107,671,457'Semiconductor package including top-surface terminals for mounting another semiconductor package'20107,670,962'Substrate having stiffener fabrication method'20107,589,398'Embedded metal features structure'20097,572,681'Embedded electronic component package'20097,548,430'Buildup dielectric and metallization process and semiconductor package'20097,501,338'Semiconductor package substrate fabrication method'20097,420,272'Two-sided wafer escape package'20087,399,661'Method for making an integrated circuit substrate having embedded back-side access conductors and vias'20087,365,006'Semiconductor package and substrate having multi-level vias fabrication method'20087,361,533'Stacked embedded leadframe'20087,247,523'Two-sided wafer escape package'20077,190,062'Embedded leadframe semiconductor package'20077,185,426'Method of manufacturing a semiconductor package'20077,145,238'Semiconductor package and substrate having multi-level vias'20067,028,400'Integrated circuit substrate having laser-exposed terminals'20066,930,257'Integrated circuit substrate having laminated laser-embedded circuit layers'20056,747,352'Integrated circuit having multiple power/ground connections to a single external terminal'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2021Patents assigned to AMKOR TECHNOLOGY INC (74)· patent assignee history
2004–2021Based in Chandler, AZ, US· patent location history
2012–2016Patents assigned to HUEMOELLER RONALD PATRICK (19)· patent assignee history
2012–2016Patents assigned to HINER DAVID JON (18)· patent assignee history
2012–2014Patents assigned to RUSLI SUKIANTO (4)· patent assignee history
2013–2015Patents assigned to KELLY MICHAEL G (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
AMKOR TECHNOLOGY INC742004–2021
HUEMOELLER RONALD PATRICK192012–2016
HINER DAVID JONself182012–2016
KELLY MICHAEL G52013–2015
RUSLI SUKIANTO42012–2014
Locations
LocationPatentsSpan
Chandler, AZ, US792004–2021