Burst mode control circuit

The present invention relates to a semiconductor memory, and more particularly, to a burst mode control circuit capable of facilitating realization of a circuit and reducing current consumption in a LPDDR2.

As is well known, a Double Data Rate (DDR), which can input and output data in synchronization with both rising edge and falling edge of a clock upon input and output of the data, operates in a burst mode in order to effectively perform continuous read or write operations.

The burst mode is set by a first burst signal BL 4 and a second burst signal BL 8 . When the first burst signal BL 4 is set to a high level, a burst length is set to 4 and thus data of 4 bits is continuously inputted or outputted by a single command. When the second burst signal BL 8 is set to a high level, the burst length is set to 8 and thus data of 8 bits is continuously inputted or outputted by a single command. In general, since the burst length is defined up to 8 in a DDR2, it is easy to realize an internal command generation circuit for providing the burst mode.

Meanwhile, there has been developed a Low Power DDR2 (LPDDR2) which can markedly improve power consumption and data transfer speed of mobile devices. The DDR2 can realize a data transfer speed of 800 Mbps, which is the highest speed in the field, at a voltage of 1.2 V, and is applied with ultra-fine process of 66 nm technology to thereby allow a mobile memory chip to be packaged to a size of 9 mm*12 mm. Since the burst length is defined up to 16 in the LPDDR2, there has been a problem that realization of a burst mode control circuit for generating a column access signal which controls a burst mode operation is quite complex. Such problem will be described with reference to FIG. 1 , which shows a conventional burst mode control circuit used in LPDDR2.

A conventional burst mode control circuit shown in FIG. 1 is used when a 4-bit prefetch is applied, and includes an internal command generation unit 10 , a burst pulse control unit 12 and a column access signal generation unit 14 .

The internal command generation unit 10 decodes a plurality of external commands CMD<0:3> in response to a clock signal CLK to generate a read command RD_CMDP, a write command WT_CMDP and an interrupt end signal BST. The read command RD_CMDP is a pulse signal generated upon a read operation, the write command WT_CMDP is a pulse signal generated upon a write operation and the interrupt end signal BST is a level signal generated from a pulse signal to pause the burst mode by an interrupt.

The burst pulse control unit 12 controls a pulse number of a burst pulse YBURSYP according to a first burst signal BL 4 and a second burst signal BL 8 when a pulse of the read command RD_CMDP is inputted upon the read operation or a pulse of the write command WT_CMDP is inputted upon the write operation. More specifically, the pulse of the burst pulse YBURSTP is not generated when the burst length is set to 4 and only the first burst signal BL 4 is thus at a high level, the burst pulse YBURSTP is generated in one pulse when the burst length is set to 8 and only the second burst signal BL 8 is thus at a high level, and the burst pulse YBURSTP is generated in three pulses when the burst length is set to 16 and both the first burst signal BL 4 and the second burst signal BL 8 are at a low level.

The column access signal generation signal 14 generates a column access signal INT_CASP from the burst pulse YBURSTP in synchronization with the clock signal CLK. Like the burst pulse YBURSTP, the column access signal INT_CASP is not generated as a pulse when the burst length is set to 4, is generated in one pulse when the burst length is 8, and is generated in three pulses when the burst length is 16. The burst mode is carried out when the column access signal INT_CASP is generated as such and this is because 4-bit data is basically inputted or outputted in the case that the 4-bit prefetch is applied and 4-bit data is inputted or outputted each time a pulse of the column access signal INT_CASP is generated.

Since the burst pulse control unit 12 included in the conventional burst mode control circuit configured as described above includes three clock shifters in order to provide a burst mode in which the burst length is set to 16, there has been a problem that realization of the circuit is quite complex and current consumption is very large.

In an aspect of this disclosure, there is provided a burst mode control circuit having a reduced number of clock shifters used to generate pulses periodically in a burst operation period, thereby capable of facilitating circuit realization and reducing current consumption in LPDDR2.

In an embodiment, a burst mode control unit includes a burst period signal generation unit for generating a burst period signal which is enabled during a burst mode operation period, a burst pulse generation unit for generating a burst pulse, which is generated at every predetermined number of cycles during the enabled period of the burst period signal, in response to a read command and a write command, and a column access signal generation unit for receiving the burst signal and a clock signal and generating a column access signal which controls input and output of data during the burst mode operation period.

In another embodiment, a burst mode control unit includes a burst pulse generation unit for generating a burst pulse, which includes a pulse generated at every predetermined number of cycles during a burst mode operation period, and a column access signal generation unit for receiving the burst signal and a clock signal and generating a column access signal which controls input and output of data during the burst mode operation period.

The above and other aspects, features and other advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing a configuration of a conventional burst mode control circuit;

FIG. 2 is a diagram illustrating a configuration of a burst mode control circuit in accordance with an embodiment of the present invention;

FIG. 3 is a circuit diagram illustrating a burst period signal generation unit included in the burst mode control circuit shown in FIG. 2 ;

FIG. 4 is a circuit diagram illustrating a clock shifting unit included in the burst period signal generation unit shown in FIG. 3 ;

FIG. 5 is a circuit diagram illustrating a burst pulse generation unit included in the burst mode control circuit shown in FIG. 2 ;

FIG. 6 is a circuit diagram illustrating a column access signal generation unit included in the burst mode control circuit shown in FIG. 2 ; and

FIG. 7 is a timing diagram illustrating an operation of the burst mode control circuit of FIG. 2 .

Hereinafter, embodiments of the present invention will be described with reference to accompanying drawings. However, the embodiments are for illustrative purposes only and are not intend to limit the scope of the invention.

FIG. 2 is a diagram illustrating a configuration of a burst mode control circuit in accordance with an embodiment of the present invention

As shown in FIG. 2 , a burst mode control circuit of the present embodiment includes an internal command generation unit 2 , a burst period signal generation unit 3 , a burst pulse generation unit 4 and a column access signal generation unit 5 .

The internal command generation unit 2 decodes a plurality of external commands CMD<0:3> in response to a clock signal CLK to generate a read command RDCMDP, a write command WT_CMDP and an interrupt end pulse BSTP. The internal command generation unit 2 , unlike the conventional one, outputs a pulse signal, as it is, generated to pause a burst mode by an interrupt as the interrupt end pulse BSTP without conversion into a level signal.

The burst period signal generation unit 3 includes a pulse signal generation unit 30 and a signal driving unit 32 as shown in FIG. 3 . The pulse signal generation unit 30 includes a first pulse signal generation unit 300 and a clock shifting unit 310 . The detailed configuration of the burst period signal generation unit 3 is as follows.

The first pulse generation unit 300 includes a logic unit 301 , a driving unit 302 , a driving control unit 303 , an initializing unit 304 and a latch unit 305 . The logic unit 301 includes a NAND gate ND 30 and an inverter IV 31 which perform a logic AND operation on an inverted signal of a burst signal BL 4 , inputted to a high level when the burst length is set to 4, and a reset signal RESET inputted thereto. The driving unit 302 includes a PMOS transistor P 30 , which is turned on for pull-up driving when the output signal from the logic unit 301 is at a low level, and a NMOS transistor N 30 , which is turned on for pull-down driving when the output signal from the logic unit 301 is at a high level. The driving control unit 303 includes a NMOS transistor N 31 which is turned on when a high level pulse of the read command RD_CMD is inputted and a NMOS transistor N 32 which is turned on when a high level pulse of the write command WT_CMD is inputted. The initializing unit 304 includes a PMOS transistor P 31 which initializes a node nd 30 to a high level in response to a power up signal PWRUP which is at a low level in a power up period.

The first pulse signal generation unit 300 configured as described above generates a first pulse signal enabled to a high level in a case that the burst length is set to 8 or 16 with the reset signal RESET being inputted to a high level and the high level pulse of the read command RD_CMD or the write command WT_CMD is inputted. Meanwhile, the first pulse signal generation unit 300 generates the first pulse signal PS 1 at a low level when the burst length is set to 4 or when the reset signal RESET at a low level is inputted.

The clock shifting unit 310 includes a pulse output unit 311 and a reset signal output unit 314 as shown in FIG. 4 . The pulse output unit 311 includes a transfer gate T 30 which transfers the first pulse signal PS 1 at a falling edge (shifted from a high level to a low level) of the clock signal CLK, a latch unit 312 which latches the output signal from the transfer gate T 30 , a transfer gate T 31 which transfers the output signal from the latch unit 312 at a rising edge (shifted from a low level to a high level) of the clock signal CLK, and a latch unit 313 which latches the output signal from the transfer gate T 31 and outputs a second pulse signal PS 2 . The reset signal output unit 314 buffers the output signal from the latch unit 312 to output the buffered signal as a reset signal RESET when the clock signal CLK of a high level is inputted.

The clock shifting unit 310 configured as described above generates, when the first pulse signal PS 1 is enabled to a high level, the second pulse signal PS 2 enabled to a high level and a reset signal RESET enabled to a low level after a period corresponding to one cycle of the clock signal CLK is elapsed. Since the reset signal RESET enabled to a low level is fed back to the first pulse signal generation unit 300 to disable the first pulse signal to a low level, high level pulse widths of the first pulse signal PS 1 and the second pulse signal PS 2 generated by shifting the first pulse signal PS 1 are determined to one cycle of the clock signal CLK.

The signal driving unit 32 includes a PMOS transistor P 32 which operates as a pull-up device pull-up driving a node nd 31 in response to a burst end signal BURST_END, a PMOS transistor P 33 which operates as a pull-up device pull-up driving the node nd 31 in response to the interrupt end pulse BSTP, and a latch unit 320 which latches a signal of the node nd 31 to output the latched signal as a burst period signal YBURST. Here, the burst end signal BURST_END is a signal generated to a low level pulse after a burst mode operation period is ended, and is a signal supported by a specification in the LPDDR2. This burst end signal BURST_END is not generated to a low level pulse when the burst length is set to 4, and is generated to a low level pulse after three cycle periods of the clock signal CLK are elapsed from the input of the pulses of the read command RD_CMDP and the write command WT_CMDP when the burst length is set to 8, and is generated to a low level pulse after seven cycle periods of the clock signal CLK are elapsed from the input of the pulses of the read command RD_CMDP and the write command WT_CMDP when the burst length is set to 16. Also, the interrupt end pulse BSTP is a signal generated to pause a burst mode by an interrupt.

The signal driving unit 32 configured as described above enables the burst period signal YBURST to a high level in response to the high level pulse of the second pulse signal PS 2 , and disables the burst period signal YBURST to a low level in the period when the low level pulse of the burst end signal BURST_END is inputted. Therefore, the burst period signal YBURST is generated to a signal enabled to a high level in the burst mode operation period.

The burst pulse generation unit 4 includes an internal clock generation unit 40 and a buffer unit 41 as shown in FIG. 5 . The internal clock generation unit 40 includes a control signal generation unit 400 and an oscillator 402 . Hereinafter, the configuration of the burst pulse generation unit 4 will be described in more detail.

The control signal generation unit 400 includes a logic unit 401 which performs a logic OR operation on the read command RD_CMDP and the write command WT_CMDP inputted thereto, a NOR gate NR 41 which performs a logic NOR operation on the burst signal BL 4 and the output signal of the logic unit 401 inputted thereto to generate a first control signal CS 1 , and a NAND gate ND 40 which performs a logic NAND operation on the clock signal CLK and the output signal of the NOR gate NR 41 to generate a second control signal CS 2 . The control signal generation unit 400 configured as described above generates, when a high level pulse of the read command RD_CMDP or the write command WT_CMDP is inputted, the first control signal CS 1 enabled to a low level and the second control signal CS 2 enabled to a high level.

The oscillator 402 includes a PMOS transistor which drives a node nd 40 to a high level, inverters IV 42 , IV 45 which are driven when the second control signal at a low level is inputted, latch units 403 , 404 and an inverter IV 48 . The oscillator 402 configured as described above drives the node nd 40 to a high level by the first control signal CS 1 generated to a low level when the high level pulse of the read command RD_CMDP or the write command WT_CMDP is inputted, and performs an oscillating operation to generate an internal clock HALF_CLK when the first control signal CS 1 is disabled to a high level and the second control signal is enabled to a low level after the high level pulse of the read command RD_CMDP or the write command WT_CMDP is inputted. Here, the internal clock HALF_CLK is generated to a signal having a cycle period twice of the cycle of the clock signal CLK by controlling sizes of the inverters IV 42 , IV 43 , IV 45 , IV 46 , IV 48 configuring the oscillator.

The buffer unit 41 includes a NAND gate ND 41 and an inverter IV 49 which perform a logic AND operation on the burst period signal YBURST and the internal clock HALF_CLK inputted thereto. The buffer unit 41 configured as described above buffers the internal clock HALF_CLK to output the buffered clock as the burst pulse YBURSTP in a period where the burst period signal YBURST is at a high level.

The column access signal generation unit 5 includes a NAND gate ND 50 and an inverter IV 50 which perform a logic AND operation on the clock signal CLK and the burst period signal YBURST inputted thereto. The column access signal generation unit 5 configured as described above buffers the burst pulse YBURSTP to output the buffered pulse as a column access signal INT_CASPN in a period where the clock signal CLK is at a high level.

An operation of the burst mode control circuit of the present embodiment configured as described above configured as described above will be described, and a case that the burst length is set to 16 is exemplarily explained hereinafter with reference to FIG. 7 .

First, when the external commands CMD<0:3> having a combination for performing a read operation are inputted, the internal command generation unit 2 generates a high pulse of the read command RD_CMDP in a t 1 period.

Next, the burst period signal generation unit 3 receives the read command RD_CMDP, the burst end signal BURST_END and the burst signal BL 4 and generates the burst period signal YBURST enabled to a high level in the burst mode operation period. The operation of the burst period signal generation unit 3 will be described in more detail with reference to FIGS. 3 and 4 .

Referring to FIGS. 3 and 4 , the first pulse signal generation unit 300 receives the high pulse of the read command RD_CMDP to enable the first pulse signal PS 1 to a high level in the t 1 period. When the first pulse signal PS 1 is enabled to a high level, the clock shifting unit 310 generates the second pulse signal PS 2 which is enabled to a high level in a t 2 period and generates the reset signal RESET which is enabled to a low level in the t 2 period. Since the first pulse signal generation unit 300 disables the first pulse signal PS 1 to a low level when the reset signal RESET is enabled to a low level, a width of the enabled period of the first pulse signal PS 1 becomes one cycle period of the clock signal CLK, i.e. t 1 ˜t 2 periods. Also, since the clock shifting unit 310 receives the first pulse signal PS 1 to disable the second pulse signal PS 2 to a low level, a width of the enabled period of the second pulse signal PS 2 becomes one cycle period of the clock signal CLK, i.e. t 2 ˜t 3 periods. Consequently, the second pulse signal is generated as a signal which is shifted from the first pulse signal PS 1 by one cycle period of the clock signal CLK.

When the second pulse signal PS 2 at a high level is applied during the t 2 ˜t 3 periods, the signal driving unit 32 generates the burst period signal YBURST which is enabled to a high level in the t 2 period. Also, the signal driving unit 32 receives the burst end signal BURST_END which is generated as a low level pulse after seven cycle periods of the clock signal CLK is elapsed from the input of the high level pulse of the read command RD_CMDP, and generates the burst period signal YBURST which is disabled to a low level. Therefore, when the burst length is set to 16, the burst period signal YBURST outputted from the signal driving unit 32 is maintained at a high level until seven cycle periods of the clock signal CLK is elapsed from the period when the high level pulse of the read command RD_CMDP is inputted. In other words, the burst period signal YBURST is enabled to a high level from the t 1 period to a t 8 period.

Next, the burst pulse generation unit 4 receives the read command RD_CMDP, the burst signal BL 4 and the burst period singal and generates the burst pulse. An operation of the burst pulse generation unit 4 will be described in more detail with reference to FIG. 5 .

Referring to FIG. 5 , the control signal generation unit 400 receives the high pulse of the read command RD_CMDP and generates the first control signal CS 1 enabled to a low level and the second control signal CS 2 disabled to a high level. Since the first control signal CS 1 at a low level turns on the PMOS transistor P 40 to drive the node nd 40 to a high level and the second control signal CS 2 at a high level stops the driving of the inverters IV 42 , IV 45 , the oscillator does not perform the oscillating operation. After the high level pulse of the read command RD_CMDP is inputted, the first control signal CS 1 is disabled to a high level and the second control signal is enabled to a low level. Therefore, the oscillator 402 performs the oscillating operation to generate the internal clock HALF_CLK having a cycle twice of the cycle of the clock signal CLK. The buffer unit 41 buffers the internal clock HALF_CLK to output the buffered clock as a burst pulse YBURSTP in a period where the burst period signal is at a high level.

Next, the column access signal generation unit 5 buffers the burst pulse YBURSTP to output the buffered pulse as the column access signal INT_CASPN in a period where the clock signal CLK is at a high level. Therefore, a first pulse of the column access signal INT_CASPN is generated in the t 3 period, a second pulse in the t 5 period, and a third pulse in the t 7 period. In the case that 4-bit prefetch is applied, since data of 4 bits is inputted or outputted at every pulse of the column access signal INT_CASPN, data of 16 bits is continuously outputted upon the read operation.

As is apparent from the above description, the burst mode control circuit of the present embodiment generates the burst period signal YBURST which is enabled to a high level in the burst mode operation period, generates the internal clock HALF_CLK which is generated every predetermined number of cycles using the oscillator 402 in the period where the burst period signal YBURST is at a high level, and generates the pulse of the column access signal INT_CASPN from the internal clock HALF_CLK. As such, the burst mode control circuit of the present embodiment facilitates the realization of the circuit and reduces current consumption by using the oscillator 402 , capable of reducing use of the clock shifter, to generate the pulse of the column access signal INT_CASPN.

While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

This disclosure claims priority to Korean patent application number 10-2009-0002256, filed on Jan. 12, 2009, the entire contents of which are incorporated herein by reference.