Electric system and alarm device thereof

This Non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application No(s). 096150223, filed in Taiwan, Republic of China on Dec. 26, 2007, the entire contents of which are hereby incorporated by reference.

1. Field of Invention

The present invention relates to an electronic system and an alarm device thereof.

2. Related Art

Functional requirements of an electronic apparatus are getting higher, and more accessory apparatuses are required by the electronic apparatus to satisfy the multi-functional requirement. Usually, a processor controls the electronic apparatus for the purpose of driving, controlling, detecting, indicating and communication transmitting.

Referring to FIG. 1 , a conventional system 1 has a micro control unit (MCU) 12 , a speed detecting end 13 and a fan 14 . The micro control unit 12 is electrically connected to the electronic device, such as a fan, and the speed detecting end 13 for detecting the rotating speed of the fan 14 .

According to an external input signal S 01 , the conventional micro control unit 12 can output a control signal S 02 to control the fan 14 . Herein, the external input signal S 01 can be a pulse width modulation (PWM) signal, which is composed of at least one high-level digital signal and at least one low-level digital signal. The micro control unit 12 can control the fan 14 operating at a normal status, such as the fan operates at a certain rotating speed, according to the external input signal S 01 (PWM signal).

If the micro control unit 12 has malfunction or damage in hardware due to the unknown external factors, it may continuously control the fan 14 operating at the high-speed or low-speed rotation status for a long time. This may cause the damage of the fan 14 .

When the micro control unit 12 has malfunction or damage in hardware, it can not correctly control the operation of the fan 14 for dissipating heat. Therefore, the fan 14 can not perform the heat dissipation efficiently, and if this problem goes worse, the entire electronic apparatus may be shut down.

Moreover, the micro control unit 12 has a control interface (not shown), which is connected with a connector (not shown), so that the external input signal S 01 can be inputted to the micro control unit 12 through the connector and the control interface. When the fan 14 operates normally, and the connector and the control interface are not perfectly connected or the connection therebetween is loosen due to vibration caused by the external force, the micro control unit 12 can not receive the external input signal S 01 . Thus, the fan 14 will keep operating. That is, the micro control unit 12 can not stop the operation of the fan 14 in this case, which may cause the extra power consumption and damage of the fan 14 .

In view of the foregoing, the present invention is to provide an electronic system and an alarm device thereof capable of generating an alarm signal to warn the user that the micro control unit has malfunction or the micro control unit can not receive the external input signal S 01 . The present invention is also to provide an electronic system capable of definitely judging whether a peripheral device is in an abnormal status and immediately outputting an alarm, and an alarm device thereof.

To achieve the above, the present invention discloses an alarm device including a first detecting unit and a controlling unit. The first detecting unit receives an input signal and outputs a first detecting signal according to the input signal. The controlling unit is electrically connected to the first detecting unit for receiving the first detecting signal and outputting a control signal according to the first detecting signal. The control signal controls an electronic device to operate under a standby mode, which means to turn off the electronic device when the first detecting signal refers to an abnormal status. The abnormal status means the input signal or the second detecting signal is always a high level DC signal or a low level DC signal.

In addition, the present invention also discloses an electronic system including an alarm device and a system device. The alarm device receives an input signal and generates a control signal according to the input signal. The system device is electrically connected to the alarm device for receiving the control signal, generating a system signal according to the control signal and outputting the system signal to the alarm device.

As mentioned above, the electronic system and the alarm device thereof according to the present invention both have the first detecting unit and the second detecting unit for respectively generating the first and second detecting signals. The controlling unit and the system device respectively receive the first detecting signal and the second detecting signal and judge whether the input signal refers to the abnormal status according to the first and second detecting signals. When the input signal refers to the abnormal status, the alarm device generates the control signal to immediately stop the operation of the electronic device and thus prevent the damage or the crash when the processor continues operating in the abnormal status due to the misjudgment. Thus, the overall quality can be enhanced.

The present invention will become more fully understood from the subsequent detailed description and accompanying drawings, which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:

FIG. 1 is a schematic illustration showing a conventional system;

FIG. 2 is a schematic illustration showing an electronic system according to a preferred embodiment of the present invention;

FIG. 3 is a schematic illustration showing an alarm device of the electronic system according to the preferred embodiment of the present invention;

FIG. 4 is a schematic illustration showing a second detecting unit of the electronic system according to the preferred embodiment of the present invention; and

FIG. 5 is a schematic illustration showing a controlling unit of the electronic system according to the preferred embodiment of the present invention.

The present invention will be apparent from the following detailed description, which proceeds with reference to the accompanying drawings, wherein the same references relate to the same elements.

Referring to FIG. 2 , an electronic system 2 according a first embodiment of the present invention includes an alarm device 21 , a system device 22 and an electronic device 23 . The alarm device 21 is electrically connected to the electronic device 23 and receives an input signal S 11 , which can be a DC signal or a pulse signal. When the input signal S 11 is a pulse signal, it can be a pulse width modulation (PWM) signal with the frequency equal to or higher than 200 Hz.

In addition, the input signal S 11 can be a feedback signal of the electronic device 23 . The input signal S 11 is determined to be a pulse signal or a DC signal according to the status of the electronic device 23 . When the electronic device 23 operates in a normal status, the input signal S 11 is the pulse signal. When the electronic device 23 operates in a floating, a short or an open status, the input signal S 11 is the DC signal, for example. In this embodiment, the input signal S 11 is an external input signal, for example.

The alarm device 21 generates a control signal S 12 and a second detecting signal S 13 according to the input signal S 11 , and the control signal S 12 controls the electronic device 23 . The electronic device 23 can be a fan device, a sensor device, a power supply device, a communication device, a flat panel display, an indicating device or a pressure indicating device.

The system device 22 electrically connected to the alarm device 21 receives the second detecting signal S 13 and thus judges whether the input signal S 11 refers to an abnormal status according to the second detecting signal S 13 . In this embodiment, the system device 22 is disposed at a client end.

FIG. 3 shows an equivalent circuit diagram of the alarm device 21 of FIG. 2 . Referring to FIGS. 2 and 3 , the alarm device 21 includes a first detecting unit 24 and a controlling unit 25 . The controlling unit 25 is electrically connected to the first detecting unit 24 . The controlling unit 25 is a micro-processing unit.

The first detecting unit 24 has an isolating circuit 241 , a first enabling circuit 242 , a second enabling circuit 243 and an output circuit 244 . In this embodiment, the isolating circuit 241 has a capacitor C 1 . The capacitor C 1 has one terminal for receiving the input signal S 11 , and the other terminal electrically connected to the first enabling circuit 242 . The isolating circuit 241 generates an adjusting signal S 14 according to the input signal S 11 and transmits the adjusting signal S 14 to the first enabling circuit 242 . The first enabling circuit 242 receives the adjusting signal S 14 and thus generates a first enabling signal S 15 according to the adjusting signal S 14 .

As shown in FIG. 3 , the first enabling circuit 242 has a resistor R 1 , a resistor R 2 , a resistor R 3 , a transistor Q 1 and a transistor Q 2 . The transistor Q 1 has a gate electrically connected to the isolating circuit 241 and the resistor R 1 to receive the adjusting signal S 14 , and a source electrically connected to a ground GND. The resistor R 2 has one terminal for receiving a power supply voltage V CC . The transistor Q 2 has a base electrically connected to the other terminal of the resistor R 2 and a drain of the transistor Q 1 , and an emitter electrically connected to the ground GND. The resistor R 3 has one terminal for receiving the power supply voltage V CC . A collector of the transistor Q 2 is electrically connected to the other terminal of the resistor R 3 , and outputs the first enabling signal S 15 to the second enabling circuit 243 . The transistor Q 1 and the transistor Q 2 are a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bipolar junction transistor (BJT), respectively.

The second enabling circuit 243 electrically connected to the first enabling circuit 242 receives the first enabling signal S 15 and thus generates a second enabling signal S 16 according to the first enabling signal S 15 . The second enabling circuit 243 has a resistor R 4 , a diode D 1 and a capacitor C 2 .

The diode D 1 has one terminal electrically connected to the output circuit 244 , and the other terminal electrically connected to the resistor R 3 and the first enabling circuit 242 to receive the first enabling signal S 15 . The capacitor C 2 has one terminal electrically connected to one terminal of the diode D 1 and one terminal of the resistor R 4 to generate the second enabling signal S 16 and to output the second enabling signal S 16 to the output circuit 244 . The other terminal of the capacitor C 2 and the other terminal of the resistor R 4 are electrically connected to the ground GND.

The second enabling circuit 243 can be an R-C adjustable integrator, and the diode D 1 is used for preventing the current of the second enabling circuit 243 from flowing back to the resistor R 3 .

As shown in FIG. 3 , the output circuit 244 receives the second enabling signal S 16 and thus generates a first detecting signal S 17 according to the second enabling signal S 16 . The output circuit 244 has a resistor R 5 and a transistor Q 3 . The transistor Q 3 has a gate electrically connected to the second enabling circuit 243 to receive the second enabling signal S 16 , and a source electrically connected to the ground GND. The resistor R 5 has one terminal for receiving the power supply voltage V CC . A drain of the transistor Q 3 is electrically connected to the other terminal of the resistor R 5 and the controlling unit, and generates the first detecting signal S 17 . The transistor Q 3 can be a MOSFET.

The operations of the first detecting unit 24 will be described in detail in the following with reference to FIGS. 2 and 3 . The isolating circuit 241 receives the input signal S 11 by the capacitor C 1 and generates the adjusting signal S 14 according to the input signal S 11 . Herein, the input signal S 11 is a pulse signal.

When the input signal S 11 is high, the gate of the transistor Q 1 in the first enabling circuit 242 receives the adjusting signal S 14 so that the transistor Q 1 turns on according to the adjusting signal S 14 and outputs the low-level signal from the drain of the transistor Q 1 to the transistor Q 2 to make the transistor Q 2 turn off.

At this time, the power supply voltage V CC , the resistor R 3 , the diode D 1 , the capacitor C 2 and the resistor R 4 form a current loop, and the power supply voltage V CC turns on the diode D 1 to charge the resistor (R 4 )-capacitor (C 2 ) circuit so that the second enabling circuit 243 outputs the high-level second enabling signal S 16 to the output circuit 244 .

The transistor Q 3 turns on according to the second enabling signal S 16 and outputs the low-level first detecting signal S 17 from the drain of the transistor Q 3 to the controlling unit 25 .

As mentioned hereinabove, when the input signal S 11 is in low level, the output circuit 244 outputs the high-level first detecting signal S 17 . Thus, the controlling unit 25 receives the first detecting signal S 17 and obtains that the input signal S 11 refers to the normal status according to the first detecting signal S 17 , that is, if the input signal S 11 is a pulse signal, the first detecting signal S 17 is also a pulse signal, and the alarm device 21 keeps generating the control signal S 12 to control the electronic device 23 to keep the electronic device 23 operating.

As shown in FIGS. 2 and 3 , when the input signal S 11 refers to the abnormal status (The abnormal status means the input signal is always a high level DC signal or a low level DC signal), the operations of the first detecting unit 24 are described in the following.

When the input signal S 11 refers to the abnormal status, the input signal S 11 is a DC signal and is transmitted to the isolating circuit 241 . At this time, the isolating circuit 241 isolates the input signal S 11 via the capacitor C 1 , and thus generates the low-level adjusting signal S 14 . The first transistor Q 1 of the first enabling circuit 242 turns off according to the low-level adjusting signal S 14 , and the transistor Q 2 receives the power supply voltage V CC via the resistor R 2 and thus turns on. Next, the power supply voltage V CC connected to the resistor R 3 is grounded via the transistor Q 2 , and the drain of the transistor Q 2 outputs the low-level first enabling signal S 15 .

Because the drain of the transistor Q 2 is in the low level, the diode D 1 turns off and the capacitor C 2 starts to discharge the energy to the resistor R 4 . After a period of time, the stored charges of the capacitor C 2 are decreased so that the second enabling circuit 243 outputs the low-level second enabling signal S 16 to the output circuit 244 . However, the low-level second enabling signal S 16 cannot make the transistor Q 3 turn on, and the first detecting signal S 17 is obtained by subtracting the voltage drop of the resistor R 5 from the power supply voltage V CC . Thus, the output circuit 244 outputs the high-level first detecting signal S 17 .

As shown in FIG. 3 , the alarm device 21 of this embodiment further includes a signal converting unit 26 , which includes a resistor R 6 , a resistor R 7 , a resistor R 8 , a transistor Q 4 , a capacitor C 3 and a diode D 2 .

The transistor Q 4 has a gate electrically connected to the resistor R 6 to receive the input signal S 11 , and a source electrically connected to the ground. The resistor R 7 has one terminal for receiving the power supply voltage V CC . A drain of the transistor Q 4 is electrically connected to the other terminal of the resistor R 7 and one terminal of the diode D 2 . The other terminal of the diode D 2 is electrically connected to one terminal of the capacitor C 3 and one terminal of the resistor R 8 . The other terminal of the capacitor C 3 and the other terminal of the resistor R 8 are electrically connected to the ground GND.

When the input signal S 11 is in low level, the gate of the transistor Q 4 receives the input signal S 11 and makes the transistor Q 4 turn off according to the input signal S 11 . At this time, the power supply voltage V CC , the resistor R 7 , the diode D 2 , the capacitor C 3 and the resistor R 8 form a current loop, and the power supply voltage V CC makes the diode D 2 turn on and thus charges the capacitor C 3 .

When the input signal is in high level, the gate of the transistor Q 4 receives the input signal S 11 and makes the transistor Q 4 turn on according to the input signal S 11 so that the low level signal is outputted from the drain of the transistor Q 4 . At this time, the capacitor C 3 discharges the energy to the resistor R 8 and thus provides the DC signal to the controlling unit 25 .

When the electronic device is in a normal status, the signal converting unit 26 is used to convert the input signal, which is also a PWM signal to a DC signal and output the DC signal to the controlling unit 25 .

Referring to FIG. 3 , the alarm device 21 of this embodiment further includes a second detecting unit 27 , which includes a resistor R 9 , a resistor R 10 , a resistor R 11 and a transistor Q 5 . The transistor Q 5 may be a BJT. A diode D 3 is provided to prevent the current of the second detecting unit 27 from flowing back to the first detecting unit 24 .

In addition, the aspect of the second detecting unit 27 is not particularly restricted in this embodiment. As shown in FIG. 4 , the second detecting unit 27 and the first detecting unit 24 can have the same elements. In the following, the second detecting unit 27 of FIG. 3 will be described as an example.

The resistor R 9 has one terminal electrically connected to the first detecting unit 24 to receive the first detecting signal S 17 , and the other terminal electrically connected to a base of the transistor Q 5 . The resistor R 10 has one terminal for receiving the power supply voltage V CC , and the other terminal electrically connected to the other terminal of the resistor R 9 and the base of the transistor Q 5 . The transistor Q 5 also has an emitter electrically connected to the ground GND, and a collector electrically connected to one terminal of the resistor R 11 to generate the second detecting signal S 13 .

When the first detecting signal S 17 is high, the base of the transistor Q 5 receives the first detecting signal S 17 and makes the transistor Q 5 turn on according to the first detecting input signal S 17 so that the collector of the transistor Q 5 outputs the low-level second detecting signal S 13 . When the first detecting signal S 17 is low, the base of the transistor Q 5 receives the first detecting signal S 17 and makes the transistor Q 5 turn off according to the first detecting signal S 17 . The second detecting signal S 13 is obtained by subtracting the voltage drop of the resistor R 11 from the power supply voltage V CC . Therefore, the second detecting unit 27 outputs the high-level second detecting signal S 13 . In other words, if the input signal S 11 is a pulse or PWM signal, the second detecting signal S 13 is also a pulse or PWM signal.

As mentioned hereinabove, when the input signal S 11 is the pulse signal, the second detecting signal S 13 is also the pulse signal in the normal status. When the second detecting signal S 13 is continuously kept at the high level or the low level for a period of time, it represents that the input signal S 11 refers to the abnormal status.

As shown in FIGS. 2 and 3 , when the controlling unit 25 receives the first detecting signal S 17 , which refers to the abnormal status, or the system device 22 receives the second detecting signal S 13 , which refers to the abnormal status, the alarm device 21 generates the control signal S 12 to make the electronic device 23 operate under a standby mode, such as a sleep mode or an idle mode. Herein, the electronic device 23 is a fan device in the following example. When the fan device is in the standby mode, the power supply voltage of the fan device is cut off to stop the fan device and prevent the fan device from continuously operating to cause the damage or to crash the electronic system 2 .

Referring to FIG. 5 , the controlling unit 25 includes an inverting circuit 251 and a driving circuit 252 electrically connected to the inverting circuit 251 .

The inverting circuit 251 electrically connected to the first detecting unit 24 receives the first detecting signal S 17 and outputs a first inverse detecting signal S 18 according to the first detecting signal S 17 . The inverting circuit includes a transistor Q 6 , a transistor Q 7 and a resistor R 12 .

The transistor Q 6 has a base electrically connected to a resistor R 13 and a base of the transistor Q 7 , and an emitter for receiving the power supply voltage V CC . The transistor Q 7 has an emitter electrically connected to the ground. The resistor R 12 has one terminal electrically connected to a collector of the transistor Q 6 , and the other terminal electrically connected to a collector of the transistor Q 7 .

The first detecting signal S 17 is inputted to the controlling unit 25 via the resistor R 13 . When the first detecting signal S 17 is in high level, the transistor Q 6 turns off and the transistor Q 7 turns on. At this time, the inverting circuit 251 outputs and transmits the low-level first inverse detecting signal S 18 to the driving circuit 252 .

When the first detecting signal S 17 is in low level, the transistor Q 7 turns off and the transistor Q 6 turns on. At this time, the inverting circuit 251 outputs and transmits the high-level first inverse detecting signal S 18 to the driving circuit 252 . The driving circuit 252 receives the first inverse detecting signal S 18 and outputs the control signal S 12 according to the first inverse detecting signal S 18 .

In summary, the electronic system and the alarm device thereof according to the present invention both have the first detecting unit and the second detecting unit for respectively generating the first and second detecting signals. The controlling unit and the system device respectively receive the first detecting signal and the second detecting signal, and judge whether the input signal refers to the abnormal status according to the first and second detecting signals. When the input signal refers to the abnormal status, the alarm device generates the control signal to immediately stop the operation of the electronic device and thus prevent the damage or the crash when the processor continues operating in the abnormal status due to the misjudgment. Thus, the overall quality can be enhanced.

Although the present invention has been described with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments, will be apparent to persons skilled in the art. It is, therefore, contemplated that the appended claims will cover all modifications that fall within the true scope of the present invention.