Method for achieving very small feature size in semiconductor device by undertaking silicide sidewall growth and etching

1. Field of the Invention

This invention relates generally to semiconductor device manufacture, and more particularly, to a method of achieving very small feature size of such a device.

2. Discussion of the Related Art

FIGS. 1-3 illustrate a conventional method for forming a feature, for example, a gate, of a MOSFET transistor. As shown ( FIG. 1 ), a semiconductor, for example silicon, substrate 20 is provided. A thin oxide layer 22 is grown on the substrate 20 , and a layer of polysilicon 24 is deposited on the oxide layer 22 . A layer of photoresist 26 is then provided on and in contact with the polysilicon layer 24 . Using well-known lithographic techniques, the layer of photoresist 26 is then patterned ( FIG. 2 ) to form a photoresist body 26 A on the polysilicon layer 24 . Using the photoresist body 26 A as a mask, the unmasked polysilicon and oxide are etched away ( FIG. 3 ), forming gate oxide 22 A on and in contact with the substrate 20 and polysilicon gate 24 A on and in contact with the gate oxide 22 A. The photoresist body 26 A is then removed, and further processing steps are undertaken as is well known to form a transistor including gate oxide 22 A and gate 24 A.

In etching, the width of the gate 24 A is determined by the width of the photoresist body 26 A. That is, if the photoresist body 26 A has a width A as shown, the width of the resulting polysilicon gate 24 A subsequent to the etching step will be substantially equal to the dimension A. As is well known, there is continuing interest in scaling down features sizes in semiconductor devices. It will therefore be understood that reduction in the width, i.e., dimension A of the photoresist body 26 A, is highly desirable, so that the width of the formed polysilicon gate 24 A is in turn reduced.

In patterning the photoresist 26 to provide a desired small dimension A, incorporating current lithographic technology, a light source of very short (for example 193 nm) wave length is used, resulting in the capability of providing a dimension A of the photoresist body 26 A as small as 32 nm. However, in attempting to reduce the dimension A of the photoresist body 26 A to less than 32 nm, optical interference problems arise which severely limit the ability to achieve such reduction. This in turn of course limits the ability to reduce the corresponding feature size, i.e., dimension A of the formed gate 24 A.

While the example shown and described relates to the formation of a gate of a transistor, it will be understood that this problem exists for other portions of a semiconductor device wherein photoresist is used for patterning thereof.

Therefore, what is needed is a method for overcoming the above-cited problems so that feature size in a semiconductor device can be reduced.

Broadly stated, the present invention is a method of fabricating an electronic device comprising providing first and second bodies, the second body comprising first and second portions, the second portion extending further into the first body than the first portion, removing the first portion of the second body, with at least a part of the second portion of the second body remaining, and removing material of the first body using the second portion of the second body as a mask.

The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as said preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment! when read in conjunction with the accompanying drawings, wherein:

FIG. 1-3 illustrate a prior art approach in forming a gate of a transistor; and

FIGS. 4-15 illustrate the present approach, wherein feature size of a formed gate is reduced as compared to the prior art.

Reference is now made in detail to a specific embodiment of the present invention which illustrates the best mode presently contemplated by the inventors for practicing the invention.

Initially, the steps of FIGS. 1-3 are undertaken as shown and described above to form a polysilicon element 24 A of width A, using patterned photoresist 26 A as a mask. In the resulting device, as previously described, the polysilicon element 24 A is on and in contact with gate oxide 22 A, which is in turn on and in contact with substrate 20 . Then, after removal of the photoresist body 26 A, and with reference to FIG. 4 , an oxide spacer layer 28 is grown on the resulting structure, covering the exposed portions of the substrate 20 , gate oxide 22 A, and polysilicon element 24 A. An implant step 30 is then undertaken to form lightly doped regions 32 , 34 in the substrate 20 , this step also providing dopant in the polysilicon element 24 A.

Next, and with reference to FIG. 5 , a nitride layer 36 is deposited on the resulting structure. The nitride layer 36 is then etched to forms spacers 38 , 40 ( FIG. 6 ). An etching step of the oxide spacer layer 28 is then undertaken, removing portions of the oxide spacer layer 28 from the substrate 20 , along with the portion of the oxide spacer layer 28 on the top of the polysilicon element 24 A and portions of the oxide spacer layer 28 along the sides of the polysilicon element 24 A. This step exposes the top surface S 1 of the polysilicon element 24 A and side surface portions S 2 , S 3 of the polysilicon element 24 A, and forms remaining oxide spacer layer portions 42 , 44 . This etching step of the oxide spacer layer 28 is undertaken so as to provide exposure of substantial portions of the side surfaces of the silicon element 24 A, i.e., as shown, the depths of the exposed side surface portions S 2 , S 3 from the top surface S 1 of the polysilicon element 24 A to the tops T 1 , T 2 of the oxide spacer layer portions 42 , 44 are shown by the dimensions B and C.

With reference to FIG. 7 , an implant step 46 is then undertaken to form heavily doped regions 48 , 50 in the substrate 20 , also providing dopant in the polysilicon element 24 A.

Next ( FIG. 8 ), a metal layer, in this embodiment a nickel layer 52 , is deposited over the resulting structure. Nickel of the nickel layer 52 is then reacted with polysilicon of the polysilicon element 24 A and the exposed portions of the substrate 20 mainly by diffusion of nickel into silicon, forming NiSi silicide body 54 and NiSi silicide regions 56 , 58 . The unreacted nickel is then removed, and the remaining polysilicon body 24 B has on and in contact therewith silicide body 54 , the remaining polysilicon body 24 B and silicide body 54 together forming structure 60 ( FIG. 9 ).

The diffusion of the nickel into the polysilicon element 24 A takes place inward of the exposed side surfaces S 2 , S 3 and inward of the top surface S 1 thereof (see arrows in FIG. 8 ). Because of the substantial dimensions B and C, and because diffusion of nickel into polysilicon occurs substantially evenly inwardly of the side and the top surfaces, the resulting silicide body 54 has portions 54 A, 54 B which extend further into the structure 60 from the top surface S 4 thereof than portion 54 C which is between the portions 54 A, 54 B. These portions 54 A, 54 B have depths D and E which are substantially equal to the dimensions B and C shown and described, and which are substantially greater then the depth F of the portion 54 C. As also noted, the widths G and H of the portions 54 A, 54 B are each substantially less than the width A of the remaining polysilicon body 24 B.

Next, and with reference to FIGS. 10 and 11 , a chemical-mechanical planarization (CMP) step is undertaken down to the line indicated at 62 , removing the entire silicide portion 54 C (exposing the polysilicon thereunder), and parts of the silicide portions 54 A, 54 B, with at least parts of the silicide portions 54 A, 54 B remaining. This results in silicide portions 54 A, 54 B remaining on and in contact with the remaining polysilicon body 24 B, separated by polysilicon therebetween, and, as noted previously, having respective widths G and H each of which is substantially less than the width A of the remaining polysilicon body 24 B.

With reference to FIG. 12 , some of the remaining polysilicon body 24 B and oxide 22 A are etched away, using the remaining silicide portions 54 A, 54 B as masks, forming polysilicon gates 64 , 66 , and remaining gate oxide portions 22 B, 22 C. A nitride layer 68 is then deposited on the resulting structure ( FIG. 13 ), and is etched to form spacers 70 , 72 ( FIG. 14 ). An ion implantation step 74 is undertaken ( FIG. 15 ) to form doped region 76 . The doped region 32 , 48 , doped region 76 , substrate 20 , remaining gate oxide 22 B, and polysilicon gate 64 form a transistor 78 having a gate width G, while the doped region 34 , 50 , doped region 76 , substrate 20 , remaining gate oxide 22 C, and polysilicon gate 66 form a transistor 80 having a gate width H, with both dimension G and dimension H being substantially less than dimension A. The doped region 76 may, for example, act as a common source or drain for the transistors 78 , 80 . The remaining silicide portions 54 A, 54 B can be used for example as word lines, and to reduce gate resistance and access time.

It will be seen that the present approach is capable of providing polysilicon feature width of substantially less than dimension A, without relying on photolithography. It is also possible to further reduce such width by reducing the reaction time of the nickel with polysilicon, reducing the depth of the formed silicide inward of the side and top surfaces of the polysilicon.

It will be understood that the present approach is not limited to formation of a gate of a transistor, but is applicable to any environment wherein very small feature size is desired.

The foregoing description of the embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Other modifications or variations are possible in light of the above teachings.

The embodiment was chosen and described to provide the best illustration of the principles of the invention and its practical application to thereby enable one of ordinary skill of the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally and equitably entitled.