Inventor
Minh Van Ngo
Inventor
Fremont, CA, US
Overview
Patents· 299 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1029%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%
H10DInorganic electric semiconductor devices21%
H10BElectronic memory devices10%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
C23CCoating metallic material4%
H10KOrganic electric solid-state devices2%
G11CStatic stores2%
B82YSpecific uses or applications of nanostructures2%
H01LSemiconductor devices1%
PatentTitleYear
10,944,000Contacts for semiconductor devices202110,516,044Contacts for semiconductor devices20199,831,054Insulated thermal cut-off device20179,659,690'Method for manufacturing a surface mount device'20179,646,744'Method for manufacturing a surface mount device'20179,425,325'Electrically programmable and eraseable memory device'20169,236,448'Method for achieving very small feature size in semiconductor device by undertaking silicide sidewall growth and etching'20169,202,758'Method for manufacturing a contact for a semiconductor component and related structure'20158,735,960'High ultraviolet light absorbance silicon oxynitride film for improved flash memory device performance'20148,658,496'Etch stop layer for memory cell reliability improvement'20148,647,969'Method for forming a semiconductor layer with improved gap filling properties'20148,633,074'Electrically programmable and erasable memory device and method of fabrication thereof'20148,614,475'Void free interlayer dielectric'20138,564,041'Contacts for semiconductor devices'20138,368,219'Buried silicide local interconnect with sidewall spacers and method for making the same'20138,367,493'Void free interlayer dielectric'20138,319,266'Etch stop layer for memory cell reliability improvement'20128,309,455'SiH4 soak for low hydrogen SiN deposition to improve flash memory device performance'20128,202,810'Low-H plasma treatment with N2 anneal for electronic memory devices'20128,049,334'Buried silicide local interconnect with sidewall spacers and method for making the same'20118,035,153'Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications'20118,026,169'Cu annealing for improved data retention in flash memory devices'20118,022,468'Ultraviolet radiation blocking interlayer dielectric'20117,985,674'SiH4 soak for low hydrogen SiN deposition to improve flash memory device performance'20117,927,723'Film stacks to prevent UV-induced device damage'20117,888,269'Triple layer anti-reflective hard mask'20117,884,030'Gap-filling with uniform properties'20117,880,221'Forming metal-semiconductor films having different thicknesses within different regions of an electronic device'20117,786,003'Buried silicide local interconnect with sidewall spacers and method for making the same'20107,732,276'Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications'20107,713,834'Method of forming isolation regions for integrated circuits'20107,704,878'Contact spacer formation using atomic layer deposition'20107,701,019'Tensile strained substrate'20107,670,915'Contact liner in integrated circuit technology'20107,648,886'Shallow trench isolation process'20107,632,706'System and method for processing an organic memory cell'20097,534,732'Semiconductor devices with copper interconnects and composite silicon nitride capping layers'20097,482,217'Forming metal-semiconductor films having different thicknesses within different regions of an electronic device'20097,476,604'Aggressive cleaning process for semiconductor device contact formation'20097,422,961'Method of forming isolation regions for integrated circuits'20087,341,956'Disposable hard mask for forming bit lines'20087,323,418'Etch-back process for capping a polymer memory device'20087,312,125'Fully depleted strained semiconductor on insulator transistor and method of making the same'20077,307,027'Void free interlayer dielectric'20077,307,322'Ultra-uniform silicide system in integrated circuit technology'20077,300,886'Interlayer dielectric for charge loss improvement'20077,297,592'Semiconductor memory with data retention liner'20077,238,571'Non-volatile memory device with increased reliability'20077,217,660'Method for manufacturing a semiconductor component that inhibits formation of wormholes'20077,157,335'Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices'20077,151,020'Conversion of transition metal to silicide through back end processing in integrated circuit technology'20067,118,967'Protection of charge trapping dielectric flash memory devices from UV-induced charging in BEOL processing'20067,091,088'UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing'20067,074,677'Memory with improved charge-trapping dielectric layer'20067,070,911'Structure and method for reducing standing waves in a photoresist'20067,071,562'Interconnects with improved barrier layer adhesion'20067,064,067'Reduction of lateral silicide growth in integrated circuit technology'20067,060,554'PECVD silicon-rich oxide layer for reduced UV charging'20067,060,571'Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate dielectric'20067,049,666'Low power pre-silicide process in integrated circuit technology'20067,038,320'Single damascene integration scheme for preventing copper contamination of dielectric layer'20067,033,888'Engineered metal gate electrode'20067,023,046'Undoped oxide liner/BPSG for improved data retention'20067,018,896'UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing'20067,015,504'Sidewall formation for high density polymer memory element array'20067,005,376'Ultra-uniform silicides in integrated circuit technology'20067,005,357'Low stress sidewall spacer in integrated circuit technology'20067,001,837'Semiconductor with tensile strained substrate and method of making the same'20066,989,604'Conformal barrier liner in an integrated circuit interconnect'20066,989,563'Flash memory cell with UV protective layer'20066,982,188'Post CMP precursor treatment'20066,979,903'Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers'20056,972,254'Manufacturing a conformal atomic liner layer in an integrated circuit interconnect'20056,962,857'Shallow trench isolation process using oxide deposition and anneal'20056,955,997'Laser thermal annealing method for forming semiconductor low-k dielectric layer'20056,951,220'Method of decontaminating equipment'20056,933,219'Tightly spaced gate formation through damascene process'20056,924,182'Strained silicon MOSFET having reduced leakage and method of its formation'20056,905,971'Treatment of dielectric material to enhance etch rate'20056,903,007'Process for forming bottom anti-reflection coating for semiconductor fabrication photolithography which inhibits photoresist footing'20056,900,488'Multi-cell organic memory element and methods of operating and fabricating'20056,900,121'Laser thermal annealing to eliminate oxide voiding'20056,897,144'Cu capping layer deposition with improved integrated circuit reliability'20056,894,342'Structure and method for preventing UV radiation damage in a memory cell and improving contact CD control'20056,893,929'Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends'20056,893,910'One step deposition method for high-k dielectric and metal gate electrode'20056,884,681'Method of manufacturing a semiconductor memory with deuterated materials'20056,878,592'Selective epitaxy to improve silicidation'20056,875,694'Method of treating inlaid copper for improved capping layer adhesion without damaging porous low-k materials'20056,861,350'Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode'20056,858,503'Depletion to avoid cross contamination'20056,849,925'Preparation of composite high-K/standard-K dielectrics for semiconductor devices'20056,836,398'System and method of forming a passive layer by a CMP process'20046,835,656'Method of forming ultra-shallow junctions in a semiconductor wafer with a deposited silicon layer and in-situ anneal to reduce silicon consumption during salicidation'20046,836,017'Protection of low-k ILD during damascene processing with thin liner'20046,833,581'Structure and method for preventing process-induced UV radiation damage in a memory cell'20046,830,998'Gate dielectric quality for replacement metal gate transistors'20046,828,199'Monos device having buried metal silicide bit line'20046,818,557'Method of forming SiC capped copper interconnects with reduced hillock formation and improved electromigration resistance'20046,809,402'Reflowable-doped HDP film'20046,809,043'Multi-stage, low deposition rate PECVD oxide'20046,806,165'Isolation trench fill process'20046,803,265'Liner for semiconductor memories and manufacturing method therefor'20046,803,267'Silicon containing material for patterning polymeric memory element'20046,797,614'Nickel alloy for SMOS process silicidation'20046,797,652'Copper damascene with low-k capping layer and improved electromigration reliability'20046,787,864'Mosfets incorporating nickel germanosilicided gate and methods for their formation'20046,787,458'Polymer memory device formed in via opening'20046,784,095'Phosphine treatment of low dielectric constant materials in semiconductor device manufacturing'20046,773,954'Methods of forming passive layers in organic memory cells'20046,774,432'UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL'20046,770,905'Implantation for the formation of CuX layer in an organic memory device'20046,770,523'Method for semiconductor wafer planarization by CMP stop layer formation'20046,765,254'Structure and method for preventing UV radiation damage and increasing data retention in memory cells'20046,764,898'Implantation into high-K dielectric material after gate etch to facilitate removal'20046,764,966'Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric'20046,762,454'Stacked polysilicon layer for boron penetration inhibition'20046,746,971'Method of forming copper sulfide for memory cell'20046,743,310'Method of forming nitride capped Cu lines with improved adhesion and reduced electromigration along the Cu/nitride interface'20046,730,587'Titanium barrier for nickel silicidation of a gate electrode'20046,731,006'Doped copper interconnects using laser thermal annealing'20046,730,576'Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer'20046,727,560'Engineered metal gate electrode'20046,727,176'Method of forming reliable Cu interconnects'20046,724,051'Nickel silicide process using non-reactive spacer'20046,723,634'Method of forming interconnects with improved barrier layer adhesion'20046,723,635'Protection low-k ILD during damascene processing with thin liner'20046,720,225'Reactive pre-clean using reducing gas during nickel silicide process'20046,713,874'Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-layer dielectrics'20046,713,392'Nitrogen oxide plasma treatment for reduced nickel silicide bridging'20046,706,576'Laser thermal annealing of silicon nitride for increased density and etch selectivity'20046,693,004'Interfacial barrier layer in semiconductor devices with high-K gate dielectric material'20046,686,232'Ultra low deposition rate PECVD silicon nitride'20046,686,263'Selective formation of top memory electrode by electroless formation of conductive materials'20046,674,170'Barrier metal oxide interconnect cap in integrated circuits'20046,673,696'Post trench fill oxidation process for strained silicon processes'20046,670,241'Semiconductor memory with deuterated materials'20036,664,187'Laser thermal annealing for Cu seedlayer enhancement'20036,660,634'Method of forming reliable capped copper interconnects'20036,660,621'Method of forming ultra-shallow junctions in a semiconductor wafer with silicon layer deposited from a gas precursor to reduce silicon consumption during salicidation'20036,661,067'Nitrogen-plasma treatment for reduced nickel silicide bridging'20036,656,763'Spin on polymers for organic memory devices'20036,657,304'Conformal barrier liner in an integrated circuit interconnect'20036,653,190'Flash memory with controlled wordline width'20036,645,882'Preparation of composite high-K/standard-K dielectrics for semiconductor devices'20036,645,853'Interconnects with improved barrier layer adhesion'20036,642,619'System and method for adhesion improvement at an interface between fluorine doped silicon oxide and tantalum'20036,642,145'Method of manufacturing an integrated circuit with a dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers'20036,638,861'Method of eliminating voids in W plugs'20036,627,973'Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory semiconductor device'20036,617,215'Memory wordline hard mask'20036,613,657'BPSG, SA-CVD liner/P-HDP gap fill'20036,605,848'Semiconductor device with metal gate electrode and silicon oxynitride spacer'20036,605,513'Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing'20036,602,754'Nitrogen implant into nitride spacer to reduce nickel silicide formation on spacer'20036,599,766'Method for determining an anti reflective coating thickness for patterning a thin film semiconductor layer'20036,599,827'Methods of forming capped copper interconnects with improved electromigration resistance'20036,596,631'Method of forming copper interconnect capping layers with improved interface and adhesion'20036,593,237'Method for manufacturing a low dielectric constant stop layer for integrated circuit interconnects'20036,593,632'Interconnect methodology employing a low dielectric constant etch stop layer'20036,586,333'Integrated plasma treatment and nickel deposition and tool for performing same'20036,583,051'Method of manufacturing an amorphized barrier layer for integrated circuit interconnects'20036,576,545'Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-layer dielectrics and method of forming capping/ARC layers'20036,577,009'Use of sic for preventing copper contamination of dielectric layer'20036,576,548'Method of manufacturing a semiconductor device with reliable contacts/vias'20036,576,982'Use of sion for preventing copper contamination of dielectric layer'20036,573,172'Methods for improving carrier mobility of PMOS and NMOS devices'20036,569,768'Surface treatment and capping layer process for producing a copper interface in a semiconductor device'20036,566,283'Silane treatment of low dielectric constant materials in semiconductor device manufacturing'20036,566,252'Method for simultaneous deposition and sputtering of TEOS and device thereby formed'20036,563,183'Gate array with multiple dielectric properties and method for forming same'20036,562,416'Method of forming low resistance vias'20036,562,718'Process for forming fully silicided gates'20036,555,461'Method of forming low resistance barrier on low k interconnect'20036,548,403'Silicon oxide liner for reduced nickel silicide bridging'20036,545,370'Composite silicon nitride sidewall spacers for reduced nickel silicide bridging'20036,541,866'Cobalt barrier for nickel silicidation of a gate electrode'20036,534,869'Method for reducing stress-induced voids for 0.25 m micron and smaller semiconductor chip technology by annealing interconnect lines prior to ILD deposition and semiconductor chip made thereby'20036,528,432'H2-or H2/N2-plasma treatment to prevent organic ILD degradation'20036,528,884'Conformal atomic liner layer in an integrated circuit interconnect'20036,525,428'Graded low-k middle-etch stop layer for dual-inlaid patterning'20036,525,391'Nickel silicide process using starved silicon diffusion barrier'20036,521,529'HDP treatment for reduced nickel silicide bridging'20036,515,367'Sub-cap and method of manufacture therefor in integrated circuit capping layers'20036,509,282'Silicon-starved PECVD method for metal gate electrode dielectric spacer'20036,506,677'Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance'20036,507,123'Nickel silicide process using UDOX to prevent silicide shorting'20036,504,251'Heat/cold amorphized barrier layer for integrated circuit interconnects'20036,501,177'Atomic layer barrier layer for integrated circuit interconnects'20026,495,460'Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface'20026,492,266'Method of forming reliable capped copper interconnects'20026,489,253'Method of forming a void-free interlayer dielectric (ILD0) for 0.18-m flash memory technology and semiconductor device thereby formed'20026,483,154'Nitrogen oxide plasma treatment for reduced nickel silicide bridging'20026,482,755'HDP deposition hillock suppression method in integrated circuits'20026,483,153'Method to improve LDD corner control with an in-situ film for local interconnect processing'20026,479,348'Method of making memory wordline hard mask extension'20026,479,898'Dielectric treatment in integrated circuit interconnects'20026,475,847'Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer'20026,472,755'Semiconductor device comprising copper interconnects with reduced in-line copper diffusion'20026,469,385'Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers'20026,468,900'Dual layer nickel deposition using a cobalt barrier to reduce surface roughness at silicide/junction interface'20026,465,349'Nitrogen-plasma treatment for reduced nickel silicide bridging'20026,462,417'Coherent alloy diffusion barrier for integrated circuit interconnects'20026,459,155'Damascene processing employing low Si-SiON etch stop layer/arc'20026,455,422'Densification process hillock suppression method in integrated circuits'20026,451,647'Integrated plasma etch of gate and gate dielectric and low power plasma post gate etch removal of high-K residual'20026,445,070'Coherent carbide diffusion barrier for integrated circuit interconnects'20026,444,593'Surface treatment of low-K SiOF to prevent metal interaction'20026,441,490'Low dielectric constant stop layer for integrated circuit interconnects'20026,436,808'NH3/N2-plasma treatment to prevent organic ILD degradation'20026,432,822'Method of improving electromigration resistance of capped Cu'20026,432,817'Tungsten silicide barrier for nickel silicidation of a gate electrode'20026,432,805'Co-deposition of nitrogen and metal for metal silicide formation'20026,429,128'Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface'20026,420,752'Semiconductor device with self-aligned contacts using a liner oxide layer'20026,417,100'Annealing ambient in integrated circuit interconnects'20026,410,461'Method of depositing sion with reduced defects'20026,403,474'Controlled anneal conductors for integrated circuit interconnects'20026,399,480'Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction'20026,395,644'Process for fabricating a semiconductor device using a silicon-rich silicon nitride ARC'20026,387,767'Nitrogen-rich silicon nitride sidewall spacer deposition'20026,388,330'Low dielectric constant etch stop layers in integrated circuit interconnects'20026,383,880'NH3/N2-plasma treatment for reduced nickel silicide bridging'20026,383,925'Method of improving adhesion of capping layers to cooper interconnects'20026,383,950'Insulating and capping structure with preservation of the low dielectric constant of the insulating layer'20026,380,067'Method for creating partially UV transparent anti-reflective coating for semiconductors'20026,380,588'Semiconductor device having uniform spacers'20026,376,389'Method for eliminating anti-reflective coating in semiconductors'20026,372,673'Silicon-starved nitride spacer deposition'20026,368,948'Method of forming capped copper interconnects with reduced hillocks'20026,348,410'Low temperature hillock suppression method in integrated circuit interconnects'20026,348,732'Amorphized barrier layer for integrated circuit interconnects'20026,348,406'Method for using a low dielectric constant layer as a semiconductor anti-reflective coating'20026,335,283'Method of reducing in-line copper diffusion'20026,333,218'Method of etching contacts with reduced oxide stress'20016,333,263'Method of reducing stress corrosion induced voiding of patterned metal layers'20016,329,701'Semiconductor device comprising copper interconnects with reduced in-line diffusion'20016,326,692'Insulating and capping structure with preservation of the low dielectric constant of the insulating layer'20016,323,135'Method of forming reliable capped copper interconnects/with high etch selectivity to capping layer'20016,303,505'Copper interconnect with improved electromigration resistance'20016,294,460'Semiconductor manufacturing method using a high extinction coefficient dielectric photomask'20016,291,296'Method for removing anti-reflective coating layer using plasma etch process before contact CMP'20016,281,584'Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces'20016,261,952'Method of forming copper interconnects with reduced in-line diffusion'20016,258,697'Method of etching contacts with reduced oxide stress'20016,251,776'Plasma treatment to reduce stress corrosion induced voiding of patterned metal layers'20016,242,367'Method of forming silicon nitride films'20016,235,654'Process for forming PECVD nitride with a very low deposition rate'20016,235,632'Tungsten plug formation'20016,236,091'Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide'20016,228,761'Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide'20016,225,216'Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide'20016,225,210'High density capping layers with improved adhesion to copper interconnects'20016,221,794'Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines'20016,221,793'Process for forming PECVD undoped oxide with a super low deposition rate on a single state deposition'20016,214,731'Copper metalization with improved electromigration resistance'20016,211,084'Method of forming reliable copper interconnects'20016,204,136'Post-spacer etch surface treatment for improved silicide formation'20016,201,303'Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide'20016,190,966'Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration'20016,174,743'Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines'20016,171,947'Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines'20016,171,919'MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation'20016,165,894'Method of reliably capping copper interconnects'20006,153,933'Elimination of residual materials in a multiple-layer interconnect structure'20006,150,285'Method for simultaneous deposition and sputtering of TEOS'20006,146,988'Method of making a semiconductor device comprising copper interconnects with reduced in-line copper diffusion'20006,143,672'Method of reducing metal voidings in 0.25 .mu.m AL interconnect'20006,140,255'Method for depositing silicon nitride using low temperatures'20006,136,649'Method for removing anti-reflective coating layer using plasma etch process after contact CMP'20006,137,126'Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer'20006,127,261'Method of fabricating an integrated circuit including a tri-layer pre-metal interlayer dielectric compatible with advanced CMOS technologies'20006,124,217'In-situ SiON deposition/bake/TEOS deposition process for reduction of defects in interlevel dielectric for integrated circuit interconnects'20006,121,663'Local interconnects for improved alignment tolerance and size reduction'20006,117,799'Deposition of super thin PECVD SiO.sub.2 in multiple deposition station system'20006,114,224'System and method for using N.sub.2 O plasma treatment to eliminate defects at an interface between a stop layer and an integral layered dielectric'20006,114,235'Multipurpose cap layer dielectric'20006,103,611'Methods and arrangements for improved spacer formation within a semiconductor device'20006,096,661'Method for depositing silicon dioxide using low temperatures'20006,096,662'NH.sub.3 /N.sub.2 plasma treatment to enhance the adhesion of silicon nitride to thermal oxide'20006,093,973'Hard mask for metal patterning'20006,087,275'Reduction of n-channel parasitic transistor leakage by using low power/low pressure phosphosilicate glass'20006,087,271'Methods for removal of an anti-reflective coating following a resist protect etching process'20006,066,567'Methods for in-situ removal of an anti-reflective coating during an oxide resistor protect etching process'20006,060,404'In-situ deposition of stop layer and dielectric layer during formation of local interconnects'20006,060,393'Deposition control of stop layer and dielectric layer for use in the formation of local interconnects'20006,054,735'Very thin PECVD SiO.sub.2 in 0.5 micron and 0.35 micron technologies'20006,051,870'Process for fabricating semiconductor device including improved phosphorous-doped silicon dioxide dielectric film'20006,033,584'Process for reducing copper oxide during integrated circuit fabrication'20006,027,959'Methods for in-situ removal of an anti-reflective coating during a nitride resistor protect etching process'20006,022,799'Methods for making a semiconductor device with improved hot carrier lifetime'20006,020,274'Method and system for using N.sub.2 plasma treatment to eliminate the outgassing defects at the interface of a stop layer and an oxide layer'20005,990,524'Silicon oxime spacer for preventing over-etching during local interconnect formation'19995,989,957'Process for fabricating semiconductor memory device with high data retention including silicon oxynitride etch stop layer formed at high temperature with low hydrogen ion concentration'19995,986,329'Deposition of super thin PECVD SiO.sub.2 in multiple deposition station system'19995,895,269'Methods for preventing deleterious punch-through during local interconnect formation'19995,888,911'HSQ processing for reduced dielectric constant'19995,888,898'HSQ baking for reduced dielectric constant'19995,736,423'Method for depositing very thin PECVD SiO.sub.2 in 0.5 micron and 0.35 micron technologies'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2013Patents assigned to ADVANCED MICRO DEVICES INC (258)· patent assignee history
1998–2005Based in Union City, CA, US· patent location history
2000–2021Based in Fremont, CA, US· patent location history
2002–2013Based in Freemont, CA, US· patent location history
2004–2014Patents assigned to SPANSION LLC (34)· patent assignee history
2010–2015Patents assigned to GLOBALFOUNDRIES INC (5)· patent assignee history
2012–2015Patents assigned to NGO MINH VAN (8)· patent assignee history
2015–2021Patents assigned to CYPRESS SEMICONDUCTOR CORP (5)· patent assignee history
2017Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 258 | 1998–2013 |
| SPANSION LLC | 34 | 2004–2014 |
| NGO MINH VANself | 8 | 2012–2015 |
| CYPRESS SEMICONDUCTOR CORP | 5 | 2015–2021 |
| GLOBALFOUNDRIES INC | 5 | 2010–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 235 | 2000–2021 |
| Union City, California, US | 56 | 1998–2005 |
| Freemont, California, US | 5 | 2002–2013 |
| San Jose, California, US | 3 | 2017 |