High performance CMOS devices and methods for making same

This application is a division of U.S. application Ser. No. 10/999,724, filed Nov. 30, 2004. The entire disclosure of U.S. application Ser. No. 10/999,724 is incorporated herein by reference.

The present invention relates to integrated circuits and high performance complementary metal oxide semiconductor (CMOS) devices and more particularly, to integrated circuits having high performance CMOS devices with good short channel effects, low parasitic junction capacitances, and low junction leakage currents and methods for making same.

High performance CMOS devices should have, among other characteristics, good short channel behavior, low parasitic junction capacitances and low junction leakage currents. However, as the size of integrated circuits (ICs) continues to shrink and the number of high performance CMOS devices on IC chips continue to increase, the dimensions of the CMOS devices must be scaled down. The scaling down of CMOS devices makes it difficult to achieve good short channel effects, low parasitic junction capacitances and low junction leakage currents.

Accordingly, methods are needed for manufacturing smaller ICs with scaled down high performance CMOS devices.

Integrated circuits having high performance CMOS devices with good short channel effects, low parasitic junction capacitances, and low junction leakage currents and methods for making same are disclosed. One of the methods comprises the steps of: forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; and thermal annealing the substrate when forming the spacers, the thermal annealing performed at an ultra-low temperature.

Another one of the methods comprises the steps of: forming a gate structure over a substrate; forming source/drain extensions in the substrate; and performing a thermal cycle process for solid phase epitaxy on the substrate.

Still another one of the methods comprises the steps of: forming a gate structure over a substrate; forming pocket implant regions in the substrate; forming thin, off-set spacers along sides of the gate structure; and forming source/drain extensions in the substrate.

A further one of the methods comprises the steps of: forming a gate structure over a substrate; forming pocket implant regions and source/drain extensions in the substrate; forming spacers along sides of the gate structure; performing a low dosage source/drain implant; and performing a high dosage source/drain implant.

One of the integrated circuits comprises: a gate structure over a substrate; pocket implant regions and source/drain extensions in the substrate; and spacers disposed along sides of the gate structure, the spacers formed while thermal annealing the substrate at an ultra-low temperature.

Another one of the integrated circuits comprises: a gate structure over a substrate; pocket implant regions and source/drain extensions in the substrate; graded source/drain regions in the substrate, the graded source/drain regions formed by a low dosage source/drain implant and a high dosage source/drain implant.

Still another one of the integrated circuits comprises: a gate structure over a substrate; a super halo-shape pocket implant region in the substrate; thin, off-set spacers disposed along sides of the gate structure; and source/drain extensions in the substrate.

FIGS. 1A-1E are sectional views illustrating a method of fabricating a scaled down transistor of a high performance CMOS device according to the present invention.

FIGS. 2A-2C are sectional views illustrating an alternate method of fabricating a scaled down transistor of a high performance CMOS device according to the present invention.

FIGS. 3A-3C are sectional views illustrating an alternate method of fabricating a scaled down transistor of a high performance CMOS device according to the present invention.

FIGS. 4A-4D are sectional views illustrating still another method of fabricating a scaled down transistor of a high performance CMOS device according to the present invention.

FIGS. 5A-5E are sectional views illustrating yet another method of fabricating a scaled down transistor of a high performance CMOS device according to the present invention.

FIGS. 1A-1E are sectional views illustrating a method of fabricating a scaled down transistor 100 (e.g. PMOS or NMOS) of a high performance CMOS device according to the present invention. As illustrated in FIG. 1A , the method commences with the formation of a gate structure 130 over a substrate 120 . The substrate 120 is not limited to a particular type and may be include, without limitation, an element semiconductor, such as Si and Ge, or a compound semiconductor, such as GaAs, InGaAs and ZnSe. The gate structure 130 may include a gate oxide 132 , such as SiO 2 , disposed over the substrate 120 and a gate conductor 134 , such as poly-Si, poly SiGe, a metal, a metal oxide, a metal nitride, a silicide and combinations thereof, disposed over the gate oxide 132 . The gate structure 130 may be formed using conventional methods well known in the art.

As illustrated in FIG. 1B , a self-aligning pocket ion implantation process is performed to form self-aligned first and second pocket implant regions 140 a , 140 b in the substrate 120 at opposite ends of channel region 122 . The pocket implantation process may be performed with an ion beam tilt-angle (as shown) or without an ion beam tilt-angle. When tilt-ion implantation is used, the ion beam tilt-angle may up to about 50 degrees. The pocket implantation process is performed with a implant current (dosage) that is typically less than 2E15 cm−2 and an implant voltage (energy) that is typically less than 200 kev. The dopant used may include, for example, As, P, BF 2 , In Sb, and B.

As illustrated in FIG. 1C , a self-aligning source/drain extension ion implantation process is performed to form shallow source/drain extensions 150 a , 150 b in the substrate 120 . The shallow source/drain extensions 150 a , 150 b may extend partially beneath the gate oxide 132 and above the pocket implant regions 140 a , 140 b . The source/drain extension implantation process may be performed with or without an ion beam tilt-angle. When tilt-ion implantation is used, the ion beam tilt-angle may be up to about 50 degrees. The source/drain extension implantation process is performed with an implant dosage that is typically less than 2E16 cm−2 and an implant energy that is typically less than 200 kev. The dopant used may include, for example, As, P, BF 2 , In, Sb, and B.

As illustrated in FIG. 1D , an ultra low temperature thermal cycle spacer deposition (UL-DT spacer) process is performed to form first and second non-conductive spacers 160 a , 160 b along opposing side walls of the gate structure 130 . The spacers 160 a , 160 b may be formed as single or multilayer structure. The single layer spacers may be composed, for example, of an oxide layer or a nitride layer. Multilayer spacers may be a composite composed for example, of an oxide layer and a nitride layer or a first oxide layer, a nitride layer, and a second oxide layer. The layer or layers of the spacers may be formed using low pressure chemical vapor deposition and dry plasma etching. In one embodiment, the UL-DT spacer process is performed by thermal annealing the substrate 120 using an ultra-low temperature cycle to activate the dopants forming the pocket implant regions 140 a , 140 b and source/drain extensions 150 a , 150 b and then performing a conventional spacer deposition process. The thermal annealing may be performed using RTA or a furnace anneal at an ultra-low temperature between about 350° C. and about 800° C., for a time period ranging between about 5 seconds and about 700 minutes.

In an alternative embodiment, the UL-DT spacer process is performed in a single step, i.e., during spacer deposition, which operates to thermally anneal the substrate 120 at an ultra-low temperature between about 350° C. and about 800° C., for a time period ranging between about 5 seconds and about 700 minutes.

As illustrated in FIG. 1E , the transistor 100 may be completed by forming self-aligned source/drain regions 170 a , 170 b in the substrate 120 which contact the source/drain extensions 150 a , 150 b , and forming conductive silicide films 180 a , 180 b , 180 c over the gate conductor 134 and the source/drain regions 170 a , 170 b . The source/drain regions 170 a , 170 b may be formed using conventional source/drain implantation and anneal processes. The silicide films 180 a , 180 b , 180 c may be formed using a conventional silicidation process.

FIGS. 2A-2C are sectional views illustrating an alternate method of fabricating a scaled down transistor 200 (e.g. PMOS or NMOS) of a high performance CMOS device according to the present invention. The method starts with a substrate 220 similar to the one described above with reference to FIG. 1A . Then, as illustrated in FIG. 2A , a self-aligning pocket ion implantation process is performed to form regions 240 a , 240 b in the substrate 220 . The pocket implantation process may be performed in the same manner as described earlier, i.e., with an ion beam tilt angle that may be up to 50 degrees or without an ion beam tilt-angle. The pocket implantation process is performed with an implant dosage that is typically less than 2E15 cm−2 and an implant energy that is typically less than 200 kev. The dopant used may include, for example, As, P, BF 2 , In, Sb, and B.

A self-aligning source/drain extension ion implantation process is performed, as illustrated in FIG. 2B , to form shallow source/drain extensions 250 a , 250 b in the substrate 220 . The source/drain extension implantation process may be performed with a beam tilt angle up to about 50 degrees or without an ion beam tilt-angle. The source/drain extension implantation process is performed with an implant dosage that is typically less than 2E16 cm−2 and an implant energy that is typically less than 200 kev. The dopant used may include, for example, As, P, BF 2 , In Sb, and B. A thermal anneal is then performed to activate the dopants forming the pocket implant regions 240 a , 240 b.

The substrate is then subjected to a low temperature thermal cycle process for solid phase epitaxy. The low temperature thermal cycle process activates the dopants forming the source/drain extensions 250 a , 250 b . The thermal anneal may be performed using RTA or a furnace anneal at an ultra-low temperature between about 350° C. and 800° C. for a time period ranging between about 5 seconds and about 700 minutes.

As illustrated in FIG. 2C , the transistor 200 may be completed by forming first and second non-conductive spacers 260 a , 260 b along opposing side walls of the gate structure 230 , self-aligned first and second source/drain regions 270 a , 270 b in the substrate 220 which contact the source/drain extensions 250 a , 250 b , and forming conductive silicide films 280 a , 280 b , 280 c over the gate conductor 234 and the source/drain regions 270 a , 270 b . The spacers 260 a , 260 b may be formed as single or multilayer structure using a conventional spacer forming method. The source/drain regions 270 a , 270 b may be formed using conventional source/drain implantation and anneal processes. The silicide films 280 a , 280 b , 280 c may be formed using a conventional silicidation process.

FIGS. 3A-3C are sectional views illustrating an alternate method of fabricating the scaled down transistor 200 of FIG. 2C . The method starts with a substrate 320 similar to the one described above with reference to FIG. 1A . Then, as illustrated in FIG. 3A , a self-aligning pocket ion implantation process is performed to form pocket implant regions 340 a , 340 b in the substrate 320 . The pocket implantation process may be performed in the same manner as described earlier, i.e., with an ion beam tilt angle that may be up to 50 degrees or without an ion beam tilt-angle. The pocket implantation process is performed with an implant dosage that is typically less than 2E15 cm−2 and an implant energy that is typically less than 200 kev. The dopant used may include, for example, As, P, BF 2 , In, Sb, and B.

A thermal anneal is then performed on the substrate 320 . The temperature thermal anneal is performed at a range of about 700° C. to about 1050° C., for a time period of about 0 seconds to about 60 seconds to activate the pocket dopant.

A self-aligning source/drain extension ion implantation process is performed, as illustrated in FIG. 3B , to form shallow source/drain extensions 350 a , 350 b in the substrate 320 . The source/drain extension implantation process may be performed with a beam tilt angle up to about 50 degrees or without an ion beam tilt-angle. The source/drain extension implantation process is performed with an implant dosage that is typically less than 2E16 cm−2 and an implant energy that is typically less than 200 kev. The dopant used may include, for example, As, P, BF 2 , In Sb, and B.

The substrate 320 is then subjected to a low temperature thermal cycle process for solid phase epitaxy. The low temperature thermal cycle process activates the dopants forming the source/drain extensions 350 a , 350 b . The thermal anneal is performed at an ultra-low temperature between about 350° C. and 800° C., for a time period of between about 5 seconds to about 700 minutes.

As illustrated in FIG. 3C , the transistor 300 may be completed by forming first and second non-conductive spacers 360 a , 360 b along opposing side walls of the gate structure 330 , self-aligned first and second source/drain regions 370 a , 370 b in the substrate 320 which contact the source/drain extensions 350 a , 350 b , and forming conductive silicide films 380 a , 380 b , 380 c over the gate conductor 334 and the source/drain regions 370 a , 370 b . The spacers 360 a , 360 b may be formed as single or multilayer structure using a conventional spacer forming method. The source/drain regions 370 a , 370 b may be formed using conventional source/drain implantation and anneal processes. The silicide films 380 a , 380 b , 380 c may be formed using a conventional silicidation process.

FIGS. 4A-4D are sectional views illustrating still another method of fabricating a scaled down transistor 400 (e.g. PMOS or NMOS) of a high performance CMOS device according to the present invention. The method starts with a substrate 420 similar to the one described above with reference to FIG. 1A . Then, as illustrated in FIG. 4A , a self-aligning super-halo pocket ion implantation process is performed to form a self-aligned super-halo shape pocket implant region 440 in the substrate 420 , below the channel region 422 . The super halo pocket ion implantation process may include a first step performed with a high implantation energy at a beam tilt angle of less than 20 degrees and a second step performed with a low implantation energy at a beam tilt angle of less than 40 degrees. The high implantation energy used in the first step is typically in the range of about 15 Kev to about 200 Kev with an implant dosage ranging between about 1E13 to about 5E14. The low implantation energy used in the second step is typically in the range of about 5 Kev to about 100 Kev with an implant dosage ranging between about 5E12 to about 3E14. The dopant used may include, for example, As, P, BF 2 , In Sb, and B. This process confines the profile of the pocket region 440 to the bottom of the channel region 422 .

First and second non-conductive offset, thin-width spacers 462 a , 462 b are then formed along opposing side walls of the gate structure 430 , as illustrated in FIG. 4B using a low temperature thermal cycle spacer deposition process. The thin width offset spacers 462 a , 462 b may be formed as single or multilayer structure and may have a width ranging between about 10 angstroms and 300 angstroms. Single layer spacers may be composed, for example, of an oxide layer or a nitride layer and multilayer spacers may be a composite composed for example, of an oxide layer and a nitride layer or a first oxide layer, a nitride layer, and a second oxide layer. The layer or layers of the spacers 462 a , 462 b may be formed using low pressure chemical vapor deposition and dry plasma etching. The temperature for performing both the deposition and the etching processes may range between about 600° C. and about 700° C. The time for depositing all the layers of the spacers may be less than 2 hours.

After offset spacer process, a self-aligning source/drain extension ion implantation process is performed, as illustrated in FIG. 4C , to form self-aligned shallow source/drain extensions 450 a , 450 b in the substrate 420 . The source/drain extension implantation process may be performed with without an ion beam tilt-angle, and preferably with a beam tilt angle up to about 50 degrees. An ultra-shallow junction may be achieved by using a beam tilt angle at the high end of the above beam tilt angle range. The source/drain extension implantation process is performed with an implant dosage that is typically less than 2E16 cm−2 and an implant energy that is typically less than 200 kev. The dopant used may include, for example, As, P, BF 2 , In Sb, and B.

As illustrated in FIG. 4D , the transistor 400 may be completed by forming first and second non-conductive spacers 460 a , 460 b along opposing side walls of the gate structure 430 , self-aligned first and second source/drain regions 470 a , 470 b in the substrate 420 which contact the source/drain extensions 450 a , 450 b , and forming conductive silicide films 480 a , 480 b , 480 c over the gate conductor 434 and the source/drain regions 270 a , 270 b . The spacers 460 a , 460 b may be formed as single or multilayer structure using a conventional spacer forming method. The source/drain regions 470 a , 470 b may be formed using conventional source/drain implantation and anneal processes. The silicide films 480 a , 480 b , 480 c may be formed using a conventional silicidation process.

CMOS devices fabricated in accordance with the above methods exhibit improved short channel effects and low leakage currents. More specifically, the shallow and lightly doped source/drain extensions minimize the short channel behavior as the CMOS devices are scaled down. In addition, the implant pocket region or regions reduce the leakage current of the CMOS device.

FIGS. 5A-5E are sectional views illustrating yet another method of fabricating a scaled down transistor 500 (e.g. PMOS or NMOS) of a high performance CMOS device according to the present invention. The method starts with a substrate 520 similar to the one described above with reference to FIG. 1A . Then, as illustrated in FIG. 5A , a self-aligning pocket ion implantation process is performed. The pocket ion implantation process forms regions 540 a , 540 b in the substrate 520 at the opposite ends of channel region 522 . The pocket ion implantation process may be performed in the same manner as described earlier, i.e., with an ion beam tilt angle that may be up to 50 degrees or without an ion beam tilt-angle. The pocket implantation is performed with an implant dosage that is typically less than 2E15 cm−2 and an implant energy that is typically less than 200 kev. The dopant used may include, for example, As, P, BF 2 , In Sb, and B.

As illustrated in FIG. 5B , a self-aligning source/drain extension ion implantation process is performed, which forms self-aligned shallow source/drain extensions 550 a , 550 b in the substrate 520 . The source/drain extension implantation process may be performed with a beam tilt angle up to about 50 degrees or without an ion beam tilt-angle. The source/drain extension implantation is performed with an implant dosage that is typically less than 2E16 cm−2 and an implant energy that is typically less than 200 kev. The dopant used may include, for example, As, P, BF 2 , In Sb, and B.

First and second non-conductive spacers 560 a , 560 b are then formed along opposing side walls of the gate structure 530 as illustrated in FIG. 5C . The spacers 560 a , 560 b may be formed as single or multilayer structure using, for example, a conventional spacer forming method.

As illustrated in FIG. 5D , first and second source/drain regions 570 a , 570 b are formed in the substrate 520 using a “smart” grading source/drain implantation process. The smart grading implantation process comprises a high-energy, low-dose source/drain implant followed by a high-dose source/drain implant.

The high-energy, low-dose source/drain implant may be performed with a beam tilt angle up to about 50 degrees. The implant energy is typically less than 150 kev and the implant dosage is typically less than 1E15 cm−2. The dopant used may include, for example, As, P, BF 2 , In Sb, and B.

The high-dose source/drain implant may be performed with a beam tilt angle up to about 50 degrees. The implant energy is typically greater than 1 kev and the implant dosage is typically greater than 1E14 cm−2. The dopant used may include, for example, As, P, BF 2 , In Sb, and B.

After completion of the smart grading source/drain implantation process, a silicidation process may be performed to form conductive silicide films 580 a , 580 b , 580 c over the gate conductor 534 and source/drain regions 570 a , 570 b , as illustrated in FIG. 5E . CMOS devices fabricated using the smart grading source/drain implantation process exhibit improved short channel effects and low leakage currents.

While the foregoing invention has been described with reference to the above, various modifications and changes can be made without departing from the spirit of the invention. Accordingly, all such modifications and changes are considered to be within the scope of the appended claims.