Dual-sided chip attached modules

This Application is a division of U.S. patent application Ser. No. 11/383,595 filed on May 15, 2006 now U.S. Pat. No. 7,462,509.

The present invention relates to the field of integrated circuits; more specifically, it relates dual-sided chip attached modules.

As semiconductor devices such as field effect and bipolar transistors become smaller and more densely packed, it becomes increasingly difficult to provide enough wiring levels to fully utilized the potential that such small devices offer as wiring dimensions do not shrink in scale with device dimensions and there is topographical interference between wiring levels. Therefore, there is a need to provide integrated circuit devices with increased wiring capability.

A first aspect of the present invention is an electronic device, comprising: a first substrate having a first set of electrically conductive substrate pads on a first surface of the first substrate, a second set of electrically conductive substrate pads on a second surface of the first substrate, and a plurality of electrically conductive wires connecting substrate pads of the first set of substrate pads to corresponding substrate pads of the second set of substrate pads; a second substrate having a third set of electrically conductive substrate pads on a first surface of the second substrate, a plurality of electrically conductive wires in the second substrate interconnecting combinations of substrate pads of the third set of substrate pads; and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads of the first set of substrate pads, and chip pads of the second set of chip pads physically and electrically connected to corresponding substrate pads of the third set of substrate pads.

A second aspect of the present invention is the first aspect, further including: a first set of solder bumps physically and electrically connecting the chip pads of the first set of chip pads to the corresponding substrate pads of the first set of substrate pads; and a second set of solder bumps physically and electrically connecting the chip pads of the second set of chip pads to the corresponding substrate pads of the third set of substrate pads.

A third aspect of the present invention is the first aspect, further including: a set of solder bumps physically and electrically connecting the chip pads of the first set of chip pads to the corresponding pads of the first set of substrate pads; and a set of wire bonds physically and electrically connecting the chip pads of the second set of chip pads to the corresponding substrate pads of the third set of substrate pads.

A fourth aspect of the present invention is the first aspect, further including: a heatsink physically attached to a second surface of the second substrate, the second surface of the substrate opposite from the first surface of the second substrate.

A fifth aspect of the present invention is the first aspect, wherein the first surface and the second surface of the first substrate are opposite each other.

A sixth aspect of the present invention is the first aspect, wherein the first surface and the second surface of the first substrate share a common edge and are essentially perpendicular to each other.

A seventh aspect of the present invention is the first aspect, wherein the first substrate is a single or multilevel ceramic substrate, a single or multilevel organic substrate, a fiberglass substrate, a printed circuit board or a tape automated bonding substrate, and wherein the second substrate is a single or multilevel ceramic substrate, a single or multilevel organic substrate, a fiberglass substrate, a printed circuit board or a tape automated bonding substrate.

An eighth aspect of the present invention is the first aspect, further including: an additional integrated circuit chip having a first side and an opposite second side, an additional first set of chip pads on the first side and an additional second set of chip pads on the second side of the additional integrated circuit chip, chip pads of the additional first set of chip pads physically and electrically connected to corresponding substrate pads of the first set of substrate pads, and chip pads of the additional second set of chip pads physically and electrically connected to corresponding substrate pads of the second set of substrate pads

A ninth aspect of the present invention is the eighth aspect, wherein, one or more of the wires of the second substrate electrically connect selected chip pads of the second set of chips pads of the integrated circuit chip to selected chip pads of the additional second set of chips pads of the additional integrated circuit chip.

A tenth aspect of the present invention is the first aspect, the integrated circuit chip comprising: one or more devices in a silicon-on-insulator substrate, the silicon-on-insulator substrate comprising a silicon layer on a top surface of an oxide layer and a pre-metal dielectric layer on a top surface of the silicon layer; one or more first wiring levels on a top surface of the pre-metal dielectric layer, each wiring level of the first wiring levels comprising electrically conductive wires in a corresponding dielectric layer; electrically conductive first contacts to the devices, one or more of the first contacts extending from the top surface of the pre-metal dielectric layer to the devices, one or more wires of a lowermost wiring level of the first wiring levels in physical and electrical contact with the first contacts; electrically conductive second contacts to the devices, one or more of the second contacts extending from the bottom surface of the oxide layer to the devices; and one or more second wiring levels over a bottom surface of the oxide layer, each wiring level of the second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of the second wiring levels in physical and electrical contact with the second contacts.

An eleventh aspect of the present invention is the first aspect, the integrated circuit chip comprising: one or more first devices of a first silicon-on-insulator substrate, the first silicon-on-insulator substrate comprising a first oxide layer, a first silicon layer on the first oxide layer and a first lowermost dielectric layer on the first silicon layer; one or more second devices of a second silicon-on-insulator substrate, the second silicon-on-insulator substrate comprising a second oxide layer, a second silicon layer on the second oxide layer and a second lowermost dielectric layer on the second silicon layer; a top surface of the first oxide layer bonded to a top surface of the second oxide layer; electrically conductive first contacts to the second devices, the first contacts extending from a top surface of the second lowermost dielectric layer through the second lowermost dielectric layer to the first devices; electrically conductive second contacts to the first devices, the second contacts extending from the top surface of the second lowermost dielectric layer through the second lowermost dielectric layer, through the first and second oxide layers to those portions of the second devices formed in the second silicon layer; and one or more second wiring levels over the second lowermost dielectric layer, each wiring level of the second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of the second wiring levels in physical and electrical contact with the first and second contacts.

The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1A is a cross-sectional view of a single chip module FIGS. 1B , 1 C, 1 D and 1 E are cross-sectional views of multi-chip modules according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of the wiring levels of an exemplary module substrate according to the embodiments of the present invention;

FIG. 3A is a cross-sectional view of a single chip module and FIG. 3B is a cross-sectional view of a multi-chip module according to a second embodiment of the present invention;

FIG. 4A is a cross-sectional view of a single chip module and FIGS. 4B and 4C are cross-sectional views of multi-chip modules according to a third embodiment of the present invention;

FIG. 5A is a cross-sectional view of a single chip module and FIGS. 5B and 5C are cross-sectional views of multi-chip modules according to a fourth embodiment of the present invention;

FIG. 6 is a cross-sectional view of an exemplary first type of dual-sided integrated circuit chip suitable for use with any of the embodiments of the present invention; and

FIG. 7 is a cross-sectional view of an exemplary second type of dual-sided integrated circuit chip suitable for use with any of the embodiments of the present invention.

FIG. 1A is a cross-sectional view of a single chip module and FIGS. 1B , 1 C, 1 D and 1 E are a cross-sectional views of multi-chip modules according to a first embodiment of the present invention. In FIG. 1A , a dual-sided integrated circuit chip 100 is physically and electrically attached to a substrate 105 by first solder bumps (also called controlled chip collapse connections, C4s) 110 on a first side of integrated circuit chip 100 and physically and electrically attached to a suprastrate 115 by second solder bumps 120 on a second and opposite side of integrated circuit chip 100 to form a single dual-sided chip module 125 . First and second solder bumps 110 and 120 are connected to chip pads within integrated circuit chip 100 as described infra. Substrate 105 includes one or more wiring layers containing wires 130 embedded in a dielectric matrix or laminate connecting first solder bumps 110 to solder balls 135 which are located on an opposite side of the substrate from the first solder bumps. Solder balls 135 are used to attach module 125 to the next level of packaging of an electronic device. Suprastrate 115 includes one or more wiring layers containing wires 140 embedded in a dielectric matrix or laminate connecting second solder bumps 120 .

Suprastrate 115 thus provides additional integrated circuit wiring capability beyond the wiring layers physical located within integrated circuit chip 100 . In one example, suprastrate 115 interconnects inputs and outputs of different circuits within integrated circuit chip 100 . In one example, suprastrate 115 provides power distribution to different circuits within integrated circuit chip 100 .

Both substrate 105 and suprastrate 115 may comprise single or multiple layers of ceramic or organic based materials with copper or other conductive metal wiring. Examples of organic material includes fiberglass boards (also known as printed circuit boards), flexible circuit carriers and tape automated bonding (TAB) packages. Alternatively, solder balls 135 may be replaced with copper balls, solder columns, pins or lead frames. In one example, solder bumps 110 and 120 and solder balls comprise lead or lead/tin mixtures. Optionally, suprastrate 115 may be provided with a thermal heatsink 150 . In one example, heatsink 150 comprises aluminum.

In FIG. 1B , a multi-dual-sided chip module 125 A differs from single dual-sided chip module 125 of FIG. 1A in that multiple integrated circuit chips 100 are physically and electrically attached to a substrate 105 A and a suprastrate 115 A is physically and electrically attached to the integrated circuit chips.

While three integrated circuit chips 100 are illustrated in FIG. 1B , two or more integrated circuits may be attached to substrate 105 A. While suprastrate 115 A is illustrated in FIG. 1 as attached to all three integrated circuit chips 100 , not all of the integrated circuit chips need be attached to the same suprastrate (see FIG. 1C ) as there may be more than one suprastrate, each suprastrate attached to different sets of integrated circuit chips. Conventional, single-sided integrated circuit chips may be also be physically and electrically attached to substrate 105 A (see FIG. 1D ). While optional heatsink 150 A is illustrated over all three integrated circuit chips 100 , the heatsink may be smaller and placed over selected integrated circuits (see FIG. 1E ).

In FIG. 1C , two of integrated circuit chips 100 are physically and electrically attached to a suprastrate 115 B and one integrated circuit chip 100 is attached to suprastrate 115 . In FIG. 1D , two of integrated circuit chips 100 are physically and electrically attached to a suprastrate 115 B and substrate 105 A and a single sided integrated circuit chip 170 is also attached to substrate 105 A. In FIG. 1E , a heatsink 150 C is attached to suprastrate 115 A over only one (the middle) integrated circuit chip 100 .

FIG. 2 is a cross-sectional view of the wiring levels of an exemplary module substrate according to the embodiments of the present invention. In FIG. 2 , substrate 105 B comprises multiple dielectric layers 151 , 152 , 153 , 154 , 155 , 156 and 157 containing respective lower substrate pads 161 , vias 162 , wires 163 , vias 164 , wires 165 , vias 166 and upper substrate pads 167 providing an electrical connection between first solder bumps 110 and solder balls 135 .

FIG. 3A is a cross-sectional view of a single chip module and FIG. 3B is a cross-sectional view of a multi-chip module according to a second embodiment of the present invention. In FIG. 3A , integrated circuit chip 100 is physically and electrically attached to a top surface 175 A 1 of a first substrate 180 A 1 by first solder bumps 110 . First solder bumps 110 are electrically connected to edge solder bumps 190 A 1 on an edge 190 A 1 of first substrate 180 A 1 by wires 195 A 1 formed in the first substrate. Edge 190 A 1 is adjacent to top surface 175 A 1 . Integrated circuit chip 100 is physically and electrically attached to a top surface 175 B 1 of a second substrate 180 B 1 by second solder bumps 120 . Second solder bumps 120 are electrically connected to edge solder bumps 190 B 1 on an edge 190 B 1 of second substrate 180 B 1 by wires 195 B 1 formed in the second substrate. Edge 190 B 1 is adjacent to top surface 175 B 1 . Edges 190 A 1 and 190 B 1 are coplanar so that edge solder bumps 190 A 1 and 190 B 1 may be attached to a flat surface of a next packaging level, for example, to a printed circuit board.

Attached to bottom surfaces 200 A 1 and 200 B 1 are respective optional heatsinks 205 A 1 and 205 B 1 . Bottom surface 200 A 1 is opposite top surface 175 A 1 and bottom surface 200 B 1 is opposite top surface 175 B 1 .

Both substrates 180 A 1 and 180 B 1 may comprise single or multiple layers of ceramic or organic based materials with copper or other conductive metal wiring. Alternatively, edge solder balls 185 A 1 and 185 B 1 may be replaced with copper balls, solder columns, pins or lead frames. In one example, heatsinks 205 A 1 and 205 B 1 comprise aluminum.

FIG. 3B is similar to FIG. 3A except two integrated circuit chips 100 are attached between first and second substrates 180 B 1 and 180 B 2 . While only two integrated circuit chips are illustrated in FIG. 3B , the second embodiment of the present invention is not limited to two integrated circuit chips.

FIG. 4A is a cross-sectional view of a single chip module and FIGS. 4B and 4C are cross-sectional views of multi-chip modules according to a third embodiment of the present invention. In FIG. 4A , integrated circuit chip 100 is physically and electrically attached to a top surface of a first flexible circuit carrier 210 A by solder bumps 110 . Flexible circuit carrier 210 A includes wires 215 A that electrically connect solder bumps 110 to solder bumps 220 A formed on the top surface of flexible circuit carrier 210 A.

In FIG. 4B , integrated circuit chip 100 is physically and electrically attached to a top surface of a second flexible circuit carrier 210 B by solder bumps 120 . Flexible circuit carrier 210 B includes wires 215 B that electrically connect solder bumps 120 to solder bumps 220 B formed on the top surface of second flexible circuit carrier 210 B.

In FIG. 4C , first and second flexible circuit carriers are 210 A and 210 B are bent away from each other so that solder bumps 220 A and 220 B are coplanar. Solder bumps 220 A and 220 B are then physically and electrically attached to a printed circuit board 225 or another type of electronic substrate. While only one integrated circuit chip 100 is illustrated in FIG. 3C , the dimensions of flexible circuit carriers 210 A and 210 B may be increased to accommodate multiple integrated circuit chips. Optional heatsinks 230 A and 230 B may be attached to first and second flexible circuit carriers 210 A and 210 B respectfully.

In one example, flexible circuit carriers 210 A and 210 B comprise polyimide or another flexible polymer and wires 215 A and 215 B comprise copper, aluminum or gold.

FIG. 5A is a cross-sectional view of a single chip module and FIGS. 5B and 5C are cross-sectional views of multi-chip modules according to a fourth embodiment of the present invention. In FIG. 5A , integrated circuit chip 100 is physically and electrically attached to substrate 105 C by solder bumps 110 on a first side of the integrated circuit chip. Integrated circuit chip 100 is also physically and electrically attached to substrate 105 by wire bonds 235 bonded to bonding pads 240 on a second side and opposite side of integrated circuit chip 100 . In one example, wire bonds 235 are formed from gold or aluminum wire. FIG. 5B is similar to FIG. 5A except multiple integrated circuits 100 are attached to a substrate 105 D. FIG. 5C is similar to FIG. 5B except single sided integrated circuit chip 170 is also attached to a substrate 105 E.

FIG. 6 is a cross-sectional view of an exemplary first type of dual-sided integrated circuit chip 100 suitable for use with any of the embodiments of the present invention. In FIG. 6 , integrated circuit chip 100 includes a buried oxide layer (BOX) 315 formed a single-crystal silicon layer 320 . Formed in silicon layer 320 is trench isolation 325 and source/drains 335 and channel regions 340 of field effect transistors (FETs). Also formed in silicon layer 320 are silicon regions 350 . Formed over channel regions 340 are a gate dielectric (not shown) and gates 345 of FETs as well as a dummy gate 346 . An electrically conductive metal silicide layer 352 is formed on exposed silicon surfaces of source/drains 335 , gates 345 and diffusion contacts 350 . Formed on top of silicon layer 320 is a pre-metal dielectric (PMD) layer 355 . Formed in PMD layer 355 are contacts 360 A and 360 B. Contacts 360 A and 360 B are electrically conductive. Contacts 360 A electrically contact silicide layer 352 on source/drains 335 and on silicon contact 350 . Some of contacts 360 A are dummy contacts extending to trench isolation 325 . Contacts 360 B contact silicide layer 352 on gates 345 and dummy gates 346 . PMD layer 355 and contacts 360 A and 360 B may be considered a wiring level.

Formed on PMD layer 355 is a first inter-level dielectric layer (ILD) 365 including electrically conductive dual-damascene wires 370 in electrical contact with contacts 360 A and 360 B. Formed on ILD 365 is a second ILD 380 including electrically conductive dual-damascene wires 380 in electrical contact with wires 370 . Formed on ILD 375 is a third ILD 385 including electrically conductive dual-damascene I/O and power pads 390 in electrical contact with wires 380 .

A dielectric passivation layer 395 is formed on third ILD 385 and I/O and power pads 390 . Electrically conductive first type contacts 405 are formed through BOX 315 and silicon layer 320 . Contacts 405 extend from the top surface of BOX 315 to silicide layer 352 on source/drains 335 and silicon contact 350 . Electrically conductive second type contacts 410 are formed through BOX 315 and trench isolation 325 . Contacts 410 extend from the top surface of BOX 315 to silicide layer 352 on dummy gate 346 and to selected contacts 360 A. In the case of dummy gate 346 , contact 410 extends through the gate dielectric layer (not shown) as well.

Formed on BOX 315 is first inter-level dielectric layer (ILD) 365 A including electrically conductive dual-damascene wires 370 A in electrical contact with contacts 360 A. Formed on ILD 365 A is second ILD 380 A including electrically conductive dual-damascene wires 380 A in electrical contact with wires 370 A. Formed on ILD 375 A is third ILD 385 A including electrically conductive dual-damascene I/O and power pads 390 A in electrical contact with wires 380 A. A dielectric passivation layer 395 A is formed on third ILD 385 A and I/O and power pads 390 A.

An electrically conductive passivation layer 415 is formed over I/O and power pads 390 through openings in dielectric passivation layer 395 and solder bumps 110 are formed over electrically conductive passivation layer 415 . An electrically conductive passivation layer 415 A is formed over I/O and power pads 390 A through openings in dielectric passivation layer 395 A and solder bumps 120 are formed over electrically conductive passivation layer 415 A.

FIG. 7 is a cross-sectional view of an exemplary second type of dual-sided integrated circuit chip 100 suitable for use with any of the embodiments of the present invention. Integrated circuit chip 100 , includes a first buried oxide layer (BOX) 315 formed on the silicon substrate and a first single-crystal silicon layer 320 formed on BOX 315 . Formed in silicon layer 320 is a first trench isolation 325 and source/drains 335 and channel regions 340 of field effect transistors. Also formed in silicon layer 320 are silicon regions 350 . Formed over channel regions 340 are a gate dielectric (not shown) and gates 345 of FETs. A metal silicide layer 352 is formed on exposed silicon surfaces of source/drains 335 , gates 345 and diffusion contacts 350 .

Formed on top of silicon layer 320 is a first PMD layer 355 . Formed in PMD layer 355 are contacts 360 . Contacts 360 are electrically conductive and electrically contact source/drains 335 , gates 345 and silicon contact 350 . PMD layer 355 and contacts 360 may be considered a wiring level. Formed on PMD layer 355 is a first inter-level dielectric layer (ILD) 365 including electrically conductive dual-damascene wires 370 in electrical contact with contacts 360 . Formed on ILD 365 is a second ILD 380 including electrically conductive dual-damascene wires 380 in electrical contact with wires 370 . Formed on ILD 375 is a third ILD 385 including electrically conductive dual-damascene I/O and power pads 390 in electrical contact with wires 380 .

Integrated circuit chip 100 , also includes a second buried oxide layer (BOX) 315 A formed on first BOX layer 315 and a second single-crystal silicon layer 320 A formed on BOX layer 315 A. Formed in silicon layer 320 A is a second trench isolation 325 A and source/drains 336 and channel regions 341 of field effect transistors. Formed over channel regions 341 are a gate dielectric (not shown) and gates 346 of FETs. A metal silicide layer 352 A is formed on exposed silicon surfaces of source/drains 366 and gates 346 .

Formed on top of silicon layer 320 A is a second PMD layer 355 A. Formed in PMD layer 355 A are contacts 360 A. Contacts 360 A are electrically conductive and electrically contact source/drains 336 , gates 346 and silicon contact 350 A. PMD layer 355 A and contacts 360 A may be considered a wiring level. Formed on PMD layer 355 A is a fourth ILD 365 A including electrically conductive dual-damascene wires 370 A in electrical contact with contacts 360 A. Formed on ILD 365 A is a fifth ILD 380 A including electrically conductive dual-damascene wires 380 A in electrical contact with wires 370 A. Formed on ILD 375 A is a sixth ILD 385 A including electrically conductive dual-damascene I/O and power pads 390 A in electrical contact with wires 380 A.

Electrically conductive passivation layer 415 is formed over I/O and power pads 390 through openings in dielectric passivation layer 395 and solder bumps 110 are formed over electrically conductive passivation layer 415 . Electrically conductive passivation layer 415 A is formed over I/O and power pads 390 A through openings in dielectric passivation layer 395 A and solder bumps 120 are formed over electrically conductive passivation layer 415 A.

Thus the embodiments of the present invention provide integrated circuit devices with increased wiring capability.

The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention.

For, example, in the various embodiments of the present invention, the dual-sided integrated circuits may be arranged out in a single row or column or may be in a two dimensional array of two or more rows and two or more columns.

Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.