Inventor

Mark D. Jaffe

Inventor
Shelburne, VT, US

Overview

156→
Patents
1998–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 156 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
H10DInorganic electric semiconductor devices14%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation13%
H01LSemiconductor devices13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
G06FElectric digital data processing5%
H03HImpedance networks, e.g. resonant circuits4%
Y10TTechnical subjects covered by former us classification4%
G02BOptical elements, systems or apparatus3%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution3%
PatentTitleYear
10,964,840Photodiode structures202110,896,992Photodiode structures202110,790,190Backside contact to a final substrate202010,712,498Shielding structures between optical waveguides202010,692,753Semiconductor structure with airgap202010,629,482Backside contact to a final substrate202010,622,506Photodiode structures202010,615,302Photodiode structures202010,573,554Backside contact to a final substrate202010,566,235Backside contact to a final substrate202010,559,743Backside integration of RF filters for RF front end modules and design structure202010,453,987Photodiode structures201910,424,686Photodiode structures201910,361,123Backside contact to a final substrate201910,277,188Switchable filters and design structures201910,224,280Backside device contact201910,211,146Air gap over transistor gate and related method201910,211,087Semiconductor structure with airgap201910,191,213Shielding structures between optical waveguides201910,170,418Backside device contact201910,164,597Switchable filters and design structures201810,164,101Transistor with improved channel mobility201810,164,596Switchable filters and design structures201810,157,838Backside device contact201810,157,777Air gap over transistor gate and related method201810,141,472Photodiode structures201810,079,248Field-effect transistors with a buried body contact201810,074,561Backside contact to a final substrate201810,050,171Photodiode structures201810,037,911Device layer transfer with a preserved handle wafer section201810,020,789Switchable filters and design structures20189,978,849SOI-MOSFET gate insulation layer with different thickness20189,935,600Switchable filters and design structures20189,917,005'Semiconductor structure with airgap'20189,887,156'Backside device contact'20189,852,944Backside contact to a final substrate20179,843,303'Switchable filters and design structures'20179,818,637'Device layer transfer with a preserved handle wafer section'20179,786,835'Backside integration of RF filters for RF front end modules and design structure'20179,740,080'Waveguide switch with tuned photonic microring'20179,728,838'On chip antenna with opening'20179,673,220'Chip structures with distributed wiring'20179,666,475'Semiconductor structure with airgap'20179,633,894'Semiconductor structure with airgap'20179,627,575'Photodiode structures'20179,543,356'Pixel sensor cell including light shield'20179,514,987'Backside contact to final substrate'20169,455,187'Backside device contact'20169,385,022'Silicon waveguide on bulk silicon substrate and methods of forming'20169,349,793'Semiconductor structure with airgap'20169,300,272'Tunable filter structures and design structures'20169,252,733'Switchable filters and design structures'20169,225,311'Method of manufacturing switchable filters'20159,214,561'Thin body switch transistor'20159,171,971'Encapsulated sensors'20159,165,819'High linearity SOI wafer for low-distortion circuit applications'20159,099,982'Method of manufacturing switching filters and design structures'20159,058,455'Backside integration of RF filters for RF front end modules and design structure'20159,054,671'Tunable filter structures and design structures'20159,048,809'Method of manufacturing switchable filters'20159,002,156'Vertically curved waveguide'20158,987,067'Segmented guard ring structures with electrically insulated gap structures and design structures thereof'20158,963,293'High resistivity silicon-on-insulator substrate and method of forming'20158,951,896'High linearity SOI wafer for low-distortion circuit applications'20158,910,355'Method of manufacturing a film bulk acoustic resonator with a loading element'20148,903,210'Vertical bend waveguide coupler for photonics applications'20148,828,746'Compensation for a charge in a silicon substrate'20148,796,130'Diffusion barrier for oppositely doped portions of gate conductor'20148,796,057'Isolation structures for global shutter imager pixel, methods of manufacture and design structures'20148,741,739'High resistivity silicon-on-insulator substrate and method of forming'20148,729,664'Discontinuous guard ring'20148,723,392'Saw filter having planar barrier layer and method of making'20148,689,152'Double-sided integrated circuit chips'20148,681,254'Methods for enhancing quality of pixel sensor image frames for global shutter imaging'20148,618,588'Anti-blooming pixel sensor cell with active neutral density filter, methods of manufacture, and design structure'20138,536,035'Silicon-on-insulator substrate and method of forming'20138,507,962'Isolation structures for global shutter imager pixel, methods of manufacture and design structures'20138,492,272'Passivated through wafer vias in low-doped semiconductor substrates'20138,471,306'Double-sided integrated circuit chips'20138,440,490'CMOS imager photodiode with enhanced capacitance'20138,421,126'Double-sided integrated circuit chips'20138,409,899'Delamination and crack resistant image sensor structures and methods'20138,384,690'Interface device with integrated solar cell(S) for power collection'20138,233,070'Variable dynamic range pixel sensor cell, design structure and method'20128,232,651'Bond pad for wafer and package for CMOS imager'20128,232,190'Three dimensional vertical E-fuse structures and methods of manufacturing the same'20128,168,474'Self-dicing chips using through silicon vias'20128,158,453'Methods of forming silicide strapping in imager transfer gate device'20128,138,531'Structures, design structures and methods of fabricating global shutter pixel sensor cells'20128,119,456'Bond pad for wafer and package for CMOS imager'20128,106,432'CMOS imager photodiode with enhanced capacitance'20128,077,240'Methods for enhancing quality of pixel sensor image frames for global shutter imaging'20118,039,875'Structure for pixel sensor cell that collects electrons and holes'20118,034,699'Isolation with offset deep well implants'20118,023,021'High efficiency CMOS image sensor pixel employing dynamic voltage supply'20118,013,342'Double-sided integrated circuit chips'20118,015,514'Random personalization of chips during fabrication'20118,004,289'Wafer-to-wafer alignments'20117,989,312'Double-sided integrated circuit chips'20117,977,711'Pixel sensor cell for collecting electrons and holes'20117,964,967'High surface area aluminum bond pad for through-wafer connections to an electronic package'20117,960,245'Dual wired integrated circuit chips'20117,939,914'Dual wired integrated circuit chips'20117,928,527'Delamination and crack resistant image sensor structures and methods'20117,915,056'Image sensor monitor structure in scribe area'20117,863,734'Dual-sided chip attached modules'20117,825,416'Image sensor including spatially different active and dark pixel interconnect patterns'20107,824,961'Stacked imager package'20107,821,553'Pixel array, imaging sensor including the pixel array and digital camera including the imaging sensor'20107,781,781'CMOS imager array with recessed dielectric'20107,772,028'CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom'20107,732,841'Pixel sensor cell for collecting electrons and holes'20107,719,118'Semiconductor chip scale package incorporating through-vias electrically connected to a substrate and other vias that are isolated from the substrate, and method of forming the package'20107,675,097'Silicide strapping in imager transfer gate device'20107,670,927'Double-sided integrated circuit chips'20107,659,564'CMOS imager photodiode with enhanced capacitance'20107,655,966'High efficiency CMOS image sensor pixel employing dynamic voltage supply'20107,655,495'Damascene copper wiring optical image sensor'20107,633,042'Pixel sensor cell having a pinning layer surrounding collection well regions for collecting electrons and holes'20097,633,106'Light shield for CMOS imager'20097,622,364'Bond pad for wafer and package for CMOS imager'20097,586,139'Photo-sensor and pixel array with backside illumination and method of forming the photo-sensor'20097,572,701'Recessed gate for a CMOS image sensor'20097,563,636'Method of forming a pixel sensor cell for collecting electrons and holes'20097,538,373'Body potential imager cell'20097,537,951'Image sensor including spatially different active and dark pixel interconnect patterns'20097,531,392'Multi-orientation semiconductor-on-insulator (SOI) substrate, and method of fabricating same'20097,528,427'Pixel sensor cell having asymmetric transfer gate with reduced pinning layer barrier potential'20097,521,798'Stacked imager package'20097,517,806'Integrated circuit having pairs of parallel complementary FinFETs'20097,491,992'Image sensor cells'20097,492,048'CMOS sensors having charge pushing regions'20097,491,561'Pixel sensor having doped isolation structure sidewall'20097,462,509'Dual-sided chip attached modules'20087,459,360'Method of forming pixel sensor cell having reduced pinning layer barrier potential'20087,439,561'Pixel sensor cell for collecting electrons and holes'20087,381,627'Dual wired integrated circuit chips'20087,361,989'Stacked imager package'20087,361,581'High surface area aluminum bond pad for through-wafer connections to an electronic package'20087,342,268'CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom'20087,285,477'Dual wired integrated circuit chips'20077,276,748'Body potential imager cell'20077,217,968'Recessed gate for an image sensor'20077,205,591'Pixel sensor cell having reduced pinning layer barrier potential and method thereof'20077,205,627'Image sensor cells'20077,193,289'Damascene copper wiring image sensor'20077,194,706'Designing scan chains with specific parameter sensitivities to identify process defects'20077,193,423'Wafer-to-wafer alignments'20077,141,836'Pixel sensor having doped isolation structure sidewall'20067,132,339'Transistor structure with thick recessed source/drain structures and fabrication process of same'20067,098,067'Masked sidewall implant for image sensor'20066,943,405'Integrated circuit having pairs of parallel complementary FinFETs'20056,870,225'Transistor structure with thick recessed source/drain structures and fabrication process of same'20056,394,638'Trench isolation for active areas and first level conductors'20026,063,687'Formation of trench isolation for active areas and first level conductors'20005,734,192'Trench isolation for active areas and first level conductors'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2021Patents assigned to IBM (140)· patent assignee history
1998–2002Based in Colchester, VT, US· patent location history
2005–2021Based in Shelburne, VT, US· patent location history
2011–2017Patents assigned to JAFFE MARK D (27)· patent assignee history
2012–2017Patents assigned to GAMBINO JEFFREY P (15)· patent assignee history
2012–2015Patents assigned to ADKISSON JAMES W (14)· patent assignee history
2015–2020Patents assigned to GLOBALFOUNDRIES INC (19)· patent assignee history
2017–2018Based in Essex Junction, VT, US· patent location history
2017Based in Shelbourne, VT, US· patent location history
2017Based in Selburne, VT, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM1401998–2021
JAFFE MARK Dself272011–2017
GLOBALFOUNDRIES INC192015–2020
GAMBINO JEFFREY P152012–2017
ADKISSON JAMES W142012–2015
Locations
LocationPatentsSpan
Shelburne, VT, US1452005–2021
Essex Junction, VT, US32017–2018
Colchester, VT, US31998–2002
Shelbourne, VT, US22017
Selburne, VT, US12017